| Age | Commit message (Expand) | Author |
|---|
| 2021-06-07 | Updated the board with the new footprints to correct the fabrication layers. | Pavel V. Shatov (Meister) |
| 2021-06-07 | Repaired fabrication layers for all the footprints. These are used to generate | Pavel V. Shatov (Meister) |
| 2021-06-03 | Updated the board with the new power jack footprint. | Pavel V. Shatov (Meister) |
| 2021-06-03 | Fixed power jack footprint (0.8x3.0 oval holes turned 0.8 circular after | Pavel V. Shatov (Meister) |
| 2020-09-23 | Don't track .xml and .csv files. These are the raw and parsed BOM lists. | Pavel V. Shatov (Meister) |
| 2020-09-23 | Apparently this is the companion of the .dcm, so will commit just in case: | Pavel V. Shatov (Meister) |
| 2020-09-23 | No idea where the this .dcm came from and whether it would be safe to delete it, | Pavel V. Shatov (Meister) |
| 2020-09-23 | Forgot to commit the footprint for newly added voltage regulators. | Pavel V. Shatov (Meister) |
| 2020-09-23 | Finished BOM overhaul. All the discrete components should have proper tolerance | Pavel V. Shatov (Meister) |
| 2020-09-23 | Okay, capacitor parameters (tolerance, rated voltage, dielectric) were lost | Pavel V. Shatov (Meister) |
| 2020-09-23 | Turns out things were even worse, since resistor tolerance values apparently | Pavel V. Shatov (Meister) |
| 2020-09-23 | First attempt at automatic BOM export failed. Turns out some of the components | Pavel V. Shatov (Meister) |
| 2020-09-23 | Cleaned up silkscreen, this was mostly about re-arranging component names to | Pavel V. Shatov (Meister) |
| 2020-09-23 | Doing some final polishing, added the "Open Source Hardware" logo I removed | Pavel V. Shatov (Meister) |
| 2020-09-23 | Finished cleanup, fixed all pcbnew DRC errors reported. First attempt at | Pavel V. Shatov (Meister) |
| 2020-09-23 | Renamed schematics sheets for consistency. | Pavel V. Shatov (Meister) |
| 2020-09-23 | Finishing cleanup. Fixed schematics DRC errors (mostly missing NC flags on some | Pavel V. Shatov (Meister) |
| 2020-09-23 | Did some cleanup, also had to re-route VCC_PLL for iCE40. | Pavel V. Shatov (Meister) |
| 2020-09-23 | Entirely routed the design. Not useable right now, so far just reports zero | Pavel V. Shatov (Meister) |
| 2020-09-23 | Intermediate step, re-routing the design according to the changes in schematics. | Pavel V. Shatov (Meister) |
| 2020-09-23 | Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGA | Pavel V. Shatov (Meister) |
| 2020-09-23 | Continued doing edits. Removed AVR tiny tamper detection processor. | Pavel V. Shatov (Meister) |
| 2020-09-23 | Started editing the design. So far removed the old MKM component. | Pavel V. Shatov (Meister) |
| 2020-09-23 | Forward annotation (eeschema -> pcbnew) is now FULLY OPERATIONAL! Hoorah! | Pavel V. Shatov (Meister) |
| 2020-09-23 | Turns out multi-part components were not fully converted and were not | Pavel V. Shatov (Meister) |
| 2020-09-23 | Fixed PCB footprint references. Basically had to just replace dashes with | Pavel V. Shatov (Meister) |
| 2020-09-23 | Initial project cleanup | Pavel V. Shatov (Meister) |
| 2020-05-25 | Internal ground layers OK. | Pavel V. Shatov (Meister) |
| 2020-05-25 | Bottom Layer OK | Pavel V. Shatov (Meister) |
| 2020-05-25 | Internal signal layer #2 cleaned up. | Pavel V. Shatov (Meister) |
| 2020-05-25 | Internal signal layer #1 cleaned up. | Pavel V. Shatov (Meister) |
| 2020-05-11 | Top (aka "Front") Layer OK | Pavel V. Shatov (Meister) |
| 2020-05-11 | Don't track autosave files | Pavel V. Shatov (Meister) |
| 2020-05-11 | Tweak gitignore | Pavel V. Shatov (Meister) |
| 2020-04-23 | Don't track Gerber output. | Pavel V. Shatov (Meister) |
| 2020-04-23 | Copy of rev.04 project as-is after Fredrik's conversion script. | Pavel V. Shatov (Meister) |
