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AgeCommit message (Expand)Author
2021-06-07Discrete 0402 and 0603 packages had too small font on the fabrication layer,Pavel V. Shatov (Meister)
2021-06-07Updated the board with the new footprints to correct the fabrication layers.Pavel V. Shatov (Meister)
2021-06-07Repaired fabrication layers for all the footprints. These are used to generatePavel V. Shatov (Meister)
2021-06-03Updated the board with the new power jack footprint.Pavel V. Shatov (Meister)
2021-06-03Fixed power jack footprint (0.8x3.0 oval holes turned 0.8 circular afterPavel V. Shatov (Meister)
2020-09-23Don't track .xml and .csv files. These are the raw and parsed BOM lists.Pavel V. Shatov (Meister)
2020-09-23Apparently this is the companion of the .dcm, so will commit just in case:Pavel V. Shatov (Meister)
2020-09-23No idea where the this .dcm came from and whether it would be safe to delete it,Pavel V. Shatov (Meister)
2020-09-23Forgot to commit the footprint for newly added voltage regulators.Pavel V. Shatov (Meister)
2020-09-23Finished BOM overhaul. All the discrete components should have proper tolerancePavel V. Shatov (Meister)
2020-09-23Okay, capacitor parameters (tolerance, rated voltage, dielectric) were lostPavel V. Shatov (Meister)
2020-09-23Turns out things were even worse, since resistor tolerance values apparentlyPavel V. Shatov (Meister)
2020-09-23First attempt at automatic BOM export failed. Turns out some of the componentsPavel V. Shatov (Meister)
2020-09-23Cleaned up silkscreen, this was mostly about re-arranging component names toPavel V. Shatov (Meister)
2020-09-23Doing some final polishing, added the "Open Source Hardware" logo I removedPavel V. Shatov (Meister)
2020-09-23Finished cleanup, fixed all pcbnew DRC errors reported. First attempt atPavel V. Shatov (Meister)
2020-09-23Renamed schematics sheets for consistency.Pavel V. Shatov (Meister)
2020-09-23Finishing cleanup. Fixed schematics DRC errors (mostly missing NC flags on somePavel V. Shatov (Meister)
2020-09-23Did some cleanup, also had to re-route VCC_PLL for iCE40.Pavel V. Shatov (Meister)
2020-09-23Entirely routed the design. Not useable right now, so far just reports zeroPavel V. Shatov (Meister)
2020-09-23Intermediate step, re-routing the design according to the changes in schematics.Pavel V. Shatov (Meister)
2020-09-23Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGAPavel V. Shatov (Meister)
2020-09-23Continued doing edits. Removed AVR tiny tamper detection processor.Pavel V. Shatov (Meister)
2020-09-23Started editing the design. So far removed the old MKM component.Pavel V. Shatov (Meister)
2020-09-23Forward annotation (eeschema -> pcbnew) is now FULLY OPERATIONAL! Hoorah!Pavel V. Shatov (Meister)
2020-09-23Turns out multi-part components were not fully converted and were notPavel V. Shatov (Meister)
2020-09-23Fixed PCB footprint references. Basically had to just replace dashes withPavel V. Shatov (Meister)
2020-09-23Initial project cleanupPavel V. Shatov (Meister)
2020-05-25Internal ground layers OK.Pavel V. Shatov (Meister)
2020-05-25Bottom Layer OKPavel V. Shatov (Meister)
2020-05-25Internal signal layer #2 cleaned up.Pavel V. Shatov (Meister)
2020-05-25Internal signal layer #1 cleaned up.Pavel V. Shatov (Meister)
2020-05-11Top (aka "Front") Layer OKPavel V. Shatov (Meister)
2020-05-11Don't track autosave filesPavel V. Shatov (Meister)
2020-05-11Tweak gitignorePavel V. Shatov (Meister)
2020-04-23Don't track Gerber output.Pavel V. Shatov (Meister)
2020-04-23Copy of rev.04 project as-is after Fredrik's conversion script.Pavel V. Shatov (Meister)