Age | Commit message (Collapse) | Author | |
---|---|---|---|
2020-09-23 | Finishing cleanup. Fixed schematics DRC errors (mostly missing NC flags on some | Pavel V. Shatov (Meister) | |
of the pins of the newly added componets). Also updated pages to show "rev.04", not "rev.02" | |||
2020-09-23 | Entirely routed the design. Not useable right now, so far just reports zero | Pavel V. Shatov (Meister) | |
unrouted nets. Will cleanup next. | |||
2020-09-23 | Intermediate step, re-routing the design according to the changes in schematics. | Pavel V. Shatov (Meister) | |
2020-09-23 | Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGA | Pavel V. Shatov (Meister) | |
along with it's power subsystem and programming circuitry. | |||
2020-09-23 | Turns out multi-part components were not fully converted and were not | Pavel V. Shatov (Meister) | |
recognized properly during forward annotation. Had to do a couple of experiments to figure out how KiCAD handles this and then write some quick and dirty scripts to repair the multi-part symbols (STM32, Artix-7 and the 74_244 logic buffer were affected). | |||
2020-04-23 | Copy of rev.04 project as-is after Fredrik's conversion script. | Pavel V. Shatov (Meister) | |