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2021-07-20Added LICENSE file to Alpha rev.04 KiCAD design project.HEADmasterPavel V. Shatov (Meister)
2021-06-07Regenerated assembly drawings with increased font size.Pavel V. Shatov (Meister)
2021-06-07Updated the board with the fixed footprints.Pavel V. Shatov (Meister)
2021-06-07Discrete 0402 and 0603 packages had too small font on the fabrication layer,Pavel V. Shatov (Meister)
increased to make it readable.
2021-06-07Added the generated assembly drawings.Pavel V. Shatov (Meister)
2021-06-07Added assembly drawings support to the production package generator script.Pavel V. Shatov (Meister)
2021-06-07Updated the board with the new footprints to correct the fabrication layers.Pavel V. Shatov (Meister)
2021-06-07Repaired fabrication layers for all the footprints. These are used to generatePavel V. Shatov (Meister)
assembly drawings needed for soldering. As it turned out, component outlines got imported just as a set of lines from Altium, without linking them to the actual component. Moreover, reference designators didn't get converted altogether, had to add them manually.
2021-06-03Regenerated NC Drill with the fixed power jack footprint.Pavel V. Shatov (Meister)
2021-06-03Updated the board with the new power jack footprint.Pavel V. Shatov (Meister)
2021-06-03Fixed power jack footprint (0.8x3.0 oval holes turned 0.8 circular afterPavel V. Shatov (Meister)
exporting from Altium). Did the fix long time ago, just forgot to commit.
2020-09-23Bundle with production filesPavel V. Shatov (Meister)
2020-09-23Use this script to generate a bundle of files required for board production.Pavel V. Shatov (Meister)
First, use pcbnew to plot Gerbers and NC Drill, then export BOM (install the custom plugin from helper/ first) and generate footprint position files. When run the script will automatically assemble everything in ./ProductionFiles_rev04/
2020-09-23Board stackup. Give to your board manufacturer along with Gerbers.Pavel V. Shatov (Meister)
2020-09-23Design tech parameters. Can be used to fill out your assembly house board ↵Pavel V. Shatov (Meister)
order form.
2020-09-23Don't track .xml and .csv files. These are the raw and parsed BOM lists.Pavel V. Shatov (Meister)
KiCAD's BOM generation is very limited, so I wrote a helper script to generate a more production-friendly BOM variant, see next commit.
2020-09-23KiCAD plugin to allow better BOM generation.Pavel V. Shatov (Meister)
2020-09-23Apparently this is the companion of the .dcm, so will commit just in case:Pavel V. Shatov (Meister)
".bck: backup file for the symbol editor of the .dcm file." https://kicad-pcb.org/help/file-formats/
2020-09-23No idea where the this .dcm came from and whether it would be safe to delete it,Pavel V. Shatov (Meister)
so committing just in case.
2020-09-23Forgot to commit the footprint for newly added voltage regulators.Pavel V. Shatov (Meister)
2020-09-23Forgot to commit the script I wrote to help repair forward annotation,Pavel V. Shatov (Meister)
basically it just scans schematics pages and the PCB file and then recreates the mapping between schematic component and PCB component based on KiCAD's "unique ID" and "sheet ID".
2020-09-23Sorting out all the files currently not tracked by Git. First, don't track myPavel V. Shatov (Meister)
own project backups.
2020-09-23Finished BOM overhaul. All the discrete components should have proper tolerancePavel V. Shatov (Meister)
and other parameters. All the other components should have partnumbers and manufacturers associated. Did some polishing to the PCB after feedback from the assembly house. KiCAD was for some reason breaking the "neck" between two copper islands in a couple of places. This was happening in two places on Layer 3 and three places on Layer 6, easily fixed by hand.
2020-09-23Okay, capacitor parameters (tolerance, rated voltage, dielectric) were lostPavel V. Shatov (Meister)
too. This is too painful to type in manually, so I created a simple script to make all the capacitors 10% 50V X7R. This way I can then manually edit those, that differ.
2020-09-23Turns out things were even worse, since resistor tolerance values apparentlyPavel V. Shatov (Meister)
were lost during conversion. Doing one more overhaul to restore the lost pieces of information.
2020-09-23First attempt at automatic BOM export failed. Turns out some of the componentsPavel V. Shatov (Meister)
didn't have partnumbers attached for some reason (?). Doing an overhaul.
2020-09-23Cleaned up silkscreen, this was mostly about re-arranging component names toPavel V. Shatov (Meister)
not cover footprints. As far as I understand, the problem was that KiCAD uses a different font than Altium, so component RefDes' got distorted a bit during conversion. _14.cleaned_up_silkscreen_maybe_need_script_to_reattach
2020-09-23Doing some final polishing, added the "Open Source Hardware" logo I removedPavel V. Shatov (Meister)
earlier while trying to repair forward annotation.
2020-09-23Finished cleanup, fixed all pcbnew DRC errors reported. First attempt atPavel V. Shatov (Meister)
generating Gerbers. The result is somewhat surprising, since each Gerber is huge (10MB+). This turned out to be related to the way KiCAD fills copper polygons. Version 5.1.x that I use has support for some better pouring algorithm, while the 4.x version Fredrik used at the time of conversion had some different and obviously inferior pouring algorithm. I updated all the shapes to use the newer fill algorithm and this helped a bit, but didn't entirely solve the problem. Internal layers with large planes still produce very large Gerbers (~1MB), but they're more or less manageable now. Further research indicates there currently seems to be no way of further reducing Gerbers, see eg.: https://forum.kicad.info/t/gerber-files-are-too-large-due-to-thousands-of-drawn-features/17750
2020-09-23Renamed schematics sheets for consistency.Pavel V. Shatov (Meister)
2020-09-23Finishing cleanup. Fixed schematics DRC errors (mostly missing NC flags on somePavel V. Shatov (Meister)
of the pins of the newly added componets). Also updated pages to show "rev.04", not "rev.02"
2020-09-23Did some cleanup, also had to re-route VCC_PLL for iCE40.Pavel V. Shatov (Meister)
2020-09-23Entirely routed the design. Not useable right now, so far just reports zeroPavel V. Shatov (Meister)
unrouted nets. Will cleanup next.
2020-09-23Intermediate step, re-routing the design according to the changes in schematics.Pavel V. Shatov (Meister)
2020-09-23Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGAPavel V. Shatov (Meister)
along with it's power subsystem and programming circuitry.
2020-09-23Continued doing edits. Removed AVR tiny tamper detection processor.Pavel V. Shatov (Meister)
2020-09-23Started editing the design. So far removed the old MKM component.Pavel V. Shatov (Meister)
2020-09-23Forward annotation (eeschema -> pcbnew) is now FULLY OPERATIONAL! Hoorah!Pavel V. Shatov (Meister)
2020-09-23Turns out multi-part components were not fully converted and were notPavel V. Shatov (Meister)
recognized properly during forward annotation. Had to do a couple of experiments to figure out how KiCAD handles this and then write some quick and dirty scripts to repair the multi-part symbols (STM32, Artix-7 and the 74_244 logic buffer were affected).
2020-09-23Fixed PCB footprint references. Basically had to just replace dashes withPavel V. Shatov (Meister)
underscores.
2020-09-23Initial project cleanupPavel V. Shatov (Meister)
2020-05-25Internal ground layers OK.Pavel V. Shatov (Meister)
2020-05-25Bottom Layer OKPavel V. Shatov (Meister)
2020-05-25Internal signal layer #2 cleaned up.Pavel V. Shatov (Meister)
2020-05-25Internal signal layer #1 cleaned up.Pavel V. Shatov (Meister)
2020-05-11Top (aka "Front") Layer OKPavel V. Shatov (Meister)
2020-05-11Don't track autosave filesPavel V. Shatov (Meister)
2020-05-11Tweak gitignorePavel V. Shatov (Meister)
2020-04-23Layer info.Pavel V. Shatov (Meister)
2020-04-23Don't track Gerber output.Pavel V. Shatov (Meister)
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 20:41:05 +0000