| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-09-23 | Doing some final polishing, added the "Open Source Hardware" logo I removed | Pavel V. Shatov (Meister) | |
| earlier while trying to repair forward annotation. | |||
| 2020-09-23 | Finished cleanup, fixed all pcbnew DRC errors reported. First attempt at | Pavel V. Shatov (Meister) | |
| generating Gerbers. The result is somewhat surprising, since each Gerber is huge (10MB+). This turned out to be related to the way KiCAD fills copper polygons. Version 5.1.x that I use has support for some better pouring algorithm, while the 4.x version Fredrik used at the time of conversion had some different and obviously inferior pouring algorithm. I updated all the shapes to use the newer fill algorithm and this helped a bit, but didn't entirely solve the problem. Internal layers with large planes still produce very large Gerbers (~1MB), but they're more or less manageable now. Further research indicates there currently seems to be no way of further reducing Gerbers, see eg.: https://forum.kicad.info/t/gerber-files-are-too-large-due-to-thousands-of-drawn-features/17750 | |||
| 2020-09-23 | Renamed schematics sheets for consistency. | Pavel V. Shatov (Meister) | |
| 2020-09-23 | Finishing cleanup. Fixed schematics DRC errors (mostly missing NC flags on some | Pavel V. Shatov (Meister) | |
| of the pins of the newly added componets). Also updated pages to show "rev.04", not "rev.02" | |||
| 2020-09-23 | Did some cleanup, also had to re-route VCC_PLL for iCE40. | Pavel V. Shatov (Meister) | |
| 2020-09-23 | Entirely routed the design. Not useable right now, so far just reports zero | Pavel V. Shatov (Meister) | |
| unrouted nets. Will cleanup next. | |||
| 2020-09-23 | Intermediate step, re-routing the design according to the changes in schematics. | Pavel V. Shatov (Meister) | |
| 2020-09-23 | Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGA | Pavel V. Shatov (Meister) | |
| along with it's power subsystem and programming circuitry. | |||
| 2020-09-23 | Continued doing edits. Removed AVR tiny tamper detection processor. | Pavel V. Shatov (Meister) | |
| 2020-09-23 | Started editing the design. So far removed the old MKM component. | Pavel V. Shatov (Meister) | |
| 2020-09-23 | Forward annotation (eeschema -> pcbnew) is now FULLY OPERATIONAL! Hoorah! | Pavel V. Shatov (Meister) | |
| 2020-09-23 | Turns out multi-part components were not fully converted and were not | Pavel V. Shatov (Meister) | |
| recognized properly during forward annotation. Had to do a couple of experiments to figure out how KiCAD handles this and then write some quick and dirty scripts to repair the multi-part symbols (STM32, Artix-7 and the 74_244 logic buffer were affected). | |||
| 2020-09-23 | Fixed PCB footprint references. Basically had to just replace dashes with | Pavel V. Shatov (Meister) | |
| underscores. | |||
| 2020-09-23 | Initial project cleanup | Pavel V. Shatov (Meister) | |
| 2020-05-25 | Internal ground layers OK. | Pavel V. Shatov (Meister) | |
| 2020-05-25 | Bottom Layer OK | Pavel V. Shatov (Meister) | |
| 2020-05-25 | Internal signal layer #2 cleaned up. | Pavel V. Shatov (Meister) | |
| 2020-05-25 | Internal signal layer #1 cleaned up. | Pavel V. Shatov (Meister) | |
| 2020-05-11 | Top (aka "Front") Layer OK | Pavel V. Shatov (Meister) | |
| 2020-05-11 | Don't track autosave files | Pavel V. Shatov (Meister) | |
| 2020-05-11 | Tweak gitignore | Pavel V. Shatov (Meister) | |
| 2020-04-23 | Layer info. | Pavel V. Shatov (Meister) | |
| 2020-04-23 | Don't track Gerber output. | Pavel V. Shatov (Meister) | |
| 2020-04-23 | Copy of rev.04 project as-is after Fredrik's conversion script. | Pavel V. Shatov (Meister) | |
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index : user/shatov/alpha_rev04 | |
| Unnamed repository; edit this file 'description' to name the repository. | git repositories |
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