diff options
Diffstat (limited to 'KiCAD')
| -rw-r--r-- | KiCAD/Cryptech Alpha.kicad_pcb | 19127 | ||||
| -rw-r--r-- | KiCAD/fp-info-cache | 2 |
2 files changed, 9591 insertions, 9538 deletions
diff --git a/KiCAD/Cryptech Alpha.kicad_pcb b/KiCAD/Cryptech Alpha.kicad_pcb index cb40d20..549f954 100644 --- a/KiCAD/Cryptech Alpha.kicad_pcb +++ b/KiCAD/Cryptech Alpha.kicad_pcb @@ -2,7 +2,7 @@ (general (thickness 1.6) - (drawings 3565) + (drawings 3618) (tracks 9265) (zones 0) (modules 404) @@ -11,7 +11,7 @@ (page A4) (layers - (0 F.Cu signal) + (0 F.Cu signal hide) (1 In1.Cu power hide) (2 In2.Cu mixed hide) (3 In3.Cu power hide) @@ -24,18 +24,18 @@ (34 B.Paste user hide) (35 F.Paste user hide) (36 B.SilkS user hide) - (37 F.SilkS user) + (37 F.SilkS user hide) (38 B.Mask user hide) (39 F.Mask user hide) (40 Dwgs.User user hide) (41 Cmts.User user hide) (42 Eco1.User user hide) (43 Eco2.User user hide) - (44 Edge.Cuts user hide) + (44 Edge.Cuts user) (45 Margin user hide) (46 B.CrtYd user hide) (47 F.CrtYd user hide) - (48 B.Fab user hide) + (48 B.Fab user) (49 F.Fab user hide) ) @@ -80,7 +80,7 @@ (creategerberjobfile false) (excludeedgelayer false) (linewidth 0.100000) - (plotframeref true) + (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) @@ -89,7 +89,7 @@ (hpglpendiameter 15.000000) (psnegative false) (psa4output false) - (plotreference true) + (plotreference false) (plotvalue false) (plotinvisibletext false) (padsonsilk true) @@ -1375,1050 +1375,24 @@ (uvia_drill 0.127) ) - (module Cryptech_Alpha_Footprints:WE-SHC_36103205_NO_CREAM (layer B.Cu) (tedit 60BDE566) (tstamp 539EEDBF) - (at 83.82 -87.7454) - (path /57D8488D/580240A2) - (attr smd) - (fp_text reference S1 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 36103205 (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at -5.588 -7.2506) (layer B.Fab) - (effects (font (size 5 5) (thickness 0.5)) (justify mirror)) - ) - (fp_line (start -11.176 9.652) (end 11.176 9.652) (layer B.Fab) (width 0.1)) - (fp_line (start 11.176 9.652) (end 11.176 -12.192) (layer B.Fab) (width 0.1)) - (fp_line (start 11.176 -12.192) (end -11.176 -12.192) (layer B.Fab) (width 0.1)) - (fp_line (start -11.176 -12.192) (end -11.176 9.652) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at 10.2616 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at -10.25 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at -10.25 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at 10.2616 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at 9.1186 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at -9.1 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at -9.1 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at 9.1186 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at 3.7592 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at 3.7592 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at -3.75 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at -3.75 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at 10.2616 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at 10.2616 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at -10.25 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 1 smd rect (at -10.25 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - ) - - (module Cryptech_Alpha_Footprints:XTAL3215 (layer F.Cu) (tedit 60BDE4F3) (tstamp 539EEDBF) - (at 19.275 -45.6) - (path /57D84C55/5802401E) - (attr smd) - (fp_text reference X1 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value ABS07-32.768KHZ-T (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -1.27 -2.032) (end 1.27 -2.032) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 -2.032) (end 1.27 2.032) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 2.032) (end -1.27 2.032) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 2.032) (end -1.27 -2.032) (layer F.Fab) (width 0.1)) - (pad P$1 smd rect (at 0 -1.2192 90) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) - (net 153 "Net-(C70-Pad2)")) - (pad P$2 smd rect (at 0 1.2 270) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) - (net 154 "Net-(C71-Pad2)")) - ) - - (module Cryptech_Alpha_Footprints:USB-MINIB (layer F.Cu) (tedit 60BDE442) (tstamp 539EEDBF) - (at 65 14.9) - (path /57D84CB3/58023FF3) - (attr smd) - (fp_text reference CN1 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 690-005-299-043 (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 3 3) (thickness 0.15))) - ) - (fp_line (start -5.588 -5.08) (end 5.588 -5.08) (layer F.Fab) (width 0.1)) - (fp_line (start 5.588 -5.08) (end 5.588 5.08) (layer F.Fab) (width 0.1)) - (fp_line (start 5.588 5.08) (end -5.588 5.08) (layer F.Fab) (width 0.1)) - (fp_line (start -5.588 5.08) (end -5.588 -5.08) (layer F.Fab) (width 0.1)) - (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) - (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) - (pad GND smd rect (at -4.34 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 144 FT_VREGIN)) - (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 221 "/User USB UART/D1_N")) - (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 222 "/User USB UART/D1_P")) - (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 266 "Net-(CN1-PadID)")) - (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad GND smd rect (at -4.34 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad GND smd rect (at 4.36 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad GND smd rect (at 4.36 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model wrlshp/c-1734035-2-e-3d.wrl - (offset (xyz 0.02539999961853028 -5.009133924770355 2.000001049962997)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 360)) - ) - (model wrlshp/23D50C2B-5C98.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module Cryptech_Alpha_Footprints:USB-MINIB (layer F.Cu) (tedit 60BDE442) (tstamp 539EEDBF) - (at 85 14.9) - (path /57D84E30/58023FBD) - (attr smd) - (fp_text reference CN2 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 690-005-299-043 (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 3 3) (thickness 0.15))) - ) - (fp_line (start -5.588 -5.08) (end 5.588 -5.08) (layer F.Fab) (width 0.1)) - (fp_line (start 5.588 -5.08) (end 5.588 5.08) (layer F.Fab) (width 0.1)) - (fp_line (start 5.588 5.08) (end -5.588 5.08) (layer F.Fab) (width 0.1)) - (fp_line (start -5.588 5.08) (end -5.588 -5.08) (layer F.Fab) (width 0.1)) - (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) - (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) - (pad GND smd rect (at -4.34 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 137 FT_MGMT_VREGIN)) - (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 223 "/MGMT USB UART/DM_N")) - (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 224 "/MGMT USB UART/DM_P")) - (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 267 "Net-(CN2-PadID)")) - (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad GND smd rect (at -4.34 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad GND smd rect (at 4.36 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad GND smd rect (at 4.36 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model wrlshp/c-1734035-2-e-3d.wrl - (offset (xyz 0.02539999961853028 -5.009133924770355 2.000001049962997)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 360)) - ) - (model wrlshp/23D50C2B-5C98.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module Cryptech_Alpha_Footprints:TSSOP50P1180X120-86N (layer F.Cu) (tedit 60BDE398) (tstamp 539EEDBF) - (at 86.1704 -49.8264 180) - (path /57D84B22/58024046) - (attr smd) - (fp_text reference U5 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value IS45S32160F-*** (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 5 5) (thickness 0.5))) - ) - (fp_line (start -6.604 -10.922) (end -6.604 10.922) (layer F.Fab) (width 0.1)) - (fp_line (start -6.604 10.922) (end 6.604 10.922) (layer F.Fab) (width 0.1)) - (fp_line (start 6.604 10.922) (end 6.604 -10.922) (layer F.Fab) (width 0.1)) - (fp_line (start 6.604 -10.922) (end -6.604 -10.922) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy -5.08 -10.16) (xy -6.604 -10.16) (xy -6.604 -10.922) (xy -5.08 -10.922)) (layer F.Fab) (width 0.1)) - (pad 1 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 41 FMC_D0)) - (pad 3 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 4 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 42 FMC_D1)) - (pad 5 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 43 FMC_D2)) - (pad 6 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 7 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 44 FMC_D3)) - (pad 8 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 45 FMC_D4)) - (pad 9 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) - (pad 10 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 46 FMC_D5)) - (pad 11 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 47 FMC_D6)) - (pad 12 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 13 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 48 FMC_D7)) - (pad 14 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) - (pad 15 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 16 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 73 FMC_NBL0)) - (pad 17 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 89 FMC_SDNWE)) - (pad 18 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 85 FMC_SDNCAS)) - (pad 19 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 88 FMC_SDNRAS)) - (pad 20 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 86 FMC_SDNE0)) - (pad 21 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 25 FMC_A11)) - (pad 22 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 28 FMC_A14)) - (pad 23 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 29 FMC_A15)) - (pad 24 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 24 FMC_A10)) - (pad 25 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 14 FMC_A0)) - (pad 26 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 15 FMC_A1)) - (pad 27 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 16 FMC_A2)) - (pad 28 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 75 FMC_NBL2)) - (pad 29 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 30 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) - (pad 31 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 57 FMC_D16)) - (pad 32 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 33 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 58 FMC_D17)) - (pad 34 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 59 FMC_D18)) - (pad 35 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 36 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 60 FMC_D19)) - (pad 37 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 61 FMC_D20)) - (pad 38 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 39 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 62 FMC_D21)) - (pad 40 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 63 FMC_D22)) - (pad 41 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 42 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 64 FMC_D23)) - (pad 43 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 86 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 85 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 56 FMC_D15)) - (pad 84 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 83 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 55 FMC_D14)) - (pad 82 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 54 FMC_D13)) - (pad 81 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 80 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 53 FMC_D12)) - (pad 79 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 52 FMC_D11)) - (pad 78 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 77 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 51 FMC_D10)) - (pad 76 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 50 FMC_D9)) - (pad 75 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 74 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 49 FMC_D8)) - (pad 73 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) - (pad 72 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 71 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 74 FMC_NBL1)) - (pad 70 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) - (pad 69 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 26 FMC_A12)) - (pad 68 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 84 FMC_SDCLK)) - (pad 67 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 82 FMC_SDCKE0)) - (pad 66 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 23 FMC_A9)) - (pad 65 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 22 FMC_A8)) - (pad 64 smd oval (at 5.75 0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 21 FMC_A7)) - (pad 63 smd oval (at 5.75 1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 20 FMC_A6)) - (pad 62 smd oval (at 5.75 1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 19 FMC_A5)) - (pad 61 smd oval (at 5.75 2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 18 FMC_A4)) - (pad 60 smd oval (at 5.75 2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 17 FMC_A3)) - (pad 59 smd oval (at 5.75 3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 76 FMC_NBL3)) - (pad 58 smd oval (at 5.75 3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 57 smd oval (at 5.75 4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) - (pad 56 smd oval (at 5.75 4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 72 FMC_D31)) - (pad 55 smd oval (at 5.75 5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 54 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 71 FMC_D30)) - (pad 53 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 70 FMC_D29)) - (pad 52 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 51 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 69 FMC_D28)) - (pad 50 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 68 FMC_D27)) - (pad 49 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 48 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 67 FMC_D26)) - (pad 47 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 66 FMC_D25)) - (pad 46 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 45 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 65 FMC_D24)) - (pad 44 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model wrlshp/D87FE1D2-D8B7.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:TSSOP50P1180X120-86N (layer B.Cu) (tedit 60BDE398) (tstamp 539EEDBF) - (at 80.6704 -49.8264) - (path /57D84B22/58024042) - (attr smd) - (fp_text reference U6 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value IS45S32160F-*** (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 -90) (layer B.Fab) - (effects (font (size 5 5) (thickness 0.5)) (justify mirror)) - ) - (fp_line (start -6.604 10.922) (end -6.604 -10.922) (layer B.Fab) (width 0.1)) - (fp_line (start -6.604 -10.922) (end 6.604 -10.922) (layer B.Fab) (width 0.1)) - (fp_line (start 6.604 -10.922) (end 6.604 10.922) (layer B.Fab) (width 0.1)) - (fp_line (start 6.604 10.922) (end -6.604 10.922) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy -5.08 10.16) (xy -6.604 10.16) (xy -6.604 10.922) (xy -5.08 10.922)) (layer B.Fab) (width 0.1)) - (pad 1 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 41 FMC_D0)) - (pad 3 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 4 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 42 FMC_D1)) - (pad 5 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 43 FMC_D2)) - (pad 6 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 7 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 44 FMC_D3)) - (pad 8 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 45 FMC_D4)) - (pad 9 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) - (pad 10 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 46 FMC_D5)) - (pad 11 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 47 FMC_D6)) - (pad 12 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 13 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 48 FMC_D7)) - (pad 14 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) - (pad 15 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 16 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 73 FMC_NBL0)) - (pad 17 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 89 FMC_SDNWE)) - (pad 18 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 85 FMC_SDNCAS)) - (pad 19 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 88 FMC_SDNRAS)) - (pad 20 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 87 FMC_SDNE1)) - (pad 21 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 25 FMC_A11)) - (pad 22 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 28 FMC_A14)) - (pad 23 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 29 FMC_A15)) - (pad 24 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 24 FMC_A10)) - (pad 25 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 14 FMC_A0)) - (pad 26 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 15 FMC_A1)) - (pad 27 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 16 FMC_A2)) - (pad 28 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 75 FMC_NBL2)) - (pad 29 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 30 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) - (pad 31 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 57 FMC_D16)) - (pad 32 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 33 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 58 FMC_D17)) - (pad 34 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 59 FMC_D18)) - (pad 35 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 36 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 60 FMC_D19)) - (pad 37 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 61 FMC_D20)) - (pad 38 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 39 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 62 FMC_D21)) - (pad 40 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 63 FMC_D22)) - (pad 41 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 42 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 64 FMC_D23)) - (pad 43 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 86 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 85 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 56 FMC_D15)) - (pad 84 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 83 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 55 FMC_D14)) - (pad 82 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 54 FMC_D13)) - (pad 81 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 80 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 53 FMC_D12)) - (pad 79 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 52 FMC_D11)) - (pad 78 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 77 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 51 FMC_D10)) - (pad 76 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 50 FMC_D9)) - (pad 75 smd oval (at 5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 74 smd oval (at 5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 49 FMC_D8)) - (pad 73 smd oval (at 5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) - (pad 72 smd oval (at 5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 71 smd oval (at 5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 74 FMC_NBL1)) - (pad 70 smd oval (at 5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) - (pad 69 smd oval (at 5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 26 FMC_A12)) - (pad 68 smd oval (at 5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 84 FMC_SDCLK)) - (pad 67 smd oval (at 5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 83 FMC_SDCKE1)) - (pad 66 smd oval (at 5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 23 FMC_A9)) - (pad 65 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 22 FMC_A8)) - (pad 64 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 21 FMC_A7)) - (pad 63 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 20 FMC_A6)) - (pad 62 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 19 FMC_A5)) - (pad 61 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 18 FMC_A4)) - (pad 60 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 17 FMC_A3)) - (pad 59 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 76 FMC_NBL3)) - (pad 58 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 57 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) - (pad 56 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 72 FMC_D31)) - (pad 55 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 54 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 71 FMC_D30)) - (pad 53 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 70 FMC_D29)) - (pad 52 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 51 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 69 FMC_D28)) - (pad 50 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 68 FMC_D27)) - (pad 49 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 48 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 67 FMC_D26)) - (pad 47 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 66 FMC_D25)) - (pad 46 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 45 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 65 FMC_D24)) - (pad 44 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model wrlshp/D87FE1D2-D8B7.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:TSQFP50P3000X3000X160-208N (layer B.Cu) (tedit 60BDE330) (tstamp 539EEDBF) - (at 48.6918 -32.6136) - (path /57D84936/58024086) - (attr smd) - (fp_text reference U4 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value STM32F429BIT6 (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 10 10) (thickness 0.5)) (justify mirror)) - ) - (fp_line (start -15.748 15.748) (end -15.748 -15.748) (layer B.Fab) (width 0.1)) - (fp_line (start -15.748 -15.748) (end 15.748 -15.748) (layer B.Fab) (width 0.1)) - (fp_line (start 15.748 -15.748) (end 15.748 15.748) (layer B.Fab) (width 0.1)) - (fp_line (start 15.748 15.748) (end -15.748 15.748) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy -13.208 13.208) (xy -15.748 13.208) (xy -15.748 15.748) (xy -13.208 15.748)) (layer B.Fab) (width 0.1)) - (pad 208 smd oval (at -12.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 70 FMC_D29)) - (pad 207 smd oval (at -12.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 69 FMC_D28)) - (pad 206 smd oval (at -11.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 76 FMC_NBL3)) - (pad 205 smd oval (at -11.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 75 FMC_NBL2)) - (pad 204 smd oval (at -10.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 203 smd oval (at -10.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 202 smd oval (at -9.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 201 smd oval (at -9.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 74 FMC_NBL1)) - (pad 200 smd oval (at -8.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 73 FMC_NBL0)) - (pad 199 smd oval (at -8.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 272 "Net-(U4-Pad199)")) - (pad 198 smd oval (at -7.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 273 "Net-(U4-Pad198)")) - (pad 197 smd oval (at -7.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 248 "/STM32 configuration/BOOT0")) - (pad 196 smd oval (at -6.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 78 FMC_NL)) - (pad 195 smd oval (at -6.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 87 FMC_SDNE1)) - (pad 194 smd oval (at -5.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 83 FMC_SDCKE1)) - (pad 193 smd oval (at -5.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 274 "Net-(U4-Pad193)")) - (pad 192 smd oval (at -4.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 275 "Net-(U4-Pad192)")) - (pad 191 smd oval (at -4.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 85 FMC_SDNCAS)) - (pad 190 smd oval (at -3.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 12 ARM_LED4)) - (pad 189 smd oval (at -3.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 11 ARM_LED3)) - (pad 188 smd oval (at -2.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 10 ARM_LED2)) - (pad 187 smd oval (at -2.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 9 ARM_LED1)) - (pad 186 smd oval (at -1.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 276 "Net-(U4-Pad186)")) - (pad 185 smd oval (at -1.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 184 smd oval (at -0.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 183 smd oval (at -0.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 39 FMC_A25)) - (pad 182 smd oval (at 0.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 38 FMC_A24)) - (pad 181 smd oval (at 0.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 277 "Net-(U4-Pad181)")) - (pad 180 smd oval (at 1.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 278 "Net-(U4-Pad180)")) - (pad 179 smd oval (at 1.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 279 "Net-(U4-Pad179)")) - (pad 178 smd oval (at 2.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 280 "Net-(U4-Pad178)")) - (pad 177 smd oval (at 2.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 96 FPGA_DONE)) - (pad 176 smd oval (at 3.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 281 "Net-(U4-Pad176)")) - (pad 175 smd oval (at 3.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 123 FPGA_IRQ_N_3)) - (pad 174 smd oval (at 4.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 122 FPGA_IRQ_N_2)) - (pad 173 smd oval (at 4.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 77 FMC_NE1)) - (pad 172 smd oval (at 5.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 80 FMC_NWAIT)) - (pad 171 smd oval (at 5.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 170 smd oval (at 6.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 169 smd oval (at 6.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 81 FMC_NWE)) - (pad 168 smd oval (at 7.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 79 FMC_NOE)) - (pad 167 smd oval (at 7.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 40 FMC_CLK)) - (pad 166 smd oval (at 8.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 282 "Net-(U4-Pad166)")) - (pad 165 smd oval (at 8.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 44 FMC_D3)) - (pad 164 smd oval (at 9.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 43 FMC_D2)) - (pad 163 smd oval (at 9.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 576 ARM_SPI3_MOSI)) - (pad 162 smd oval (at 10.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 577 ARM_SPI3_MISO)) - (pad 161 smd oval (at 10.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 578 ARM_SPI3_SCK)) - (pad 160 smd oval (at 11.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 283 "Net-(U4-Pad160)")) - (pad 159 smd oval (at 11.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 238 "/STM32 configuration/SWDCLK")) - (pad 158 smd oval (at 12.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 157 smd oval (at 12.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 68 FMC_D27)) - (pad 156 smd oval (at 14.75 12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 67 FMC_D26)) - (pad 155 smd oval (at 14.75 12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 66 FMC_D25)) - (pad 154 smd oval (at 14.75 11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 65 FMC_D24)) - (pad 153 smd oval (at 14.75 11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 64 FMC_D23)) - (pad 152 smd oval (at 14.75 10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 63 FMC_D22)) - (pad 151 smd oval (at 14.75 10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 62 FMC_D21)) - (pad 150 smd oval (at 14.75 9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 149 smd oval (at 14.75 9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 148 smd oval (at 14.75 8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 216 "/STM32 power/VCAP2")) - (pad 147 smd oval (at 14.75 8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 237 "/STM32 configuration/SWDIO")) - (pad 146 smd oval (at 14.75 7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 129 FT_MGMT_CTS)) - (pad 145 smd oval (at 14.75 7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 131 FT_MGMT_RTS)) - (pad 144 smd oval (at 14.75 6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 133 FT_MGMT_TXD)) - (pad 143 smd oval (at 14.75 6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 132 FT_MGMT_RXD)) - (pad 142 smd oval (at 14.75 5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 130 FT_MGMT_DTR)) - (pad 141 smd oval (at 14.75 5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 579 ARM_SPI3_CS_N)) - (pad 140 smd oval (at 14.75 4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 585 ICE40_CRESET)) - (pad 139 smd oval (at 14.75 4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 284 "Net-(U4-Pad139)")) - (pad 138 smd oval (at 14.75 3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 285 "Net-(U4-Pad138)")) - (pad 137 smd oval (at 14.75 3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 136 smd oval (at 14.75 2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 135 smd oval (at 14.75 2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 84 FMC_SDCLK)) - (pad 134 smd oval (at 14.75 1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 286 "Net-(U4-Pad134)")) - (pad 133 smd oval (at 14.75 1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 287 "Net-(U4-Pad133)")) - (pad 132 smd oval (at 14.75 0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 29 FMC_A15)) - (pad 131 smd oval (at 14.75 0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 28 FMC_A14)) - (pad 130 smd oval (at 14.75 -0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 27 FMC_A13)) - (pad 129 smd oval (at 14.75 -0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 26 FMC_A12)) - (pad 128 smd oval (at 14.75 -1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 288 "Net-(U4-Pad128)")) - (pad 127 smd oval (at 14.75 -1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 289 "Net-(U4-Pad127)")) - (pad 126 smd oval (at 14.75 -2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 290 "Net-(U4-Pad126)")) - (pad 125 smd oval (at 14.75 -2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 124 smd oval (at 14.75 -3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 123 smd oval (at 14.75 -3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 121 FPGA_IRQ_N_1)) - (pad 122 smd oval (at 14.75 -4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 120 FPGA_IRQ_N_0)) - (pad 121 smd oval (at 14.75 -4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 291 "Net-(U4-Pad121)")) - (pad 120 smd oval (at 14.75 -5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 124 FPGA_PROGRAM_B)) - (pad 119 smd oval (at 14.75 -5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 119 FPGA_INIT_B)) - (pad 118 smd oval (at 14.75 -6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 292 "Net-(U4-Pad118)")) - (pad 117 smd oval (at 14.75 -6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 42 FMC_D1)) - (pad 116 smd oval (at 14.75 -7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 41 FMC_D0)) - (pad 115 smd oval (at 14.75 -7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 114 smd oval (at 14.75 -8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 113 smd oval (at 14.75 -8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 32 FMC_A18)) - (pad 112 smd oval (at 14.75 -9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 31 FMC_A17)) - (pad 111 smd oval (at 14.75 -9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 30 FMC_A16)) - (pad 110 smd oval (at 14.75 -10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 56 FMC_D15)) - (pad 109 smd oval (at 14.75 -10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 55 FMC_D14)) - (pad 108 smd oval (at 14.75 -11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 54 FMC_D13)) - (pad 107 smd oval (at 14.75 -11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 7 ARM_FPGA_CFG_MOSI)) - (pad 106 smd oval (at 14.75 -12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 6 ARM_FPGA_CFG_MISO)) - (pad 105 smd oval (at 14.75 -12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 8 ARM_FPGA_CFG_SCLK)) - (pad 104 smd oval (at 12.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 5 ARM_FPGA_CFG_CS_N)) - (pad 103 smd oval (at 12.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 102 smd oval (at 11.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 61 FMC_D20)) - (pad 101 smd oval (at 11.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 60 FMC_D19)) - (pad 100 smd oval (at 10.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 59 FMC_D18)) - (pad 99 smd oval (at 10.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 58 FMC_D17)) - (pad 98 smd oval (at 9.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 57 FMC_D16)) - (pad 97 smd oval (at 9.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 586 ICE40_GPIO_ARM_0)) - (pad 96 smd oval (at 8.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 587 ICE40_GPIO_ARM_1)) - (pad 95 smd oval (at 8.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 293 "Net-(U4-Pad95)")) - (pad 94 smd oval (at 7.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 93 smd oval (at 7.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 92 smd oval (at 6.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 215 "/STM32 power/VCAP1")) - (pad 91 smd oval (at 6.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 588 ICE40_GPIO_ARM_2)) - (pad 90 smd oval (at 5.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 589 ICE40_GPIO_ARM_3)) - (pad 89 smd oval (at 5.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 53 FMC_D12)) - (pad 88 smd oval (at 4.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 52 FMC_D11)) - (pad 87 smd oval (at 4.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 51 FMC_D10)) - (pad 86 smd oval (at 3.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 50 FMC_D9)) - (pad 85 smd oval (at 3.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 49 FMC_D8)) - (pad 84 smd oval (at 2.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 48 FMC_D7)) - (pad 83 smd oval (at 2.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 82 smd oval (at 1.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 81 smd oval (at 1.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 47 FMC_D6)) - (pad 80 smd oval (at 0.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 46 FMC_D5)) - (pad 79 smd oval (at 0.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 45 FMC_D4)) - (pad 78 smd oval (at -0.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 25 FMC_A11)) - (pad 77 smd oval (at -0.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 24 FMC_A10)) - (pad 76 smd oval (at -1.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 23 FMC_A9)) - (pad 75 smd oval (at -1.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 22 FMC_A8)) - (pad 74 smd oval (at -2.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 21 FMC_A7)) - (pad 73 smd oval (at -2.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 72 smd oval (at -3.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 71 smd oval (at -3.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 20 FMC_A6)) - (pad 70 smd oval (at -4.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 88 FMC_SDNRAS)) - (pad 69 smd oval (at -4.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 294 "Net-(U4-Pad69)")) - (pad 68 smd oval (at -5.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 295 "Net-(U4-Pad68)")) - (pad 67 smd oval (at -5.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 296 "Net-(U4-Pad67)")) - (pad 66 smd oval (at -6.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 297 "Net-(U4-Pad66)")) - (pad 65 smd oval (at -6.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 298 "Net-(U4-Pad65)")) - (pad 64 smd oval (at -7.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 299 "Net-(U4-Pad64)")) - (pad 63 smd oval (at -7.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 300 "Net-(U4-Pad63)")) - (pad 62 smd oval (at -8.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 301 "Net-(U4-Pad62)")) - (pad 61 smd oval (at -8.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 145 KSM_PROM_CS_N)) - (pad 60 smd oval (at -9.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 59 smd oval (at -9.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 58 smd oval (at -10.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 302 "Net-(U4-Pad58)")) - (pad 57 smd oval (at -10.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 303 "Net-(U4-Pad57)")) - (pad 56 smd oval (at -11.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 147 KSM_PROM_MOSI)) - (pad 55 smd oval (at -11.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 146 KSM_PROM_MISO)) - (pad 54 smd oval (at -12.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 148 KSM_PROM_SCLK)) - (pad 53 smd oval (at -12.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 128 FT_DTR)) - (pad 52 smd oval (at -14.75 -12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 51 smd oval (at -14.75 -12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 50 smd oval (at -14.75 -11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 140 FT_TXD)) - (pad 49 smd oval (at -14.75 -11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 208 RTC_SDA)) - (pad 48 smd oval (at -14.75 -10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 207 RTC_SCL)) - (pad 47 smd oval (at -14.75 -10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 206 RTC_MFP)) - (pad 46 smd oval (at -14.75 -9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 304 "Net-(U4-Pad46)")) - (pad 45 smd oval (at -14.75 -9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 139 FT_RXD)) - (pad 44 smd oval (at -14.75 -8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 127 FT_CTS)) - (pad 43 smd oval (at -14.75 -8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 138 FT_RTS)) - (pad 42 smd oval (at -14.75 -7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 41 smd oval (at -14.75 -7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 40 smd oval (at -14.75 -6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 39 smd oval (at -14.75 -6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 38 smd oval (at -14.75 -5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 82 FMC_SDCKE0)) - (pad 37 smd oval (at -14.75 -5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 86 FMC_SDNE0)) - (pad 36 smd oval (at -14.75 -4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 305 "Net-(U4-Pad36)")) - (pad 35 smd oval (at -14.75 -4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 89 FMC_SDNWE)) - (pad 34 smd oval (at -14.75 -3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 214 "/STM32 configuration/NRST")) - (pad 33 smd oval (at -14.75 -3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 213 "/STM32 configuration/OSC_OUT")) - (pad 32 smd oval (at -14.75 -2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 247 "/STM32 configuration/OSC_IN")) - (pad 31 smd oval (at -14.75 -2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 306 "Net-(U4-Pad31)")) - (pad 30 smd oval (at -14.75 -1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 307 "Net-(U4-Pad30)")) - (pad 29 smd oval (at -14.75 -1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 308 "Net-(U4-Pad29)")) - (pad 28 smd oval (at -14.75 -0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 309 "Net-(U4-Pad28)")) - (pad 27 smd oval (at -14.75 -0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 91 FPGA_CFG_CTRL_ARM_ENA)) - (pad 26 smd oval (at -14.75 0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 25 smd oval (at -14.75 0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 24 smd oval (at -14.75 1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 19 FMC_A5)) - (pad 23 smd oval (at -14.75 1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 18 FMC_A4)) - (pad 22 smd oval (at -14.75 2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 17 FMC_A3)) - (pad 21 smd oval (at -14.75 2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 92 FPGA_CFG_CTRL_FPGA_DIS)) - (pad 20 smd oval (at -14.75 3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 310 "Net-(U4-Pad20)")) - (pad 19 smd oval (at -14.75 3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 311 "Net-(U4-Pad19)")) - (pad 18 smd oval (at -14.75 4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 16 FMC_A2)) - (pad 17 smd oval (at -14.75 4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 15 FMC_A1)) - (pad 16 smd oval (at -14.75 5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 14 FMC_A0)) - (pad 15 smd oval (at -14.75 5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 14 smd oval (at -14.75 6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 13 smd oval (at -14.75 6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 312 "Net-(U4-Pad13)")) - (pad 12 smd oval (at -14.75 7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 72 FMC_D31)) - (pad 11 smd oval (at -14.75 7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 71 FMC_D30)) - (pad 10 smd oval (at -14.75 8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 313 "Net-(U4-Pad10)")) - (pad 9 smd oval (at -14.75 8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 314 "Net-(U4-Pad9)")) - (pad 8 smd oval (at -14.75 9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 584 ICE40_CDONE)) - (pad 7 smd oval (at -14.75 9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 315 "Net-(U4-Pad7)")) - (pad 6 smd oval (at -14.75 10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 191 "Net-(R32-Pad2)")) - (pad 5 smd oval (at -14.75 10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 36 FMC_A22)) - (pad 4 smd oval (at -14.75 11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 35 FMC_A21)) - (pad 3 smd oval (at -14.75 11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 34 FMC_A20)) - (pad 2 smd oval (at -14.75 12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 33 FMC_A19)) - (pad 1 smd oval (at -14.75 12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) - (net 37 FMC_A23)) - (model wrlshp/1B9BC620-BA33.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:TACTILE_SWITCH (layer F.Cu) (tedit 60BDE2C1) (tstamp 539EEDBF) - (at 62.8 -5.3608) - (path /57D84FAD/58023F9C) - (attr smd) - (fp_text reference S2 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value EVQPT9A15 (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 2 2) (thickness 0.15))) - ) - (fp_line (start -3.048 -3.048) (end 3.048 -3.048) (layer F.Fab) (width 0.1)) - (fp_line (start 3.048 -3.048) (end 3.048 3.048) (layer F.Fab) (width 0.1)) - (fp_line (start 3.048 3.048) (end -3.048 3.048) (layer F.Fab) (width 0.1)) - (fp_line (start -3.048 3.048) (end -3.048 -3.048) (layer F.Fab) (width 0.1)) - (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad B2 smd rect (at -1.8542 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad B1 smd rect (at -1.8542 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad A1 smd rect (at 1.85 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) - (net 618 "Net-(S2-PadA1)")) - (pad A2 smd rect (at 1.85 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) - (net 604 ICE40_PANIC)) - ) - - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 5F27EEA2) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 5F27EEA2) (at 95.8 -10.6) (path /57D8509E/5F17C1AC) (attr smd) - (fp_text reference LED5 (at -1.312 3.488 270) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) + (fp_text reference LED5 (at 0 0) (layer F.SilkS) + (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text value LTST-C191KGKT (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2430,7 +1404,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 45.5142 16) (path /57D84936/5802407B) (attr smd) @@ -2441,13 +1415,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2459,7 +1433,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 41.51419 16) (path /57D84936/58024079) (attr smd) @@ -2470,13 +1444,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2488,7 +1462,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 39.51419 16) (path /57D84936/5802407C) (attr smd) @@ -2499,13 +1473,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2517,7 +1491,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 43.5142 16) (path /57D84936/5802407A) (attr smd) @@ -2528,13 +1502,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2546,7 +1520,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 34.35 16) (path /57D84FAD/58023F8E) (attr smd) @@ -2557,13 +1531,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2575,7 +1549,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 30.35 16) (path /57D84FAD/58023F9E) (attr smd) @@ -2586,13 +1560,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2604,7 +1578,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 28.35 16) (path /57D84FAD/58023F8F) (attr smd) @@ -2615,13 +1589,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2633,7 +1607,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 32.35 16) (path /57D84FAD/58023F8D) (attr smd) @@ -2644,13 +1618,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2662,7 +1636,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 74 16) (path /57D85134/58023F59) (attr smd) @@ -2673,13 +1647,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 244 "/Config interface/FPGA_DONE_INT")) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2691,7 +1665,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 52.05 16) (path /57D854CB/58023EEE) (attr smd) @@ -2702,13 +1676,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2720,7 +1694,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 56.05 16) (path /57D854CB/58023EF0) (attr smd) @@ -2731,13 +1705,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2749,7 +1723,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 54.05 16) (path /57D854CB/58023EEF) (attr smd) @@ -2760,13 +1734,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2778,7 +1752,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 50.05 16) (path /57D854CB/58023EF1) (attr smd) @@ -2789,13 +1763,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2807,7 +1781,7 @@ ) ) - (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BDE1D7) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:VD_0603 (layer F.Cu) (tedit 60BE4937) (tstamp 539EEDBF) (at 76.13225 16) (path /57D85B19/58023E15) (attr smd) @@ -2818,13 +1792,13 @@ (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text user %R (at 0 -0.254 90) (layer F.Fab) - (effects (font (size 0.4 0.4) (thickness 0.05))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_poly (pts (xy 0.762 1.524) (xy -0.762 1.524) (xy -0.762 1.016) (xy 0.762 1.016)) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) (net 184 "Net-(LED18-Pad2)")) (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) @@ -2836,5594 +1810,5171 @@ ) ) - (module Cryptech_Alpha_Footprints:TSOT-8-23 (layer F.Cu) (tedit 60BDE0CF) (tstamp 539EEDBF) - (at 70.5 -89.75) - (path /57D84708/580240B8) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 5F27EC88) + (at 93.2 -33 270) + (path /57D8509E/5F112F44) (attr smd) - (fp_text reference U2 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C228 (at 0 0 90) (layer B.SilkS) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value LT3060ITS8-15#TRMPBF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0.254) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at -0.02 0.998 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.286 -1.524) (end 2.286 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 2.286 -1.524) (end 2.286 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 2.286 1.524) (end -2.286 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -2.286 1.524) (end -2.286 -1.524) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy -0.508 -0.762) (xy -2.286 -0.762) (xy -2.286 -1.524) (xy -0.508 -1.524)) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1.3 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) - (net 243 /Power/15V_LDO_ENABLE)) - (pad 2 smd rect (at -1.3 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 3 smd rect (at -1.3 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 4 smd rect (at -1.3 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 1 3V3_BATT)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 5 smd rect (at 1.3208 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) - (net 202 PWR_18V)) - (pad 6 smd rect (at 1.3208 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) - (net 2 15V_STABLE)) - (pad 7 smd rect (at 1.3208 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) - (net 150 "Net-(C11-Pad1)")) - (pad 8 smd rect (at 1.3208 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) - (net 151 "Net-(C12-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:SOT-23-5 (layer B.Cu) (tedit 60BDE057) (tstamp 539EEDBF) - (at 77.3684 -85.1408) - (path /57D8488D/5802409C) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 5F27EC82) + (at 94.2 -33 90) + (path /57D8509E/5F112F4E) (attr smd) - (fp_text reference U3 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C227 (at 0 0 90) (layer B.SilkS) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value MC74HC1G14DTT1G (at 0 0) (layer Cmts.User) + (fp_text value 0.01uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + (fp_text user %R (at 0 1.05 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.032 1.524) (end 2.032 1.524) (layer B.Fab) (width 0.1)) - (fp_line (start 2.032 1.524) (end 2.032 -1.524) (layer B.Fab) (width 0.1)) - (fp_line (start 2.032 -1.524) (end -2.032 -1.524) (layer B.Fab) (width 0.1)) - (fp_line (start -2.032 -1.524) (end -2.032 1.524) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy 2.032 -1.524) (xy 0.762 -1.524) (xy 0.762 -1.27) (xy 1.778 -1.27) - (xy 1.778 -0.508) (xy 2.032 -0.508)) (layer B.Fab) (width 0.1)) - (pad 5 smd rect (at -1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 4 smd rect (at -1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) - (net 13 DIGITIZED_NOISE)) - (pad 3 smd rect (at 1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 smd rect (at 1.35 0 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) - (net 225 "/Entropy source/AMPLIFIED")) - (pad 1 smd oval (at 1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) - (net 271 "Net-(U3-Pad1)")) - (model "wrlshp/User Library-SOT23-5-1.wrl" - (at (xyz 0 0 0)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 1 3V3_BATT)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/612DFB50-5309.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer B.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 82.8548 -89.1794 90) - (path /57D8488D/58024095) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F048F99) + (at 76.8 -29) + (path /57D8509E/5F14E9EA) (attr smd) - (fp_text reference D1 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C226 (at 0 0) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BAT54LT1G (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 -90) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -2.286 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 1.778) (end -1.524 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -1.778) (end 1.524 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end 1.524 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end -1.524 -1.778) (layer B.Fab) (width 0.1)) - (pad 3 smd rect (at 0 -1.1 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) - (net 225 "/Entropy source/AMPLIFIED")) - (pad 2 smd rect (at -0.95 1.1 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask)) - (pad 1 smd rect (at 0.95 1.1 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) - (net 4 "Net-(C15-Pad2)")) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 20.9804 -63.5508 270) - (path /57D85B19/58023E10) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F048F93) + (at 76.8 -28 180) + (path /57D8509E/5F154973) (attr smd) - (fp_text reference D2 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C225 (at 0 0) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BAT54LT1G (at 0 0 90) (layer Cmts.User) + (fp_text value 0.01uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 2.286 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) - (pad 3 smd rect (at 0 1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 209 VCC_5V0)) - (pad 2 smd rect (at -0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) - (pad 1 smd rect (at 0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 204 PWR_ENA_VCCINT)) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 11.6078 -47.2694 270) - (path /57D85B19/58023E0A) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F048F8D) + (at 81 -33.2 270) + (path /57D8509E/5F149FB8) (attr smd) - (fp_text reference D3 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C224 (at 0 0 90) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BAT54LT1G (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -2.614 -0.026 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) - (pad 3 smd rect (at 0 1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 199 POK_VCCAUX)) - (pad 2 smd rect (at -0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) - (pad 1 smd rect (at 0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 205 PWR_ENA_VCCO)) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 32.8168 -72.9234 90) - (path /57D85B19/58023E0D) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F048F87) + (at 83.2 -28 180) + (path /57D8509E/5F13FBA7) (attr smd) - (fp_text reference D4 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C223 (at 0 0) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BAT54LT1G (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 2.286 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) - (pad 3 smd rect (at 0 1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 200 POK_VCCINT)) - (pad 2 smd rect (at -0.95 -1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) - (pad 1 smd rect (at 0.95 -1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 203 PWR_ENA_VCCAUX)) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 72.452 -95.2388) - (path /57D84708/580240BE) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F048F81) + (at 82 -33.2 90) + (path /57D8509E/5F15426E) (attr smd) - (fp_text reference Q1 (at 0 0) (layer F.SilkS) hide + (fp_text reference C222 (at 0 0 90) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 2N7002 (at 0 0) (layer Cmts.User) + (fp_text value 0.01uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 2.614 0.042 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) - (pad 3 smd rect (at 0 1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 169 "Net-(JP2-Pad2)")) - (pad 2 smd rect (at -0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 185 "Net-(Q1-Pad1)")) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer B.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 90.3732 -92.7862 270) - (path /57D8488D/580240A1) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F048F7B) + (at 83.2 -29) + (path /57D8509E/5F153C00) (attr smd) - (fp_text reference Q2 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C221 (at 0 0) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BC818-40LT1G (at 0 0 90) (layer Cmts.User) + (fp_text value 0.01uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + (fp_text user %R (at -2.286 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 1.778) (end -1.524 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -1.778) (end 1.524 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end 1.524 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end -1.524 -1.778) (layer B.Fab) (width 0.1)) - (pad 3 smd rect (at 0 -1.1) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) - (net 269 "Net-(Q2-Pad3)")) - (pad 2 smd rect (at -0.95 1.1) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) - (net 211 "/Entropy source/NOISE_IN")) - (pad 1 smd rect (at 0.95 1.1) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) - (net 245 "/Entropy source/NOISE_OUT")) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 89.3064 -73.0504 270) - (path /57D85134/58023F5B) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F045642) + (at 83.2 -30) + (path /57D8509E/5F11DC09) (attr smd) - (fp_text reference Q4 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C220 (at 0 0) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 2N7002 (at 0 0 90) (layer Cmts.User) + (fp_text value 0.01uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at -2.286 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) - (pad 3 smd rect (at 0 1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 246 "/Config interface/FPGA_INIT_B_INT")) - (pad 2 smd rect (at -0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 119 FPGA_INIT_B)) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 571 "/Master Key Memory/MKM_VCC")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 15.7398 -42.4106 90) - (path /57D85B19/58023E16) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F04563C) + (at 76.8 -31) + (path /57D8509E/5F11E1B4) (attr smd) - (fp_text reference Q6 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C219 (at 0 0) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 2N7002 (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -2.286 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) - (pad 3 smd rect (at 0 1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 184 "Net-(LED18-Pad2)")) - (pad 2 smd rect (at -0.95 -1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0.95 -1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) - (net 201 POK_VCCO)) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 571 "/Master Key Memory/MKM_VCC")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer B.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 90.2208 -88.1634 180) - (path /57D8488D/580240A0) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F036329) + (at 76.8 -30 180) + (path /57D8509E/5F0798C6) (attr smd) - (fp_text reference T1 (at 0 0) (layer F.SilkS) hide + (fp_text reference C218 (at 0 0) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BC847BLT3G (at 0 0) (layer Cmts.User) + (fp_text value 0.01uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 2.286 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 1.778) (end -1.524 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -1.778) (end 1.524 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end 1.524 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end -1.524 -1.778) (layer B.Fab) (width 0.1)) - (pad 3 smd rect (at 0 -1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) - (net 212 "/Entropy source/RAW_NOISE")) - (pad 2 smd rect (at -0.95 1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 571 "/Master Key Memory/MKM_VCC")) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0.95 1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) - (net 245 "/Entropy source/NOISE_OUT")) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOT-23 (layer B.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) - (at 84.201 -82.7532) - (path /57D8488D/5802409F) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F036323) + (at 83.2 -31 180) + (path /57D8509E/5F077BE8) (attr smd) - (fp_text reference T2 (at 0 0) (layer F.SilkS) hide + (fp_text reference C217 (at 0 0) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BC847BLT3G (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 -180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + (fp_text user %R (at 2.286 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 1.524 1.778) (end -1.524 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -1.778) (end 1.524 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -1.778) (end 1.524 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 1.778) (end -1.524 -1.778) (layer B.Fab) (width 0.1)) - (pad 3 smd rect (at 0 -1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) - (net 225 "/Entropy source/AMPLIFIED")) - (pad 2 smd rect (at -0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 571 "/Master Key Memory/MKM_VCC")) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) - (net 4 "Net-(C15-Pad2)")) - (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" - (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/04B9CA18-3B1B.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:SOIC127P600X175-8N (layer F.Cu) (tedit 60BDDF09) (tstamp 539EEDBF) - (at 25.6 -43.45 270) - (path /57D84C55/58024021) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 5F03631D) + (at 86.7 -30.4) + (path /57D8509E/5F05C031) (attr smd) - (fp_text reference U7 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C216 (at 0 0) (layer F.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value MCP79412-I_SN (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0.762 0) (layer F.Fab) - (effects (font (size 2 2) (thickness 0.15))) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 -1.096) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -2.794 -4.064) (end 2.794 -4.064) (layer F.Fab) (width 0.1)) - (fp_line (start 2.794 -4.064) (end 2.794 4.064) (layer F.Fab) (width 0.1)) - (fp_line (start 2.794 4.064) (end -2.794 4.064) (layer F.Fab) (width 0.1)) - (fp_line (start -2.794 4.064) (end -2.794 -4.064) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy -1.016 4.064) (xy -2.794 4.064) (xy -2.794 1.778) (xy -1.016 1.778)) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1.905 2.7178) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 153 "Net-(C70-Pad2)")) - (pad 2 smd rect (at -0.635 2.7178) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 154 "Net-(C71-Pad2)")) - (pad 3 smd rect (at 0.635 2.7178) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) - (pad 4 smd rect (at 1.905 2.7178) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 5 smd rect (at 1.905 -2.6924) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 208 RTC_SDA)) - (pad 6 smd rect (at 0.635 -2.6924) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 207 RTC_SCL)) - (pad 7 smd rect (at -0.635 -2.6924) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 206 RTC_MFP)) - (pad 8 smd rect (at -1.905 -2.6924) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 573 "/Master Key Memory/MKM_VCC_PLL")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:SO20W (layer F.Cu) (tedit 60BDDB8C) (tstamp 539EEDBF) - (at 39.356 -38.3524 90) - (path /57D85260/58023F40) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 26.1 -84.7) + (path /57D84708/580240C2) (attr smd) - (fp_text reference IC2 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value MC74AC244DW* (at 0 0 90) (layer Cmts.User) + (fp_text value 0.047uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 4 4) (thickness 0.3))) + (fp_text user %R (at 0.062 -0.898) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -6.604 -6.604) (end -6.604 6.604) (layer F.Fab) (width 0.1)) - (fp_line (start -6.604 6.604) (end 6.604 6.604) (layer F.Fab) (width 0.1)) - (fp_line (start 6.604 6.604) (end 6.604 -6.604) (layer F.Fab) (width 0.1)) - (fp_line (start 6.604 -6.604) (end -6.604 -6.604) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy -4.826 6.604) (xy -6.604 6.604) (xy -6.604 3.556) (xy -4.826 3.556)) (layer F.Fab) (width 0.1)) - (pad 11 smd rect (at 5.715 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 90 FPGA_CFG_CS_N)) - (pad 12 smd rect (at 4.445 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 6 ARM_FPGA_CFG_MISO)) - (pad 10 smd rect (at 5.715 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 202 PWR_18V)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 9 smd rect (at 4.445 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 226 "/Config memory/FPGA_PROM_CS_N")) - (pad 20 smd rect (at -5.715 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 19 smd rect (at -4.445 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 227 "/Config memory/SPI_B_TRISTATE")) - (pad 18 smd rect (at -3.175 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 226 "/Config memory/FPGA_PROM_CS_N")) - (pad 17 smd rect (at -1.905 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 228 "/Config memory/FPGA_PROM_MISO")) - (pad 16 smd rect (at -0.635 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 229 "/Config memory/FPGA_PROM_SCLK")) - (pad 15 smd rect (at 0.635 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 94 FPGA_CFG_MOSI)) - (pad 14 smd rect (at 1.905 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 230 "/Config memory/FPGA_PROM_MOSI")) - (pad 13 smd rect (at 3.175 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 95 FPGA_CFG_SCLK)) - (pad 8 smd rect (at 3.175 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 228 "/Config memory/FPGA_PROM_MISO")) - (pad 7 smd rect (at 1.905 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 229 "/Config memory/FPGA_PROM_SCLK")) - (pad 6 smd rect (at 0.635 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 7 ARM_FPGA_CFG_MOSI)) - (pad 5 smd rect (at -0.635 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 230 "/Config memory/FPGA_PROM_MOSI")) - (pad 4 smd rect (at -1.905 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 8 ARM_FPGA_CFG_SCLK)) - (pad 3 smd rect (at -3.175 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 93 FPGA_CFG_MISO)) - (pad 2 smd rect (at -4.445 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 5 ARM_FPGA_CFG_CS_N)) - (pad 1 smd rect (at -5.715 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 231 "/Config memory/SPI_A_TRISTATE")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:SO08 (layer F.Cu) (tedit 60BDDB3A) (tstamp 539EEDBF) - (at 33.1552 -51.028) - (path /57D84C13/5802402B) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 25.55 -75.725) + (path /57D84708/580240B6) (attr smd) - (fp_text reference IC1 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value MT25QL128ABA1ESE (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 2 2) (thickness 0.2))) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0.358 -0.983) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start 4.572 -2.794) (end -4.572 -2.794) (layer F.Fab) (width 0.1)) - (fp_line (start -4.572 -2.794) (end -4.572 2.794) (layer F.Fab) (width 0.1)) - (fp_line (start -4.572 2.794) (end 4.572 2.794) (layer F.Fab) (width 0.1)) - (fp_line (start 4.572 2.794) (end 4.572 -2.794) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy -2.032 -1.524) (xy -4.572 -1.524) (xy -4.572 -2.794) (xy -2.032 -2.794)) (layer F.Fab) (width 0.1)) - (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 147 KSM_PROM_MOSI)) - (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 148 KSM_PROM_SCLK)) - (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 168 "Net-(IC1-Pad3)")) - (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 146 KSM_PROM_MISO)) - (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 145 KSM_PROM_CS_N)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 149 "Net-(C5-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:SO08 (layer F.Cu) (tedit 60BDDB3A) (tstamp 539EEDBF) - (at 45.5368 -25.2832) - (path /57D85260/58023F42) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 25.5778 -71.8312) + (path /57D84708/580240C3) (attr smd) - (fp_text reference IC3 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value MT25QL128ABA1ESE (at 0 0) (layer Cmts.User) + (fp_text value 0.047uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 2 2) (thickness 0.2))) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0.0762 0.9652) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start 4.572 -2.794) (end -4.572 -2.794) (layer F.Fab) (width 0.1)) - (fp_line (start -4.572 -2.794) (end -4.572 2.794) (layer F.Fab) (width 0.1)) - (fp_line (start -4.572 2.794) (end 4.572 2.794) (layer F.Fab) (width 0.1)) - (fp_line (start 4.572 2.794) (end 4.572 -2.794) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy -2.032 -1.524) (xy -4.572 -1.524) (xy -4.572 -2.794) (xy -2.032 -2.794)) (layer F.Fab) (width 0.1)) - (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 230 "/Config memory/FPGA_PROM_MOSI")) - (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 229 "/Config memory/FPGA_PROM_SCLK")) - (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 232 "/Config memory/FPGA_PROM_W_N")) - (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 228 "/Config memory/FPGA_PROM_MISO")) - (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) - (net 226 "/Config memory/FPGA_PROM_CS_N")) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:RCLAMP0502A (layer F.Cu) (tedit 60BDDAD0) (tstamp 539EEDBF) - (at 51.816 -11.0744) - (path /57D84CB3/58023FF2) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 74.5 -89.5 270) + (path /57D84708/580240C4) (attr smd) - (fp_text reference IC5 (at 0 0) (layer F.SilkS) hide + (fp_text reference C11 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value RCLAMP0502A.TCT (at 0 0) (layer Cmts.User) + (fp_text value 0.01uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05))) + (fp_text user %R (at 0 1.094 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 150 "Net-(C11-Pad1)")) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 2 15V_STABLE)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) ) - (fp_line (start -0.762 -1.27) (end -0.762 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.27) (end 0.762 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.27) (end 0.762 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.762) (end 0.254 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 0.254 -1.27) (end -0.762 -1.27) (layer F.Fab) (width 0.1)) - (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 222 "/User USB UART/D1_P")) - (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 144 FT_VREGIN)) - (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 221 "/User USB UART/D1_N")) - (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 233 "/User USB UART/USB_N")) - (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 234 "/User USB UART/USB_P")) ) - (module Cryptech_Alpha_Footprints:RCLAMP0502A (layer F.Cu) (tedit 60BDDAD0) (tstamp 539EEDBF) - (at 69.1134 -11.0744) - (path /57D84E30/58023FBC) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 71.25 -92.5) + (path /57D84708/580240B5) (attr smd) - (fp_text reference IC6 (at 0 0) (layer F.SilkS) hide + (fp_text reference C12 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value RCLAMP0502A.TCT (at 0 0) (layer Cmts.User) + (fp_text value 0.01uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05))) + (fp_text user %R (at -2.162 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -1.27) (end -0.762 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.27) (end 0.762 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.27) (end 0.762 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.762) (end 0.254 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 0.254 -1.27) (end -0.762 -1.27) (layer F.Fab) (width 0.1)) - (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 224 "/MGMT USB UART/DM_P")) - (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 137 FT_MGMT_VREGIN)) - (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 223 "/MGMT USB UART/DM_N")) - (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 235 "/MGMT USB UART/USB_MGMT_N")) - (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) - (net 236 "/MGMT USB UART/USB_MGMT_P")) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 151 "Net-(C12-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:QFN68 (layer B.Cu) (tedit 60BDDA1D) (tstamp 539EEDBF) - (at 25.9842 -57.4802) - (path /57D85A75/58023E29) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 89.9922 -96.2152 180) + (path /57D8488D/5802409B) (attr smd) - (fp_text reference U16 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C14 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value EN5364QI (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 3 3) (thickness 0.2)) (justify mirror)) + (fp_text user %R (at 0 1.0668) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -6.096 4.572) (end -6.096 -4.572) (layer B.Fab) (width 0.1)) - (fp_line (start -6.096 -4.572) (end 6.096 -4.572) (layer B.Fab) (width 0.1)) - (fp_line (start 6.096 -4.572) (end 6.096 4.572) (layer B.Fab) (width 0.1)) - (fp_line (start 6.096 4.572) (end -6.096 4.572) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy 6.096 -4.572) (xy 4.826 -4.572) (xy 4.826 -3.81) (xy 6.096 -3.81)) (layer B.Fab) (width 0.1)) - (pad 1 smd oval (at 5.5 -3.5052 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 2 smd oval (at 5.5 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 3 smd oval (at 5.5 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 4 smd oval (at 5.5 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 5 smd oval (at 5.5 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 6 smd oval (at 5.5 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 7 smd oval (at 5.5 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 8 smd oval (at 5.5 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 9 smd oval (at 5.5 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 10 smd oval (at 5.5 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 11 smd oval (at 5.5 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 12 smd oval (at 5.5 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 13 smd oval (at 5.5 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 14 smd oval (at 5.5 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 15 smd oval (at 5.5 3.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 16 smd oval (at 4.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 17 smd oval (at 4 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 18 smd oval (at 3.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 19 smd oval (at 3 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 20 smd oval (at 2.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 21 smd oval (at 2 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 22 smd oval (at 1.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 23 smd oval (at 1 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 24 smd oval (at 0.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 25 smd oval (at 0 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 26 smd oval (at -0.508 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 27 smd oval (at -1.016 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 28 smd oval (at -1.524 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 29 smd oval (at -2.0066 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 30 smd oval (at -2.5146 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 31 smd oval (at -3.0226 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 32 smd oval (at -3.5052 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 33 smd oval (at -4.0132 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 34 smd oval (at -4.5212 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 35 smd oval (at -5.5118 3.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 36 smd oval (at -5.5118 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 37 smd oval (at -5.5118 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 38 smd oval (at -5.5118 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 39 smd oval (at -5.5118 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 40 smd oval (at -5.5118 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 41 smd oval (at -5.5118 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 42 smd oval (at -5.5118 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 43 smd oval (at -5.5118 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 44 smd oval (at -5.5118 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 45 smd oval (at -5.5118 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 46 smd oval (at -5.5118 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 47 smd oval (at -5.5118 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 48 smd oval (at -5.5118 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 562 "Net-(U16-Pad48)")) - (pad 49 smd oval (at -5.5118 -3.5052) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 563 "Net-(U16-Pad49)")) - (pad 50 smd oval (at -4.5212 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 564 "Net-(U16-Pad50)")) - (pad 51 smd oval (at -4.0132 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 197 "Net-(R66-Pad1)")) - (pad 52 smd oval (at -3.5052 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 204 PWR_ENA_VCCINT)) - (pad 53 smd oval (at -3.0226 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 54 smd oval (at -2.5146 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 200 POK_VCCINT)) - (pad 55 smd oval (at -2.0066 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 56 smd oval (at -1.524 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 167 "Net-(C208-Pad2)")) - (pad 57 smd oval (at -1.016 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 565 "Net-(U16-Pad57)")) - (pad 58 smd oval (at -0.508 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 566 "Net-(U16-Pad58)")) - (pad 59 smd oval (at 0 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 165 "Net-(C207-Pad1)")) - (pad 60 smd oval (at 0.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 567 "Net-(U16-Pad60)")) - (pad 61 smd oval (at 1 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 568 "Net-(U16-Pad61)")) - (pad 62 smd oval (at 1.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 569 "Net-(U16-Pad62)")) - (pad 63 smd oval (at 2 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 198 "Net-(R67-Pad1)")) - (pad 64 smd oval (at 2.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 65 smd oval (at 3 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 66 smd oval (at 3.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 67 smd oval (at 4 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 68 smd oval (at 4.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad PAD69 smd oval (at -2.175 0.625 90) (size 5.35 2.35) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad PAD70 smd oval (at 3.55 -2.65 180) (size 2.5 1.3) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 211 "/Entropy source/NOISE_IN")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:QFN38 (layer B.Cu) (tedit 60BDD9B9) (tstamp 539EEDBF) - (at 35.4584 -76.5556 180) - (path /57D853B0/58023F0C) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 89.4842 -81.6864 180) + (path /57D8488D/58024098) (attr smd) - (fp_text reference U14 (at 0 0) (layer F.SilkS) hide + (fp_text reference C15 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value EN6347QI (at 0 0) (layer Cmts.User) + (fp_text user %R (at 0.0762 1.1176) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 212 "/Entropy source/RAW_NOISE")) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 4 "Net-(C15-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 77.343 -88.5444 180) + (path /57D8488D/580240A3) + (attr smd) + (fp_text reference C16 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 2 2) (thickness 0.15)) (justify mirror)) + (fp_text user %R (at 0 1.1176) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.286 3.81) (end -2.286 -3.81) (layer B.Fab) (width 0.1)) - (fp_line (start -2.286 -3.81) (end 2.286 -3.81) (layer B.Fab) (width 0.1)) - (fp_line (start 2.286 -3.81) (end 2.286 3.81) (layer B.Fab) (width 0.1)) - (fp_line (start 2.286 3.81) (end -2.286 3.81) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy 2.286 3.302) (xy 1.778 3.302) (xy 1.778 3.81) (xy 2.286 3.81)) (layer B.Fab) (width 0.1)) - (pad 1 smd oval (at 1.27 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 2 smd oval (at 0.762 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 3 smd oval (at 0.254 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 4 smd oval (at -0.25 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 5 smd oval (at -0.75 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (pad 6 smd oval (at -1.25 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (pad 7 smd oval (at -1.9 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (pad 8 smd oval (at -1.9 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (pad 9 smd oval (at -1.9 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (pad 10 smd oval (at -1.9 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (pad 11 smd oval (at -1.9 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (pad 12 smd oval (at -1.9 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 13 smd oval (at -1.9 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 14 smd oval (at -1.9 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 15 smd oval (at -1.9 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 16 smd oval (at -1.9 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 17 smd oval (at -1.9 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 18 smd oval (at -1.9 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 19 smd oval (at -1.9 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 20 smd oval (at -1.25 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 21 smd oval (at -0.75 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 22 smd oval (at -0.25 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 23 smd oval (at 0.254 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 24 smd oval (at 0.762 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 25 smd oval (at 1.27 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 26 smd oval (at 1.905 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 192 "Net-(R52-Pad1)")) - (pad 27 smd oval (at 1.905 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 203 PWR_ENA_VCCAUX)) - (pad 28 smd oval (at 1.905 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 199 POK_VCCAUX)) - (pad 29 smd oval (at 1.905 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 193 "Net-(R53-Pad2)")) - (pad 30 smd oval (at 1.905 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 159 "Net-(C115-Pad1)")) - (pad 31 smd oval (at 1.905 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 162 "Net-(C117-Pad2)")) - (pad 32 smd oval (at 1.905 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 33 smd oval (at 1.905 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 34 smd oval (at 1.905 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 35 smd oval (at 1.905 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 36 smd oval (at 1.905 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 37 smd oval (at 1.905 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 38 smd oval (at 1.905 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad PAD39 smd oval (at 0 -1.26 180) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:QFN38 (layer B.Cu) (tedit 60BDD9B9) (tstamp 539EEDBF) - (at 10.8458 -41.0972) - (path /57D853B0/58023F0B) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 28.925 -32.05) + (path /57D84936/58024080) (attr smd) - (fp_text reference U15 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C17 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value EN6347QI (at 0 0) (layer Cmts.User) + (fp_text value 5.1pF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 -270) (layer B.Fab) - (effects (font (size 2 2) (thickness 0.15)) (justify mirror)) + (fp_text user %R (at 0.031 1.062) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.286 3.81) (end -2.286 -3.81) (layer B.Fab) (width 0.1)) - (fp_line (start -2.286 -3.81) (end 2.286 -3.81) (layer B.Fab) (width 0.1)) - (fp_line (start 2.286 -3.81) (end 2.286 3.81) (layer B.Fab) (width 0.1)) - (fp_line (start 2.286 3.81) (end -2.286 3.81) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy 2.286 3.302) (xy 1.778 3.302) (xy 1.778 3.81) (xy 2.286 3.81)) (layer B.Fab) (width 0.1)) - (pad 1 smd oval (at 1.27 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 2 smd oval (at 0.762 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 3 smd oval (at 0.254 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 4 smd oval (at -0.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 5 smd oval (at -0.75 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (pad 6 smd oval (at -1.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (pad 7 smd oval (at -1.9 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (pad 8 smd oval (at -1.9 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (pad 9 smd oval (at -1.9 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (pad 10 smd oval (at -1.9 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (pad 11 smd oval (at -1.9 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (pad 12 smd oval (at -1.9 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 13 smd oval (at -1.9 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 14 smd oval (at -1.9 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 15 smd oval (at -1.9 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 16 smd oval (at -1.9 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 17 smd oval (at -1.9 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 18 smd oval (at -1.9 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 19 smd oval (at -1.9 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 20 smd oval (at -1.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 21 smd oval (at -0.75 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 22 smd oval (at -0.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 23 smd oval (at 0.254 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 24 smd oval (at 0.762 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 25 smd oval (at 1.27 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 26 smd oval (at 1.905 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 194 "Net-(R54-Pad1)")) - (pad 27 smd oval (at 1.905 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 205 PWR_ENA_VCCO)) - (pad 28 smd oval (at 1.905 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 201 POK_VCCO)) - (pad 29 smd oval (at 1.905 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 195 "Net-(R55-Pad2)")) - (pad 30 smd oval (at 1.905 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 160 "Net-(C116-Pad1)")) - (pad 31 smd oval (at 1.905 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 164 "Net-(C118-Pad2)")) - (pad 32 smd oval (at 1.905 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 33 smd oval (at 1.905 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 34 smd oval (at 1.905 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 35 smd oval (at 1.905 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 36 smd oval (at 1.905 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 37 smd oval (at 1.905 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad 38 smd oval (at 1.905 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) - (pad PAD39 smd oval (at 0 -1.26) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 152 "Net-(C17-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 28.175 -38.55 180) + (path /57D84936/58024089) + (attr smd) + (fp_text reference C18 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 5.1pF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 2.013 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 213 "/STM32 configuration/OSC_OUT")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:PLS-8 (layer F.Cu) (tedit 60BDD914) (tstamp 539EEDBF) - (at 40.3 -1.3) - (path /57D85134/58023F68) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 13.125 -20.45 180) + (path /57D84936/58024087) (attr smd) - (fp_text reference SV1 (at 0 0) (layer F.SilkS) hide + (fp_text reference C19 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 0 0.886) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -10.16 -1.27) (end -10.16 0) (layer F.Fab) (width 0.1)) - (fp_line (start -10.16 0) (end -8.89 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -8.89 1.27) (end 10.16 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 10.16 1.27) (end 10.16 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 10.16 -1.27) (end -10.16 -1.27) (layer F.Fab) (width 0.1)) - (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 3 GND)) - (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 258 "/Config interface/FPGA_JTAG_TCK")) - (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 257 "/Config interface/FPGA_JTAG_TMS")) - (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 256 "/Config interface/FPGA_JTAG_TDI")) - (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 265 "/Config interface/FPGA_JTAG_TDO")) - (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 3 GND)) - (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model wrlshp/PLS-8.wrl - (offset (xyz 8.889999866485596 -0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/A962434E-CFE5.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:PLS-6 (layer F.Cu) (tedit 60BDD8EC) (tstamp 539EEDBF) - (at 22.78379 -20.4216) - (path /57D84936/58024085) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 26.6 -23.3 90) + (path /57D84936/5802407E) (attr smd) - (fp_text reference J1 (at 0 0) (layer F.SilkS) hide + (fp_text reference C20 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value "STM32 SWD connector" (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 0 -0.946 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -7.62 -1.27) (end -7.62 0) (layer F.Fab) (width 0.1)) - (fp_line (start -7.62 0) (end -6.35 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -6.35 1.27) (end 7.62 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 7.62 1.27) (end 7.62 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 7.62 -1.27) (end -7.62 -1.27) (layer F.Fab) (width 0.1)) - (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 268 "Net-(J1-Pad6)")) - (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 214 "/STM32 configuration/NRST")) - (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 237 "/STM32 configuration/SWDIO")) - (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 238 "/STM32 configuration/SWDCLK")) - (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 210 VCCO_3V3)) - (model wrlshp/pin_header_a-sl254-ea-g06mp1.wrl - (offset (xyz 0.006349999904632569 0.08635999870300293 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 90 360 360)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/670BFB14-85C2.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:PLS-3 (layer F.Cu) (tedit 60BDD856) (tstamp 539EEDBF) - (at 88.67933 1.5) - (path /57D84FAD/58023F9B) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 50.6476 -49.3522 180) + (path /57D849FD/58024069) (attr smd) - (fp_text reference JP4 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C28 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value "Standard 3-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115). Molex polarized connector foot print use with SKU : PRT-08232 with associated crimp pins and housings." (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 1.8796 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -3.81 -1.27) (end -3.81 0) (layer F.Fab) (width 0.1)) - (fp_line (start -3.81 0) (end -2.54 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -2.54 1.27) (end 3.81 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 3.81 1.27) (end 3.81 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 3.81 -1.27) (end -3.81 -1.27) (layer F.Fab) (width 0.1)) - (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 3 GND)) - (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 1 3V3_BATT)) - (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (model wrlshp/pin_header_aw_108_03-t.wrl - (offset (xyz 0.05003799924850464 0.05003799924850464 0)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 90 360 0)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/836C6F64-A2E5.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:PLS-2 (layer F.Cu) (tedit 60BDD824) (tstamp 5F27EE3C) - (at 75 -19.8 180) - (path /57D84FAD/5F27A891) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 65.4304 -35.6616 270) + (path /57D849FD/5802406A) (attr smd) - (fp_text reference JP3 (at 0 0) (layer F.SilkS) hide + (fp_text reference C29 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) + (fp_text user %R (at 0 -1.1176 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 57.3532 -49.784 90) + (path /57D849FD/5802406B) + (attr smd) + (fp_text reference C30 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 2.032 0.0508 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.54 -1.27) (end -2.54 0) (layer F.Fab) (width 0.1)) - (fp_line (start -2.54 0) (end -1.27 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 1.27) (end 2.54 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 1.27) (end 2.54 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.Fab) (width 0.1)) - (pad 2 thru_hole circle (at 1.27 0 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 594 ICE40_JUMPER)) - (pad 1 thru_hole rect (at -1.27 0 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/User Library-Header1x2.wrl" - (offset (xyz 5.675121914768218 11.80693582267761 -6.799998997874261)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/3416A7AC-A52A.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:PLS-2 (layer F.Cu) (tedit 60BDD824) (tstamp 539EEDBF) - (at 64.6468 -91.7448) - (path /57D84708/580240BB) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 61.341 -15.9512) + (path /57D849FD/5802406D) (attr smd) - (fp_text reference JP2 (at 0 0) (layer F.SilkS) hide + (fp_text reference C31 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) + (fp_text user %R (at 0 1.2192) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 31.9278 -26.6192 270) + (path /57D849FD/5802406C) + (attr smd) + (fp_text reference C32 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 1.9812 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.54 -1.27) (end -2.54 0) (layer F.Fab) (width 0.1)) - (fp_line (start -2.54 0) (end -1.27 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 1.27) (end 2.54 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 1.27) (end 2.54 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.Fab) (width 0.1)) - (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 169 "Net-(JP2-Pad2)")) - (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 243 /Power/15V_LDO_ENABLE)) - (model "wrlshp/User Library-Header1x2.wrl" - (offset (xyz 5.675121914768218 11.80693582267761 -6.799998997874261)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/3416A7AC-A52A.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:PLD-6 (layer F.Cu) (tedit 60BDD7F2) (tstamp 539EEDBF) - (at 41.04639 -12.5222 90) - (path /57D84CB3/58023FEF) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 30.5308 -41.4782 90) + (path /57D849FD/58024053) (attr smd) - (fp_text reference J2 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C33 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value "2x3 .1\" header" (at 0 0 90) (layer Cmts.User) + (fp_text user %R (at -2.1082 -0.0508 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.9346 -49.784 90) + (path /57D849FD/58024061) + (attr smd) + (fp_text reference C34 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 2.032 0.0254 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.54 3.81) (end 2.54 3.81) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 3.81) (end 2.54 -3.81) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 -3.81) (end -1.27 -3.81) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 -3.81) (end -2.54 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -2.54 -2.54) (end -2.54 3.81) (layer F.Fab) (width 0.1)) - (pad 1 thru_hole rect (at -1.27 -2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 thru_hole circle (at 1.27 -2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 144 FT_VREGIN)) - (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 234 "/User USB UART/USB_P")) - (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 233 "/User USB UART/USB_N")) - (pad 5 thru_hole circle (at -1.27 2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 239 "/User USB UART/FT_RXD1")) - (pad 6 thru_hole circle (at 1.27 2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 240 "/User USB UART/FT_TXD1")) - (model wrlshp/pin_header_awl254-dg-g06d.wrl - (offset (xyz 0 -0.009905999851226806 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 90 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/B3089A96-FA19.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:PLD-6 (layer F.Cu) (tedit 60BDD7F2) (tstamp 539EEDBF) - (at 74.90459 -12.5222 90) - (path /57D84E30/58023FB9) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 37.8 -20.5 90) + (path /57D849FD/58024054) (attr smd) - (fp_text reference J3 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C35 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value "2x3 .1\" header" (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 2.106 0.046 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -2.54 3.81) (end 2.54 3.81) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 3.81) (end 2.54 -3.81) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 -3.81) (end -1.27 -3.81) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 -3.81) (end -2.54 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -2.54 -2.54) (end -2.54 3.81) (layer F.Fab) (width 0.1)) - (pad 1 thru_hole rect (at -1.27 -2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 2 thru_hole circle (at 1.27 -2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 137 FT_MGMT_VREGIN)) - (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 236 "/MGMT USB UART/USB_MGMT_P")) - (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 235 "/MGMT USB UART/USB_MGMT_N")) - (pad 5 thru_hole circle (at -1.27 2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 241 "/MGMT USB UART/FT_MGMT_RXD1")) - (pad 6 thru_hole circle (at 1.27 2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 242 "/MGMT USB UART/FT_MGMT_TXD1")) - (model wrlshp/pin_header_awl254-dg-g06d.wrl - (offset (xyz 0 -0.009905999851226806 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 90 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/B3089A96-FA19.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:PLD-6 (layer F.Cu) (tedit 60BDD7F2) (tstamp 539EEDBF) - (at 18.25 -29.475) - (path /57D85260/58023F3C) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 65.4304 -29.7434 90) + (path /57D849FD/58024062) (attr smd) - (fp_text reference JP7 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C36 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at -0.0254 1.1176 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.54 3.81) (end 2.54 3.81) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 3.81) (end 2.54 -3.81) (layer F.Fab) (width 0.1)) - (fp_line (start 2.54 -3.81) (end -1.27 -3.81) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 -3.81) (end -2.54 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -2.54 -2.54) (end -2.54 3.81) (layer F.Fab) (width 0.1)) - (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 91 FPGA_CFG_CTRL_ARM_ENA)) - (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 231 "/Config memory/SPI_A_TRISTATE")) - (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 92 FPGA_CFG_CTRL_FPGA_DIS)) - (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 227 "/Config memory/SPI_B_TRISTATE")) - (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 232 "/Config memory/FPGA_PROM_W_N")) - (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (model wrlshp/pin_header_awl254-dg-g06d.wrl - (offset (xyz 0 -0.009905999851226806 0)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 90 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/B3089A96-FA19.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:PLD-16 (layer F.Cu) (tedit 60BDD74B) (tstamp 539EEDBF) - (at 59.58299 -97.7646) - (path /57D854CB/58023EF9) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 39.2 -20.3 90) + (path /57D849FD/58024055) (attr smd) - (fp_text reference SV2 (at 0 0) (layer F.SilkS) hide + (fp_text reference C37 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 2.052 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 8.89 -2.54) (end -10.16 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 10.16 -1.27) (end 8.89 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 10.16 2.54) (end 10.16 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -10.16 2.54) (end 10.16 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -10.16 -2.54) (end -10.16 2.54) (layer F.Fab) (width 0.1)) - (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 210 VCCO_3V3)) - (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 210 VCCO_3V3)) - (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 210 VCCO_3V3)) - (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 3 GND)) - (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 3 GND)) - (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 99 FPGA_GPIO_A_0)) - (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 100 FPGA_GPIO_A_1)) - (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 101 FPGA_GPIO_A_2)) - (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 102 FPGA_GPIO_A_3)) - (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 47.7266 -15.9512) + (path /57D849FD/58024064) + (attr smd) + (fp_text reference C38 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at -2.0066 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 103 FPGA_GPIO_A_4)) - (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 104 FPGA_GPIO_A_5)) - (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 105 FPGA_GPIO_A_6)) - (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 106 FPGA_GPIO_A_7)) - (model wrlshp/pin_header_awl254-dg-g16d.wrl - (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 90 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/B280C847-2543.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:PLD-16 (layer F.Cu) (tedit 60BDD74B) (tstamp 539EEDBF) - (at 36.79919 -97.7646) - (path /57D854CB/58023EF4) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 54.6862 -15.9512) + (path /57D849FD/58024056) (attr smd) - (fp_text reference SV3 (at 0 0) (layer F.SilkS) hide + (fp_text reference C39 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (fp_text user %R (at 0 1.2192) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 31.9278 -45.1358 270) + (path /57D849FD/58024065) + (attr smd) + (fp_text reference C40 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 0 0.9398 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start 8.89 -2.54) (end -10.16 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 10.16 -1.27) (end 8.89 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 10.16 2.54) (end 10.16 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -10.16 2.54) (end 10.16 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -10.16 -2.54) (end -10.16 2.54) (layer F.Fab) (width 0.1)) - (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 31.9278 -41.4782 90) + (path /57D849FD/58024057) + (attr smd) + (fp_text reference C41 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at -2.1082 0.0762 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 66.294 -21.971) + (path /57D849FD/58024066) + (attr smd) + (fp_text reference C42 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 1.143) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 39.2176 -49.3522) + (path /57D849FD/58024058) + (attr smd) + (fp_text reference C43 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 -0.9398) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 45.6438 -49.3522 180) + (path /57D849FD/58024067) + (attr smd) + (fp_text reference C44 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 1.9558 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 107 FPGA_GPIO_B_0)) - (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 108 FPGA_GPIO_B_1)) - (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 109 FPGA_GPIO_B_2)) - (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 110 FPGA_GPIO_B_3)) - (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 65.4304 -40.6146 90) + (path /57D849FD/58024059) + (attr smd) + (fp_text reference C45 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 1.1176 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 31.9278 -31.877 270) + (path /57D849FD/58024068) + (attr smd) + (fp_text reference C46 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 0.9398 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 111 FPGA_GPIO_B_4)) - (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 112 FPGA_GPIO_B_5)) - (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 113 FPGA_GPIO_B_6)) - (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 114 FPGA_GPIO_B_7)) - (model wrlshp/pin_header_awl254-dg-g16d.wrl - (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 90 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/B280C847-2543.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:NDY (layer B.Cu) (tedit 60BDD618) (tstamp 539EEDBF) - (at 22.2758 -78.2828) - (path /57D84708/580240B7) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 94.0562 -38.608 270) + (path /57D84B22/5802402F) (attr smd) - (fp_text reference U1 (at 0 0) (layer F.SilkS) hide + (fp_text reference C47 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value LMZ13608TZ/NOPB (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at -7.62 0) (layer B.Fab) - (effects (font (size 5 5) (thickness 0.5)) (justify mirror)) + (fp_text user %R (at 0 -1.1938 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start 2.54 7.62) (end -16.51 7.62) (layer B.Fab) (width 0.1)) - (fp_line (start -16.51 7.62) (end -16.51 -7.62) (layer B.Fab) (width 0.1)) - (fp_line (start -16.51 -7.62) (end 2.54 -7.62) (layer B.Fab) (width 0.1)) - (fp_line (start 2.54 -7.62) (end 2.54 7.62) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy 2.54 -7.62) (xy -2.54 -7.62) (xy -2.54 -5.08) (xy 2.54 -5.08)) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at 0 -6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 202 PWR_18V)) - (pad 2 smd rect (at 0 -5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 202 PWR_18V)) - (pad 3 smd rect (at 0 -3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 4 smd rect (at 0 -2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 189 "Net-(R3-Pad2)")) - (pad 5 smd rect (at 0 -1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 6 smd rect (at 0 0 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 7 smd rect (at 0 1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 190 "Net-(R8-Pad1)")) - (pad TP1 smd rect (at -9.525 0 90) (size 9.144 13.3858) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 8 smd rect (at 0 2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 149 "Net-(C5-Pad1)")) - (pad 9 smd rect (at 0 3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 270 "Net-(U1-Pad9)")) - (pad 10 smd rect (at 0 5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 11 smd rect (at 0 6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:LQFP-48 (layer F.Cu) (tedit 60BDD4EE) (tstamp 539EEDBF) - (at 13.8186 -9.636 90) - (path /57D84CB3/58024000) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 78.105 -41.2274 270) + (path /57D84B22/58024030) (attr smd) - (fp_text reference U8 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C48 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value FT232HL-REEL (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 4 4) (thickness 0.2))) + (fp_text user %R (at 0 1.143 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -5.08 -5.08) (end 5.08 -5.08) (layer F.Fab) (width 0.1)) - (fp_line (start 5.08 -5.08) (end 5.08 5.08) (layer F.Fab) (width 0.1)) - (fp_line (start 5.08 5.08) (end -5.08 5.08) (layer F.Fab) (width 0.1)) - (fp_line (start -5.08 5.08) (end -5.08 -5.08) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy -3.048 5.08) (xy -5.08 5.08) (xy -5.08 3.048) (xy -3.048 3.048)) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -2.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 155 "Net-(C75-Pad2)")) - (pad 2 smd rect (at -2.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 156 "Net-(C78-Pad2)")) - (pad 3 smd rect (at -1.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 142 FT_VPHY)) - (pad 4 smd rect (at -1.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 5 smd rect (at -0.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 249 "/User USB UART/FT_REF")) - (pad 6 smd rect (at -0.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 233 "/User USB UART/USB_N")) - (pad 7 smd rect (at 0.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 234 "/User USB UART/USB_P")) - (pad 8 smd rect (at 0.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 143 FT_VPLL)) - (pad 9 smd rect (at 1.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 10 smd rect (at 1.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 11 smd rect (at 2.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 12 smd rect (at 2.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (pad 13 smd rect (at 4.05 2.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 240 "/User USB UART/FT_TXD1")) - (pad 14 smd rect (at 4.05 2.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 239 "/User USB UART/FT_RXD1")) - (pad 15 smd rect (at 4.05 1.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 138 FT_RTS)) - (pad 16 smd rect (at 4.05 1.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 127 FT_CTS)) - (pad 17 smd rect (at 4.05 0.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 128 FT_DTR)) - (pad 18 smd rect (at 4.05 0.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 316 "Net-(U8-Pad18)")) - (pad 19 smd rect (at 4.05 -0.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 317 "Net-(U8-Pad19)")) - (pad 20 smd rect (at 4.05 -0.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 318 "Net-(U8-Pad20)")) - (pad 21 smd rect (at 4.05 -1.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 319 "Net-(U8-Pad21)")) - (pad 22 smd rect (at 4.05 -1.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 23 smd rect (at 4.05 -2.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 24 smd rect (at 4.05 -2.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (pad 25 smd rect (at 2.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 320 "Net-(U8-Pad25)")) - (pad 26 smd rect (at 2.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 321 "Net-(U8-Pad26)")) - (pad 27 smd rect (at 1.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 322 "Net-(U8-Pad27)")) - (pad 28 smd rect (at 1.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 323 "Net-(U8-Pad28)")) - (pad 29 smd rect (at 0.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 324 "Net-(U8-Pad29)")) - (pad 30 smd rect (at 0.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 325 "Net-(U8-Pad30)")) - (pad 31 smd rect (at -0.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 326 "Net-(U8-Pad31)")) - (pad 32 smd rect (at -0.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 327 "Net-(U8-Pad32)")) - (pad 33 smd rect (at -1.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 328 "Net-(U8-Pad33)")) - (pad 34 smd rect (at -1.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 250 "/User USB UART/FT_RESET")) - (pad 35 smd rect (at -2.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 36 smd rect (at -2.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 37 smd rect (at -4.05 -2.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 218 "/User USB UART/FT_VCCA")) - (pad 38 smd rect (at -4.05 -2.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 217 "/User USB UART/FT_VCCORE")) - (pad 39 smd rect (at -4.05 -1.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (pad 40 smd rect (at -4.05 -1.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 144 FT_VREGIN)) - (pad 41 smd rect (at -4.05 -0.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 42 smd rect (at -4.05 -0.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 43 smd rect (at -4.05 0.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 329 "Net-(U8-Pad43)")) - (pad 44 smd rect (at -4.05 0.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 330 "Net-(U8-Pad44)")) - (pad 45 smd rect (at -4.05 1.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 331 "Net-(U8-Pad45)")) - (pad 46 smd rect (at -4.05 1.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (pad 47 smd rect (at -4.05 2.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 48 smd rect (at -4.05 2.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model wrlshp/SW3dPS-LQFP48.wrl + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 0)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/6B6B27F8-B7AC.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:LQFP-48 (layer F.Cu) (tedit 60BDD4EE) (tstamp 539EEDBF) - (at 86.3854 -17.8496) - (path /57D84E30/58023FCA) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 94.0562 -55.9054 270) + (path /57D84B22/58024031) (attr smd) - (fp_text reference U9 (at 0 0) (layer F.SilkS) hide + (fp_text reference C49 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value FT232HL-REEL (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 4 4) (thickness 0.2))) + (fp_text user %R (at 0.0254 -1.1938 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -5.08 -5.08) (end 5.08 -5.08) (layer F.Fab) (width 0.1)) - (fp_line (start 5.08 -5.08) (end 5.08 5.08) (layer F.Fab) (width 0.1)) - (fp_line (start 5.08 5.08) (end -5.08 5.08) (layer F.Fab) (width 0.1)) - (fp_line (start -5.08 5.08) (end -5.08 -5.08) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy -3.048 5.08) (xy -5.08 5.08) (xy -5.08 3.048) (xy -3.048 3.048)) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 157 "Net-(C90-Pad2)")) - (pad 2 smd rect (at -2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 158 "Net-(C93-Pad2)")) - (pad 3 smd rect (at -1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 135 FT_MGMT_VPHY)) - (pad 4 smd rect (at -1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 5 smd rect (at -0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 251 "/MGMT USB UART/FT_REF1")) - (pad 6 smd rect (at -0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 235 "/MGMT USB UART/USB_MGMT_N")) - (pad 7 smd rect (at 0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 236 "/MGMT USB UART/USB_MGMT_P")) - (pad 8 smd rect (at 0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 136 FT_MGMT_VPLL)) - (pad 9 smd rect (at 1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 10 smd rect (at 1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 11 smd rect (at 2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 12 smd rect (at 2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (pad 13 smd rect (at 4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 242 "/MGMT USB UART/FT_MGMT_TXD1")) - (pad 14 smd rect (at 4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 241 "/MGMT USB UART/FT_MGMT_RXD1")) - (pad 15 smd rect (at 4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 131 FT_MGMT_RTS)) - (pad 16 smd rect (at 4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 129 FT_MGMT_CTS)) - (pad 17 smd rect (at 4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 130 FT_MGMT_DTR)) - (pad 18 smd rect (at 4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 332 "Net-(U9-Pad18)")) - (pad 19 smd rect (at 4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 333 "Net-(U9-Pad19)")) - (pad 20 smd rect (at 4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 334 "Net-(U9-Pad20)")) - (pad 21 smd rect (at 4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 335 "Net-(U9-Pad21)")) - (pad 22 smd rect (at 4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 23 smd rect (at 4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 24 smd rect (at 4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (pad 25 smd rect (at 2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 336 "Net-(U9-Pad25)")) - (pad 26 smd rect (at 2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 337 "Net-(U9-Pad26)")) - (pad 27 smd rect (at 1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 338 "Net-(U9-Pad27)")) - (pad 28 smd rect (at 1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 339 "Net-(U9-Pad28)")) - (pad 29 smd rect (at 0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 340 "Net-(U9-Pad29)")) - (pad 30 smd rect (at 0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 341 "Net-(U9-Pad30)")) - (pad 31 smd rect (at -0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 342 "Net-(U9-Pad31)")) - (pad 32 smd rect (at -0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 343 "Net-(U9-Pad32)")) - (pad 33 smd rect (at -1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 344 "Net-(U9-Pad33)")) - (pad 34 smd rect (at -1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 252 "/MGMT USB UART/FT_RESET1")) - (pad 35 smd rect (at -2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 36 smd rect (at -2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 37 smd rect (at -4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 220 "/MGMT USB UART/FT_VCCA1")) - (pad 38 smd rect (at -4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 219 "/MGMT USB UART/FT_VCCORE1")) - (pad 39 smd rect (at -4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (pad 40 smd rect (at -4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 137 FT_MGMT_VREGIN)) - (pad 41 smd rect (at -4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 42 smd rect (at -4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 43 smd rect (at -4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 345 "Net-(U9-Pad43)")) - (pad 44 smd rect (at -4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 346 "Net-(U9-Pad44)")) - (pad 45 smd rect (at -4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 347 "Net-(U9-Pad45)")) - (pad 46 smd rect (at -4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (pad 47 smd rect (at -4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 48 smd rect (at -4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model wrlshp/SW3dPS-LQFP48.wrl + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 0)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/6B6B27F8-B7AC.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:L_1206 (layer B.Cu) (tedit 60BDD442) (tstamp 539EEDBF) - (at 41.4528 -84.2772 270) - (path /57D853B0/58023F06) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 78.105 -58.3946 90) + (path /57D84B22/58024033) (attr smd) - (fp_text reference FB5 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C50 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BLM31PG330SN1 (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 0.0254 -1.143 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.016 2.286) (end 1.016 2.286) (layer B.Fab) (width 0.1)) - (fp_line (start 1.016 2.286) (end 1.016 -2.286) (layer B.Fab) (width 0.1)) - (fp_line (start 1.016 -2.286) (end -1.016 -2.286) (layer B.Fab) (width 0.1)) - (fp_line (start -1.016 -2.286) (end -1.016 2.286) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.4 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad 1 smd rect (at 0 1.4 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (model "wrlshp/User Library-V1206HD.wrl" - (offset (xyz 0.05003799924850464 0 0)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 270)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/76148CD0-6DD3.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:L_1206 (layer B.Cu) (tedit 60BDD442) (tstamp 539EEDBF) - (at 7.7978 -33.147 270) - (path /57D853B0/58023F14) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 94.0562 -45.9232 270) + (path /57D84B22/58024032) (attr smd) - (fp_text reference FB6 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C51 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BLM31PG330SN1 (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 0 -1.1938 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.016 2.286) (end 1.016 2.286) (layer B.Fab) (width 0.1)) - (fp_line (start 1.016 2.286) (end 1.016 -2.286) (layer B.Fab) (width 0.1)) - (fp_line (start 1.016 -2.286) (end -1.016 -2.286) (layer B.Fab) (width 0.1)) - (fp_line (start -1.016 -2.286) (end -1.016 2.286) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.4 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 1 smd rect (at 0 1.4 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (model "wrlshp/User Library-V1206HD.wrl" - (offset (xyz 0.05003799924850464 0 0)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 270)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/76148CD0-6DD3.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:L_1206 (layer B.Cu) (tedit 60BDD442) (tstamp 539EEDBF) - (at 39.624 -58.2168) - (path /57D85A75/58023E22) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 78.105 -55.5244 90) + (path /57D84B22/58024034) (attr smd) - (fp_text reference FB7 (at 0 0) (layer F.SilkS) hide + (fp_text reference C52 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value BLM31PG330SN1 (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 -90) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 0.1016 -1.143 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.016 2.286) (end 1.016 2.286) (layer B.Fab) (width 0.1)) - (fp_line (start 1.016 2.286) (end 1.016 -2.286) (layer B.Fab) (width 0.1)) - (fp_line (start 1.016 -2.286) (end -1.016 -2.286) (layer B.Fab) (width 0.1)) - (fp_line (start -1.016 -2.286) (end -1.016 2.286) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 1 smd rect (at 0 1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (model "wrlshp/User Library-V1206HD.wrl" - (offset (xyz 0.05003799924850464 0 0)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 270)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/76148CD0-6DD3.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:L_0603 (layer F.Cu) (tedit 60BDD397) (tstamp 539EEDBF) - (at 27.3512 -15.7226) - (path /57D84CB3/58023FF4) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 94.0562 -60.9934 90) + (path /57D84B22/58024043) (attr smd) - (fp_text reference FB1 (at 0 0) (layer F.SilkS) hide + (fp_text reference C53 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value FBMH1608HL601-T (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05))) + (fp_text user %R (at 0 1.1938 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) - (net 142 FT_VPHY)) - (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (model "wrlshp/User Library-V0603HD.wrl" + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/AF13F747-700F.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:L_0603 (layer F.Cu) (tedit 60BDD397) (tstamp 539EEDBF) - (at 20.7528 -14.9192 90) - (path /57D84CB3/58023FF6) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 94.0562 -40.9956 90) + (path /57D84B22/58024035) (attr smd) - (fp_text reference FB2 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C54 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value FBMH1608HL601-T (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05))) + (fp_text user %R (at 0 1.1938 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 0.85 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) - (net 143 FT_VPLL)) - (pad 1 smd rect (at 0 -0.85 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (model "wrlshp/User Library-V0603HD.wrl" + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/AF13F747-700F.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:L_0603 (layer F.Cu) (tedit 60BDD397) (tstamp 539EEDBF) - (at 93.218 -10.9662) - (path /57D84E30/58023FBE) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 94.0562 -58.8772 270) + (path /57D84B22/58024044) (attr smd) - (fp_text reference FB3 (at 0 0) (layer F.SilkS) hide + (fp_text reference C55 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value FBMH1608HL601-T (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05))) + (fp_text user %R (at 0 -1.1938 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) - (net 135 FT_MGMT_VPHY)) - (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (model "wrlshp/User Library-V0603HD.wrl" + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/AF13F747-700F.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:L_0603 (layer F.Cu) (tedit 60BDD397) (tstamp 539EEDBF) - (at 91.186 -10.9662) - (path /57D84E30/58023FC0) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 78.105 -45.3644 90) + (path /57D84B22/5802403B) (attr smd) - (fp_text reference FB4 (at 0 0) (layer F.SilkS) hide + (fp_text reference C56 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value FBMH1608HL601-T (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05))) + (fp_text user %R (at 0 -1.143 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) - (net 136 FT_MGMT_VPLL)) - (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (model "wrlshp/User Library-V0603HD.wrl" + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 360 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/AF13F747-700F.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:HDR1X10 (layer F.Cu) (tedit 60BDD308) (tstamp 539EEDBF) - (at 31.5 6) - (path /57D84FAD/58023F9D) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 94.0562 -52.9082 270) + (path /57D84B22/58024045) (attr smd) - (fp_text reference JP5 (at 0 0) (layer F.SilkS) hide + (fp_text reference C57 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value PLS-10 (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 11.43 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) + (fp_text user %R (at 0 -1.1938 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.27 -1.27) (end -1.27 0) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 0) (end 0 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 0 1.27) (end 24.13 1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 24.13 1.27) (end 24.13 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 24.13 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1)) - (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 595 ICE40_GPIO_1)) - (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 596 ICE40_GPIO_7)) - (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 597 ICE40_GPIO_6)) - (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 598 ICE40_GPIO_5)) - (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 599 ICE40_GPIO_4)) - (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 600 ICE40_GPIO_3)) - (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 601 ICE40_GPIO_2)) - (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 602 ICE40_GPIO_0)) - (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) - (net 1 3V3_BATT)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:CRYSTAL_3.2X2.5 (layer F.Cu) (tedit 60BDD26D) (tstamp 539EEDBF) - (at 82.525 -8.8) - (path /57D84E30/58023FB6) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 72.8222 -40.8924 90) + (path /57D84B22/58024039) (attr smd) - (fp_text reference Y2 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C58 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value ABM8G-12.000MHZ-4Y-T3 (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0.762) (layer F.Fab) - (effects (font (size 1.2 1.2) (thickness 0.1))) + (fp_text user %R (at 0 -0.9402 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.286 -1.778) (end 2.286 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 2.286 -1.778) (end 2.286 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 2.286 1.778) (end -2.286 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -2.286 1.778) (end -2.286 -1.778) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy 2.286 -0.254) (xy 0.508 -0.254) (xy 0.508 -1.778) (xy 2.286 -1.778)) (layer F.Fab) (width 0.1)) - (pad 4 smd rect (at 1.1176 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 3 smd rect (at -1.0922 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) - (net 157 "Net-(C90-Pad2)")) - (pad 2 smd rect (at -1.0922 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 72.8472 -38.6826 270) + (path /57D84B22/5802403A) + (attr smd) + (fp_text reference C59 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 0.9652 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 1 smd rect (at 1.1176 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) - (net 158 "Net-(C93-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:CRYSTAL_3.2X2.5 (layer F.Cu) (tedit 60BDD26D) (tstamp 539EEDBF) - (at 23.075 -5.5 90) - (path /57D84CB3/58023FEC) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 72.8472 -60.9568 90) + (path /57D84B22/5802403C) (attr smd) - (fp_text reference Y1 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C60 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value ABM8G-12.000MHZ-4Y-T3 (at 0 0 90) (layer Cmts.User) + (fp_text user %R (at 0 -0.9652 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 88.7222 -58.666 90) + (path /57D84B22/5802403E) + (attr smd) + (fp_text reference C61 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0.762 90) (layer F.Fab) - (effects (font (size 1.2 1.2) (thickness 0.1))) + (fp_text user %R (at 0 1.1938 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.286 -1.778) (end 2.286 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 2.286 -1.778) (end 2.286 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 2.286 1.778) (end -2.286 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -2.286 1.778) (end -2.286 -1.778) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy 2.286 -0.254) (xy 0.508 -0.254) (xy 0.508 -1.778) (xy 2.286 -1.778)) (layer F.Fab) (width 0.1)) - (pad 4 smd rect (at 1.1176 0.8636 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 3 smd rect (at -1.0922 0.8636 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) - (net 155 "Net-(C75-Pad2)")) - (pad 2 smd rect (at -1.0922 -0.8382 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 72.8472 -52.6288 270) + (path /57D84B22/5802403D) + (attr smd) + (fp_text reference C62 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0.0508 0.9652 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 1 smd rect (at 1.1176 -0.8382 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) - (net 156 "Net-(C78-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:CRYSTAL_3.2X2.5 (layer B.Cu) (tedit 60BDD26D) (tstamp 539EEDBF) - (at 28.3 -34.975) - (path /57D84936/58024088) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 88.7222 -41.148 270) + (path /57D84B22/5802403F) (attr smd) - (fp_text reference Q3 (at 0 0) (layer F.SilkS) hide + (fp_text reference C63 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value ABM8G-25.000MHZ-4Y-T3 (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 -0.762) (layer B.Fab) - (effects (font (size 1.2 1.2) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 0 -1.1938 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -2.286 1.778) (end 2.286 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 2.286 1.778) (end 2.286 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 2.286 -1.778) (end -2.286 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -2.286 -1.778) (end -2.286 1.778) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy 2.286 0.254) (xy 0.508 0.254) (xy 0.508 1.778) (xy 2.286 1.778)) (layer B.Fab) (width 0.1)) - (pad 4 smd rect (at 1.1176 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 3 smd rect (at -1.0922 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) - (net 213 "/STM32 configuration/OSC_OUT")) - (pad 2 smd rect (at -1.0922 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 72.8472 -58.5978 270) + (path /57D84B22/58024036) + (attr smd) + (fp_text reference C64 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 0.9652 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 1 smd rect (at 1.1176 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) - (net 152 "Net-(C17-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:C_D (layer B.Cu) (tedit 60BDD1BE) (tstamp 539EEDBF) - (at 10.4648 -54.5846) - (path /57D84708/580240B3) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 88.7222 -55.5458 90) + (path /57D84B22/58024040) (attr smd) - (fp_text reference C9 (at 0 0) (layer F.SilkS) hide + (fp_text reference C65 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 330uF (at 0 0) (layer Cmts.User) + (fp_text user %R (at 0 1.1938 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 72.8472 -45.5422 270) + (path /57D84B22/58024037) + (attr smd) + (fp_text reference C66 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at -0.254 0) (layer B.Fab) + (fp_text user %R (at 0 0.9652 90) (layer B.Fab) (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -4.826 1.778) (end 4.826 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 4.826 1.778) (end 4.826 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 4.826 -1.778) (end -4.826 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -4.826 -1.778) (end -4.826 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 4.572 2.032) (end 4.572 3.048) (layer B.Fab) (width 0.1)) - (fp_line (start 4.064 2.54) (end 5.08 2.54) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy 4.826 -1.778) (xy 4.318 -1.778) (xy 4.318 1.778) (xy 4.826 1.778)) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at -3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 1 smd rect (at 3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (model wrlshp/SW3dPS-cap_d.wrl - (offset (xyz -0.05003799924850464 -0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/5917D381-109F.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_D (layer B.Cu) (tedit 60BDD1BE) (tstamp 539EEDBF) - (at 10.4648 -61.0616) - (path /57D84708/580240B2) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 88.7222 -45.4874 90) + (path /57D84B22/58024041) (attr smd) - (fp_text reference C10 (at 0 0) (layer F.SilkS) hide + (fp_text reference C67 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 330uF (at 0 0) (layer Cmts.User) + (fp_text user %R (at 0 1.1938 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 72.8472 -55.6514 270) + (path /57D84B22/58024038) + (attr smd) + (fp_text reference C68 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at -0.254 0) (layer B.Fab) + (fp_text user %R (at 0 0.9652 90) (layer B.Fab) (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -4.826 1.778) (end 4.826 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 4.826 1.778) (end 4.826 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 4.826 -1.778) (end -4.826 -1.778) (layer B.Fab) (width 0.1)) - (fp_line (start -4.826 -1.778) (end -4.826 1.778) (layer B.Fab) (width 0.1)) - (fp_line (start 4.572 2.032) (end 4.572 3.048) (layer B.Fab) (width 0.1)) - (fp_line (start 4.064 2.54) (end 5.08 2.54) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy 4.826 -1.778) (xy 4.318 -1.778) (xy 4.318 1.778) (xy 4.826 1.778)) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at -3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 1 smd rect (at 3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (model wrlshp/SW3dPS-cap_d.wrl - (offset (xyz -0.05003799924850464 -0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/5917D381-109F.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_D (layer F.Cu) (tedit 60BDD1BE) (tstamp 539EEDBF) - (at 79.7052 -71.501 270) - (path /57D855DE/58023E8E) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 39.1 -51.675) + (path /57D84C13/58024029) (attr smd) - (fp_text reference C123 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C69 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 330uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at -0.254 0 90) (layer F.Fab) + (fp_text user %R (at 0.016 -1.157) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -4.826 -1.778) (end 4.826 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 4.826 -1.778) (end 4.826 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 4.826 1.778) (end -4.826 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -4.826 1.778) (end -4.826 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 4.572 -2.032) (end 4.572 -3.048) (layer F.Fab) (width 0.1)) - (fp_line (start 4.064 -2.54) (end 5.08 -2.54) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy 4.826 1.778) (xy 4.318 1.778) (xy 4.318 -1.778) (xy 4.826 -1.778)) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at -3.25 0 90) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 3.25 0 90) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (model wrlshp/SW3dPS-cap_d.wrl - (offset (xyz -0.05003799924850464 -0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/5917D381-109F.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_D (layer F.Cu) (tedit 60BDD1BE) (tstamp 539EEDBF) - (at 54.8754 -90.997) - (path /57D855DE/58023E8D) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 22.1 -47.875 270) + (path /57D84C55/5802401F) (attr smd) - (fp_text reference C127 (at 0 0) (layer F.SilkS) hide + (fp_text reference C70 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 330uF (at 0 0) (layer Cmts.User) + (fp_text value 5.1pF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at -0.254 0) (layer F.Fab) + (fp_text user %R (at -0.131 -1.014 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -4.826 -1.778) (end 4.826 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 4.826 -1.778) (end 4.826 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 4.826 1.778) (end -4.826 1.778) (layer F.Fab) (width 0.1)) - (fp_line (start -4.826 1.778) (end -4.826 -1.778) (layer F.Fab) (width 0.1)) - (fp_line (start 4.572 -2.032) (end 4.572 -3.048) (layer F.Fab) (width 0.1)) - (fp_line (start 4.064 -2.54) (end 5.08 -2.54) (layer F.Fab) (width 0.1)) - (fp_poly (pts (xy 4.826 1.778) (xy 4.318 1.778) (xy 4.318 -1.778) (xy 4.826 -1.778)) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at -3.25 0 180) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 3.25 0 180) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (model wrlshp/SW3dPS-cap_d.wrl - (offset (xyz -0.05003799924850464 -0 0)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 153 "Net-(C70-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 180)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/5917D381-109F.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 21.463 -99.0854 270) - (path /57D84708/580240AD) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 19.3 -40.9 90) + (path /57D84C55/58024020) (attr smd) - (fp_text reference C1 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C71 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 10uF (at 0 0 90) (layer Cmts.User) + (fp_text value 5.1pF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at -0.006 -1.012 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 202 PWR_18V)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 154 "Net-(C71-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 21.463 -94.0689 270) - (path /57D84708/580240C1) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 12.37202 -7.06602 180) + (path /57D84CB3/58023FE5) (attr smd) - (fp_text reference C2 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C73 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value 10uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 0 1.06198) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 144 FT_VREGIN)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 202 PWR_18V)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 21.463 -89.0524 270) - (path /57D84708/580240C0) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 10.7198 -3.1844 270) + (path /57D84CB3/58023FEA) (attr smd) - (fp_text reference C3 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C74 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 10uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 2.1684 0.0518 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 217 "/User USB UART/FT_VCCORE")) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 202 PWR_18V)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 15.2908 -67.3354 90) - (path /57D84708/580240BF) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 19.8892 -4.8608 90) + (path /57D84CB3/58023FE7) (attr smd) - (fp_text reference C8 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C75 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 5.1pF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at -0.0348 0.9388 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5 180) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5 180) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 155 "Net-(C75-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 40.0558 -72.6186) - (path /57D853B0/58023F19) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 9.2974 -3.1844 270) + (path /57D84CB3/58023FEB) (attr smd) - (fp_text reference C113 (at 0 0) (layer F.SilkS) hide + (fp_text reference C76 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 22uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 -90) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 2.1684 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 218 "/User USB UART/FT_VCCA")) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 6.4008 -44.9326 180) - (path /57D853B0/58023F05) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 19.8892 -7.1976 270) + (path /57D84CB3/58023FE8) (attr smd) - (fp_text reference C114 (at 0 0) (layer F.SilkS) hide + (fp_text reference C78 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 22uF (at 0 0) (layer Cmts.User) + (fp_text value 5.1pF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 0.0856 -0.9388 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 156 "Net-(C78-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 40.0558 -79.4004 180) - (path /57D853B0/58023F0F) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 22.325 -10.025 90) + (path /57D84CB3/58023FFD) (attr smd) - (fp_text reference C119 (at 0 0) (layer F.SilkS) hide + (fp_text reference C79 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0.389 1.043 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 142 FT_VPHY)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 6.4008 -38.5826) - (path /57D853B0/58023F0D) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 19.8892 -10.7282 90) + (path /57D84CB3/58023FFB) (attr smd) - (fp_text reference C120 (at 0 0) (layer F.SilkS) hide + (fp_text reference C81 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 -90) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0.1938 1.1928 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 143 FT_VPLL)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 47.9298 -84.5566 180) - (path /57D855DE/58023E8F) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 12.5486 -3.5654) + (path /57D84CB3/58023FFE) (attr smd) - (fp_text reference C126 (at 0 0) (layer F.SilkS) hide + (fp_text reference C83 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.1))) + (fp_text user %R (at 0 1.0254) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 1.5 90) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 -1.5 90) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 42.8498 -56.09135) - (path /57D855DE/58023E9B) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 16.0792 -3.5908) + (path /57D84CB3/58023FF9) (attr smd) - (fp_text reference C133 (at 0 0) (layer F.SilkS) hide + (fp_text reference C84 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.1))) + (fp_text user %R (at 0 1.0508) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 74.5236 -65.8114) - (path /57D855DE/58023E91) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 19.8892 -12.8364 270) + (path /57D84CB3/58023FF8) (attr smd) - (fp_text reference C137 (at 0 0) (layer F.SilkS) hide + (fp_text reference C85 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.1))) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.1176 -1.1928 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 63.7794 -85.0646 270) - (path /57D8583B/58023E40) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 11.5326 -15.7828) + (path /57D84CB3/58023FF7) (attr smd) - (fp_text reference C165 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C86 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.1))) + (fp_text user %R (at -0.1026 -0.9812) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 1.5 180) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 -1.5 180) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 68.834 -54.383) - (path /57D8583B/58023E3E) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 82.50838 -18.33486 270) + (path /57D84E30/58023FAF) (attr smd) - (fp_text reference C167 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C88 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value 47uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.1))) + (fp_text user %R (at 0 -1.05762 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 137 FT_MGMT_VREGIN)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 73.0758 -75.9714) - (path /57D8583B/58023E3C) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 79.9592 -20.8976 180) + (path /57D84E30/58023FB4) (attr smd) - (fp_text reference C168 (at 0 0) (layer F.SilkS) hide + (fp_text reference C89 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.1))) + (fp_text user %R (at 1.9812 -0.0696) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 219 "/MGMT USB UART/FT_VCCORE1")) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 22.0472 -50.6476 270) - (path /57D85A75/58023E27) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 81.8 -11.825) + (path /57D84E30/58023FB1) (attr smd) - (fp_text reference C205 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C90 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 22uF (at 0 0 90) (layer Cmts.User) + (fp_text value 5.1pF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at -6.616 2.681) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 157 "Net-(C90-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 22.0472 -46.2788 270) - (path /57D85A75/58023E26) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 79.925 -22.15 180) + (path /57D84E30/58023FB5) (attr smd) - (fp_text reference C206 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C91 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 22uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 1.947 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 220 "/MGMT USB UART/FT_VCCA1")) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 34.6964 -55.3466 180) - (path /57D85A75/58023E2B) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 84.0994 -11.8298 180) + (path /57D84E30/58023FB2) (attr smd) - (fp_text reference C209 (at 0 0) (layer F.SilkS) hide + (fp_text reference C93 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0) (layer Cmts.User) + (fp_text value 5.1pF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 6.3754 -2.6858) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 158 "Net-(C93-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 34.7472 -62.4078) - (path /57D85A75/58023E2A) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 86.1314 -11.4234 270) + (path /57D84E30/58023FC7) (attr smd) - (fp_text reference C210 (at 0 0) (layer F.SilkS) hide + (fp_text reference C94 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 -90) (layer B.Fab) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 7.3594 -4.8006 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) - (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 135 FT_MGMT_VPHY)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) - (at 42.291 -85.6996 270) - (path /57D8583B/58023E3F) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 87.7824 -11.4234 270) + (path /57D84E30/58023FC5) (attr smd) - (fp_text reference C166 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C96 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.1))) + (fp_text user %R (at 7.3594 -4.1656 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) - (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) - (pad 2 smd rect (at 0 1.5 180) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 136 FT_MGMT_VPLL)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 -1.5 180) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (model wrlshp/SW3dPS-CAPC3225.wrl - (offset (xyz 1.249933981227875 0 1.250000021226883)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/F26EE9BE-B6B0.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254 (layer B.Cu) (tedit 60BDCD8B) (tstamp 539EEDBF) - (at 56.4534 -68.8848) - (path /57D85134/58023F60) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 80.391 -16.097 270) + (path /57D84E30/58023FC8) (attr smd) - (fp_text reference U13 (at 0 0) (layer F.SilkS) hide + (fp_text reference C98 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value XC7A200T-1FBG484C (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 5 5) (thickness 0.5)) (justify mirror)) + (fp_text user %R (at 0.095 0.889 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -10.922 10.922) (end 10.922 10.922) (layer B.Fab) (width 0.1)) - (fp_line (start 10.922 10.922) (end 10.922 -10.922) (layer B.Fab) (width 0.1)) - (fp_line (start 10.922 -10.922) (end -10.922 -10.922) (layer B.Fab) (width 0.1)) - (fp_line (start -10.922 -10.922) (end -10.922 10.922) (layer B.Fab) (width 0.1)) - (fp_poly (pts (xy 10.922 -10.922) (xy 9.906 -10.922) (xy 9.906 -9.906) (xy 10.922 -9.906)) (layer B.Fab) (width 0.1)) - (pad AB22 smd circle (at -10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 34 FMC_A20)) - (pad AB21 smd circle (at -9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 33 FMC_A19)) - (pad AB20 smd circle (at -8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 35 FMC_A21)) - (pad AB19 smd circle (at -7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad AB18 smd circle (at -6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 38 FMC_A24)) - (pad AB17 smd circle (at -5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 18 FMC_A4)) - (pad AB16 smd circle (at -4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 15 FMC_A1)) - (pad AB15 smd circle (at -3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 22 FMC_A8)) - (pad AB14 smd circle (at -2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad AB13 smd circle (at -1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 20 FMC_A6)) - (pad AB12 smd circle (at -0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 28 FMC_A14)) - (pad AB11 smd circle (at 0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 45 FMC_D4)) - (pad AB10 smd circle (at 1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 26 FMC_A12)) - (pad AB9 smd circle (at 2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad AB8 smd circle (at 3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 29 FMC_A15)) - (pad AB7 smd circle (at 4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 41 FMC_D0)) - (pad AB6 smd circle (at 5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 42 FMC_D1)) - (pad AB5 smd circle (at 6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 61 FMC_D20)) - (pad AB4 smd circle (at 7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad AB3 smd circle (at 8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 57 FMC_D16)) - (pad AB2 smd circle (at 9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 56 FMC_D15)) - (pad AB1 smd circle (at 10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 55 FMC_D14)) - (pad AA22 smd circle (at -10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad AA21 smd circle (at -9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 50 FMC_D9)) - (pad AA20 smd circle (at -8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 118 FPGA_GPIO_LED_3)) - (pad AA19 smd circle (at -7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 39 FMC_A25)) - (pad AA18 smd circle (at -6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 351 "Net-(U13-PadAA18)")) - (pad AA17 smd circle (at -5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad AA16 smd circle (at -4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 16 FMC_A2)) - (pad AA15 smd circle (at -3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 21 FMC_A7)) - (pad AA14 smd circle (at -2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 24 FMC_A10)) - (pad AA13 smd circle (at -1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 19 FMC_A5)) - (pad AA12 smd circle (at -0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad AA11 smd circle (at 0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 46 FMC_D5)) - (pad AA10 smd circle (at 1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 352 "Net-(U13-PadAA10)")) - (pad AA9 smd circle (at 2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 30 FMC_A16)) - (pad AA8 smd circle (at 3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 31 FMC_A17)) - (pad AA7 smd circle (at 4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad AA6 smd circle (at 5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 81 FMC_NWE)) - (pad AA5 smd circle (at 6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 60 FMC_D19)) - (pad AA4 smd circle (at 7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 63 FMC_D22)) - (pad AA3 smd circle (at 8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 59 FMC_D18)) - (pad AA2 smd circle (at 9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad AA1 smd circle (at 10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 54 FMC_D13)) - (pad Y22 smd circle (at -10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 37 FMC_A23)) - (pad Y21 smd circle (at -9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 36 FMC_A22)) - (pad Y20 smd circle (at -8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad Y19 smd circle (at -7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 353 "Net-(U13-PadY19)")) - (pad Y18 smd circle (at -6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 49 FMC_D8)) - (pad Y17 smd circle (at -5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 14 FMC_A0)) - (pad Y16 smd circle (at -4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 17 FMC_A3)) - (pad Y15 smd circle (at -3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad Y14 smd circle (at -2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 25 FMC_A11)) - (pad Y13 smd circle (at -1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 23 FMC_A9)) - (pad Y12 smd circle (at -0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 48 FMC_D7)) - (pad Y11 smd circle (at 0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 47 FMC_D6)) - (pad Y10 smd circle (at 1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad Y9 smd circle (at 2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 354 "Net-(U13-PadY9)")) - (pad Y8 smd circle (at 3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 355 "Net-(U13-PadY8)")) - (pad Y7 smd circle (at 4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 32 FMC_A18)) - (pad Y6 smd circle (at 5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 80 FMC_NWAIT)) - (pad Y5 smd circle (at 6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad Y4 smd circle (at 7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 62 FMC_D21)) - (pad Y3 smd circle (at 8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 58 FMC_D17)) - (pad Y2 smd circle (at 9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 356 "Net-(U13-PadY2)")) - (pad Y1 smd circle (at 10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 608 ICE40_FPGA_MISO)) - (pad W22 smd circle (at -10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 117 FPGA_GPIO_LED_2)) - (pad W21 smd circle (at -9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 357 "Net-(U13-PadW21)")) - (pad W20 smd circle (at -8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 51 FMC_D10)) - (pad W19 smd circle (at -7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 13 DIGITIZED_NOISE)) - (pad W18 smd circle (at -6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad W17 smd circle (at -5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 78 FMC_NL)) - (pad W16 smd circle (at -4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 79 FMC_NOE)) - (pad W15 smd circle (at -3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 358 "Net-(U13-PadW15)")) - (pad W14 smd circle (at -2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 68 FMC_D27)) - (pad W13 smd circle (at -1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad W12 smd circle (at -0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 67 FMC_D26)) - (pad W11 smd circle (at 0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 40 FMC_CLK)) - (pad W10 smd circle (at 1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 65 FMC_D24)) - (pad W9 smd circle (at 2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 359 "Net-(U13-PadW9)")) - (pad W8 smd circle (at 3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad W7 smd circle (at 4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 360 "Net-(U13-PadW7)")) - (pad W6 smd circle (at 5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 361 "Net-(U13-PadW6)")) - (pad W5 smd circle (at 6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 362 "Net-(U13-PadW5)")) - (pad W4 smd circle (at 7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 363 "Net-(U13-PadW4)")) - (pad W3 smd circle (at 8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad W2 smd circle (at 9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 609 ICE40_FPGA_CS_N)) - (pad W1 smd circle (at 10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 610 ICE40_FPGA_MOSI)) - (pad V22 smd circle (at -10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 364 "Net-(U13-PadV22)")) - (pad V21 smd circle (at -9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad V20 smd circle (at -8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 69 FMC_D28)) - (pad V19 smd circle (at -7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 365 "Net-(U13-PadV19)")) - (pad V18 smd circle (at -6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 70 FMC_D29)) - (pad V17 smd circle (at -5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 366 "Net-(U13-PadV17)")) - (pad V16 smd circle (at -4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad V15 smd circle (at -3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 367 "Net-(U13-PadV15)")) - (pad V14 smd circle (at -2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 368 "Net-(U13-PadV14)")) - (pad V13 smd circle (at -1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 369 "Net-(U13-PadV13)")) - (pad V12 smd circle (at -0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 258 "/Config interface/FPGA_JTAG_TCK")) - (pad V11 smd circle (at 0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad V10 smd circle (at 1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 370 "Net-(U13-PadV10)")) - (pad V9 smd circle (at 2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 371 "Net-(U13-PadV9)")) - (pad V8 smd circle (at 3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 372 "Net-(U13-PadV8)")) - (pad V7 smd circle (at 4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 373 "Net-(U13-PadV7)")) - (pad V6 smd circle (at 5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad V5 smd circle (at 6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 77 FMC_NE1)) - (pad V4 smd circle (at 7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 64 FMC_D23)) - (pad V3 smd circle (at 8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 611 ICE40_FPGA_SCK)) - (pad V2 smd circle (at 9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 27 FMC_A13)) - (pad V1 smd circle (at 10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad U22 smd circle (at -10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 196 "Net-(R65-Pad1)")) - (pad U21 smd circle (at -9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 374 "Net-(U13-PadU21)")) - (pad U20 smd circle (at -8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 53 FMC_D12)) - (pad U19 smd circle (at -7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad U18 smd circle (at -6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 375 "Net-(U13-PadU18)")) - (pad U17 smd circle (at -5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 376 "Net-(U13-PadU17)")) - (pad U16 smd circle (at -4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 377 "Net-(U13-PadU16)")) - (pad U15 smd circle (at -3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 378 "Net-(U13-PadU15)")) - (pad U14 smd circle (at -2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad U13 smd circle (at -1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 265 "/Config interface/FPGA_JTAG_TDO")) - (pad U12 smd circle (at -0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 259 "/Config interface/FPGA_INIT_B_INT1")) - (pad U11 smd circle (at 0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 255 "/Config interface/FPGA_M0")) - (pad U10 smd circle (at 1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 254 "/Config interface/FPGA_M1")) - (pad U9 smd circle (at 2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 253 "/Config interface/FPGA_M2")) - (pad U8 smd circle (at 3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad U7 smd circle (at 4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 379 "Net-(U13-PadU7)")) - (pad U6 smd circle (at 5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 380 "Net-(U13-PadU6)")) - (pad U5 smd circle (at 6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 381 "Net-(U13-PadU5)")) - (pad U4 smd circle (at 7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad U3 smd circle (at 8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 115 FPGA_GPIO_LED_0)) - (pad U2 smd circle (at 9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 44 FMC_D3)) - (pad U1 smd circle (at 10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 43 FMC_D2)) - (pad T22 smd circle (at -10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad T21 smd circle (at -9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 382 "Net-(U13-PadT21)")) - (pad T20 smd circle (at -8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 383 "Net-(U13-PadT20)")) - (pad T19 smd circle (at -7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 264 "/MKM interface/FPGA_CFG_CS_N1")) - (pad T18 smd circle (at -6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 384 "Net-(U13-PadT18)")) - (pad T17 smd circle (at -5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad T16 smd circle (at -4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 385 "Net-(U13-PadT16)")) - (pad T15 smd circle (at -3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 386 "Net-(U13-PadT15)")) - (pad T14 smd circle (at -2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 387 "Net-(U13-PadT14)")) - (pad T13 smd circle (at -1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 257 "/Config interface/FPGA_JTAG_TMS")) - (pad T12 smd circle (at -0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad T11 smd circle (at 0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad T10 smd circle (at 1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad T9 smd circle (at 2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad T8 smd circle (at 3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad T7 smd circle (at 4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad T6 smd circle (at 5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 388 "Net-(U13-PadT6)")) - (pad T5 smd circle (at 6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 389 "Net-(U13-PadT5)")) - (pad T4 smd circle (at 7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 390 "Net-(U13-PadT4)")) - (pad T3 smd circle (at 8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 391 "Net-(U13-PadT3)")) - (pad T2 smd circle (at 9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad T1 smd circle (at 10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 116 FPGA_GPIO_LED_1)) - (pad R22 smd circle (at -10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 263 "/MKM interface/FPGA_CFG_MISO1")) - (pad R21 smd circle (at -9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 71 FMC_D30)) - (pad R20 smd circle (at -8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad R19 smd circle (at -7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 392 "Net-(U13-PadR19)")) - (pad R18 smd circle (at -6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 393 "Net-(U13-PadR18)")) - (pad R17 smd circle (at -5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 394 "Net-(U13-PadR17)")) - (pad R16 smd circle (at -4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 395 "Net-(U13-PadR16)")) - (pad R15 smd circle (at -3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad R14 smd circle (at -2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 396 "Net-(U13-PadR14)")) - (pad R13 smd circle (at -1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 256 "/Config interface/FPGA_JTAG_TDI")) - (pad R12 smd circle (at -0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad R11 smd circle (at 0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad R10 smd circle (at 1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad R9 smd circle (at 2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad R8 smd circle (at 3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad R7 smd circle (at 4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad R6 smd circle (at 5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 397 "Net-(U13-PadR6)")) - (pad R5 smd circle (at 6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad R4 smd circle (at 7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 66 FMC_D25)) - (pad R3 smd circle (at 8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 398 "Net-(U13-PadR3)")) - (pad R2 smd circle (at 9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 399 "Net-(U13-PadR2)")) - (pad R1 smd circle (at 10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 400 "Net-(U13-PadR1)")) - (pad P22 smd circle (at -10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 262 "/MKM interface/FPGA_CFG_MOSI1")) - (pad P21 smd circle (at -9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 72 FMC_D31)) - (pad P20 smd circle (at -8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 401 "Net-(U13-PadP20)")) - (pad P19 smd circle (at -7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 402 "Net-(U13-PadP19)")) - (pad P18 smd circle (at -6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad P17 smd circle (at -5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 403 "Net-(U13-PadP17)")) - (pad P16 smd circle (at -4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 404 "Net-(U13-PadP16)")) - (pad P15 smd circle (at -3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 405 "Net-(U13-PadP15)")) - (pad P14 smd circle (at -2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 406 "Net-(U13-PadP14)")) - (pad P13 smd circle (at -1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad P12 smd circle (at -0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad P11 smd circle (at 0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad P10 smd circle (at 1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad P9 smd circle (at 2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad P8 smd circle (at 3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad P7 smd circle (at 4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad P6 smd circle (at 5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 407 "Net-(U13-PadP6)")) - (pad P5 smd circle (at 6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 408 "Net-(U13-PadP5)")) - (pad P4 smd circle (at 7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 409 "Net-(U13-PadP4)")) - (pad P3 smd circle (at 8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad P2 smd circle (at 9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 410 "Net-(U13-PadP2)")) - (pad P1 smd circle (at 10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 411 "Net-(U13-PadP1)")) - (pad N22 smd circle (at -10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 412 "Net-(U13-PadN22)")) - (pad N21 smd circle (at -9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad N20 smd circle (at -8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 413 "Net-(U13-PadN20)")) - (pad N19 smd circle (at -7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 414 "Net-(U13-PadN19)")) - (pad N18 smd circle (at -6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 415 "Net-(U13-PadN18)")) - (pad N17 smd circle (at -5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 416 "Net-(U13-PadN17)")) - (pad N16 smd circle (at -4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad N15 smd circle (at -3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 52 FMC_D11)) - (pad N14 smd circle (at -2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 417 "Net-(U13-PadN14)")) - (pad N13 smd circle (at -1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 418 "Net-(U13-PadN13)")) - (pad N12 smd circle (at -0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 260 "/Config interface/FPGA_PROGRAM_B1")) - (pad N11 smd circle (at 0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad N10 smd circle (at 1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad N9 smd circle (at 2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad N8 smd circle (at 3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad N7 smd circle (at 4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad N6 smd circle (at 5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad N5 smd circle (at 6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 419 "Net-(U13-PadN5)")) - (pad N4 smd circle (at 7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 420 "Net-(U13-PadN4)")) - (pad N3 smd circle (at 8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 421 "Net-(U13-PadN3)")) - (pad N2 smd circle (at 9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 422 "Net-(U13-PadN2)")) - (pad N1 smd circle (at 10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad M22 smd circle (at -10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 423 "Net-(U13-PadM22)")) - (pad M21 smd circle (at -9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 424 "Net-(U13-PadM21)")) - (pad M20 smd circle (at -8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 425 "Net-(U13-PadM20)")) - (pad M19 smd circle (at -7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad M18 smd circle (at -6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 426 "Net-(U13-PadM18)")) - (pad M17 smd circle (at -5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 427 "Net-(U13-PadM17)")) - (pad M16 smd circle (at -4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 428 "Net-(U13-PadM16)")) - (pad M15 smd circle (at -3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 429 "Net-(U13-PadM15)")) - (pad M14 smd circle (at -2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad M13 smd circle (at -1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 430 "Net-(U13-PadM13)")) - (pad M12 smd circle (at -0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad M11 smd circle (at 0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad M10 smd circle (at 1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad M9 smd circle (at 2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 431 "Net-(U13-PadM9)")) - (pad M8 smd circle (at 3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad M7 smd circle (at 4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad M6 smd circle (at 5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 432 "Net-(U13-PadM6)")) - (pad M5 smd circle (at 6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 433 "Net-(U13-PadM5)")) - (pad M4 smd circle (at 7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad M3 smd circle (at 8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 434 "Net-(U13-PadM3)")) - (pad M2 smd circle (at 9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 435 "Net-(U13-PadM2)")) - (pad M1 smd circle (at 10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 436 "Net-(U13-PadM1)")) - (pad L22 smd circle (at -10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad L21 smd circle (at -9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 437 "Net-(U13-PadL21)")) - (pad L20 smd circle (at -8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 438 "Net-(U13-PadL20)")) - (pad L19 smd circle (at -7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 439 "Net-(U13-PadL19)")) - (pad L18 smd circle (at -6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 440 "Net-(U13-PadL18)")) - (pad L17 smd circle (at -5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad L16 smd circle (at -4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 441 "Net-(U13-PadL16)")) - (pad L15 smd circle (at -3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 442 "Net-(U13-PadL15)")) - (pad L14 smd circle (at -2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 443 "Net-(U13-PadL14)")) - (pad L13 smd circle (at -1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 444 "Net-(U13-PadL13)")) - (pad L12 smd circle (at -0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 261 "/Config interface/FPGA_CFG_SCLK1")) - (pad L11 smd circle (at 0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad L10 smd circle (at 1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 445 "Net-(U13-PadL10)")) - (pad L9 smd circle (at 2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad L8 smd circle (at 3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad L7 smd circle (at 4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad L6 smd circle (at 5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 446 "Net-(U13-PadL6)")) - (pad L5 smd circle (at 6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 447 "Net-(U13-PadL5)")) - (pad L4 smd circle (at 7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 448 "Net-(U13-PadL4)")) - (pad L3 smd circle (at 8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 449 "Net-(U13-PadL3)")) - (pad L2 smd circle (at 9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad L1 smd circle (at 10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 450 "Net-(U13-PadL1)")) - (pad K22 smd circle (at -10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 451 "Net-(U13-PadK22)")) - (pad K21 smd circle (at -9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 452 "Net-(U13-PadK21)")) - (pad K20 smd circle (at -8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad K19 smd circle (at -7.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 453 "Net-(U13-PadK19)")) - (pad K18 smd circle (at -6.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 454 "Net-(U13-PadK18)")) - (pad K17 smd circle (at -5.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 455 "Net-(U13-PadK17)")) - (pad K16 smd circle (at -4.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 456 "Net-(U13-PadK16)")) - (pad K15 smd circle (at -3.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad K14 smd circle (at -2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 457 "Net-(U13-PadK14)")) - (pad K13 smd circle (at -1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 458 "Net-(U13-PadK13)")) - (pad K12 smd circle (at -0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad K11 smd circle (at 0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad K10 smd circle (at 1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad K9 smd circle (at 2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad K8 smd circle (at 3.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad K7 smd circle (at 4.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad K6 smd circle (at 5.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 459 "Net-(U13-PadK6)")) - (pad K5 smd circle (at 6.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad K4 smd circle (at 7.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 460 "Net-(U13-PadK4)")) - (pad K3 smd circle (at 8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 461 "Net-(U13-PadK3)")) - (pad K2 smd circle (at 9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 462 "Net-(U13-PadK2)")) - (pad K1 smd circle (at 10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 463 "Net-(U13-PadK1)")) - (pad J22 smd circle (at -10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 464 "Net-(U13-PadJ22)")) - (pad J21 smd circle (at -9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 465 "Net-(U13-PadJ21)")) - (pad J20 smd circle (at -8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 466 "Net-(U13-PadJ20)")) - (pad J19 smd circle (at -7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 467 "Net-(U13-PadJ19)")) - (pad J18 smd circle (at -6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 89.2302 -11.4234 270) + (path /57D84E30/58023FC3) + (attr smd) + (fp_text reference C99 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 7.3594 -3.7338 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad J17 smd circle (at -5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 468 "Net-(U13-PadJ17)")) - (pad J16 smd circle (at -4.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 469 "Net-(U13-PadJ16)")) - (pad J15 smd circle (at -3.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 470 "Net-(U13-PadJ15)")) - (pad J14 smd circle (at -2.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 471 "Net-(U13-PadJ14)")) - (pad J13 smd circle (at -1.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad J12 smd circle (at -0.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 92.202 -20.3134 270) + (path /57D84E30/58023FC2) + (attr smd) + (fp_text reference C100 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.0066 -1.016 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad J11 smd circle (at 0.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad J10 smd circle (at 1.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 80.391 -19.1196 270) + (path /57D84E30/58023FC1) + (attr smd) + (fp_text reference C101 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0.0696 0.889 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad J9 smd circle (at 2.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad J8 smd circle (at 3.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 31.5 8.5 270) + (path /57D84FAD/58023F9A) + (attr smd) + (fp_text reference C105 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 1.02 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 1 3V3_BATT)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad J7 smd circle (at 4.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad J6 smd circle (at 5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 472 "Net-(U13-PadJ6)")) - (pad J5 smd circle (at 6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 473 "Net-(U13-PadJ5)")) - (pad J4 smd circle (at 7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 474 "Net-(U13-PadJ4)")) - (pad J3 smd circle (at 8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 31.4842 1 270) + (path /57D85134/58023F67) + (attr smd) + (fp_text reference C108 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0.016 1.0042 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad J2 smd circle (at 9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 475 "Net-(U13-PadJ2)")) - (pad J1 smd circle (at 10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 476 "Net-(U13-PadJ1)")) - (pad H22 smd circle (at -10.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 477 "Net-(U13-PadH22)")) - (pad H21 smd circle (at -9.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad H20 smd circle (at -8.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 478 "Net-(U13-PadH20)")) - (pad H19 smd circle (at -7.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 479 "Net-(U13-PadH19)")) - (pad H18 smd circle (at -6.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 480 "Net-(U13-PadH18)")) - (pad H17 smd circle (at -5.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 481 "Net-(U13-PadH17)")) - (pad H16 smd circle (at -4.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad H15 smd circle (at -3.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 482 "Net-(U13-PadH15)")) - (pad H14 smd circle (at -2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 483 "Net-(U13-PadH14)")) - (pad H13 smd circle (at -1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 484 "Net-(U13-PadH13)")) - (pad H12 smd circle (at -0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 55.9562 -67.8942) + (path /57D85217/58023F53) + (attr smd) + (fp_text reference C109 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 -0.9398) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 125 FPGA_VCCAUX_1V8)) - (pad H11 smd circle (at 0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad H10 smd circle (at 1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad H9 smd circle (at 2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad H8 smd circle (at 3.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad H7 smd circle (at 4.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad H6 smd circle (at 5.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad H5 smd circle (at 6.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 485 "Net-(U13-PadH5)")) - (pad H4 smd circle (at 7.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 486 "Net-(U13-PadH4)")) - (pad H3 smd circle (at 8.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 487 "Net-(U13-PadH3)")) - (pad H2 smd circle (at 9.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 488 "Net-(U13-PadH2)")) - (pad H1 smd circle (at 10.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad G22 smd circle (at -10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 489 "Net-(U13-PadG22)")) - (pad G21 smd circle (at -9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 490 "Net-(U13-PadG21)")) - (pad G20 smd circle (at -8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 491 "Net-(U13-PadG20)")) - (pad G19 smd circle (at -7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad G18 smd circle (at -6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 492 "Net-(U13-PadG18)")) - (pad G17 smd circle (at -5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 493 "Net-(U13-PadG17)")) - (pad G16 smd circle (at -4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 494 "Net-(U13-PadG16)")) - (pad G15 smd circle (at -3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 495 "Net-(U13-PadG15)")) - (pad G14 smd circle (at -2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad G13 smd circle (at -1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 496 "Net-(U13-PadG13)")) - (pad G12 smd circle (at -0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad G11 smd circle (at 0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 244 "/Config interface/FPGA_DONE_INT")) - (pad G10 smd circle (at 1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad G9 smd circle (at 2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad G8 smd circle (at 3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad G7 smd circle (at 4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad G6 smd circle (at 5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad G5 smd circle (at 6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad G4 smd circle (at 7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 497 "Net-(U13-PadG4)")) - (pad G3 smd circle (at 8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 498 "Net-(U13-PadG3)")) - (pad G2 smd circle (at 9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 499 "Net-(U13-PadG2)")) - (pad G1 smd circle (at 10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 500 "Net-(U13-PadG1)")) - (pad F22 smd circle (at -10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad F21 smd circle (at -9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 501 "Net-(U13-PadF21)")) - (pad F20 smd circle (at -8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 502 "Net-(U13-PadF20)")) - (pad F19 smd circle (at -7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 503 "Net-(U13-PadF19)")) - (pad F18 smd circle (at -6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 592 ICE40_GPIO_FPGA_3)) - (pad F17 smd circle (at -5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad F16 smd circle (at -4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 121 FPGA_IRQ_N_1)) - (pad F15 smd circle (at -3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 504 "Net-(U13-PadF15)")) - (pad F14 smd circle (at -2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 120 FPGA_IRQ_N_0)) - (pad F13 smd circle (at -1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 505 "Net-(U13-PadF13)")) - (pad F12 smd circle (at -0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad F11 smd circle (at 0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad F10 smd circle (at 1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 506 "Net-(U13-PadF10)")) - (pad F9 smd circle (at 2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 507 "Net-(U13-PadF9)")) - (pad F8 smd circle (at 3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 508 "Net-(U13-PadF8)")) - (pad F7 smd circle (at 4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 509 "Net-(U13-PadF7)")) - (pad F6 smd circle (at 5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 510 "Net-(U13-PadF6)")) - (pad F5 smd circle (at 6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad F4 smd circle (at 7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 511 "Net-(U13-PadF4)")) - (pad F3 smd circle (at 8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 512 "Net-(U13-PadF3)")) - (pad F2 smd circle (at 9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad F1 smd circle (at 10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 513 "Net-(U13-PadF1)")) - (pad E22 smd circle (at -10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 514 "Net-(U13-PadE22)")) - (pad E21 smd circle (at -9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 515 "Net-(U13-PadE21)")) - (pad E20 smd circle (at -8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad E19 smd circle (at -7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 590 ICE40_GPIO_FPGA_0)) - (pad E18 smd circle (at -6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 593 ICE40_GPIO_FPGA_2)) - (pad E17 smd circle (at -5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 122 FPGA_IRQ_N_2)) - (pad E16 smd circle (at -4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 516 "Net-(U13-PadE16)")) - (pad E15 smd circle (at -3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad E14 smd circle (at -2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 99 FPGA_GPIO_A_0)) - (pad E13 smd circle (at -1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 100 FPGA_GPIO_A_1)) - (pad E12 smd circle (at -0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad E11 smd circle (at 0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad E10 smd circle (at 1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 517 "Net-(U13-PadE10)")) - (pad E9 smd circle (at 2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad E8 smd circle (at 3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 518 "Net-(U13-PadE8)")) - (pad E7 smd circle (at 4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad E6 smd circle (at 5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 519 "Net-(U13-PadE6)")) - (pad E5 smd circle (at 6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad E4 smd circle (at 7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad E3 smd circle (at 8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 520 "Net-(U13-PadE3)")) - (pad E2 smd circle (at 9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 521 "Net-(U13-PadE2)")) - (pad E1 smd circle (at 10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 522 "Net-(U13-PadE1)")) - (pad D22 smd circle (at -10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 523 "Net-(U13-PadD22)")) - (pad D21 smd circle (at -9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 524 "Net-(U13-PadD21)")) - (pad D20 smd circle (at -8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 525 "Net-(U13-PadD20)")) - (pad D19 smd circle (at -7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 526 "Net-(U13-PadD19)")) - (pad D18 smd circle (at -6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad D17 smd circle (at -5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 98 FPGA_GCLK)) - (pad D16 smd circle (at -4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 527 "Net-(U13-PadD16)")) - (pad D15 smd circle (at -3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 528 "Net-(U13-PadD15)")) - (pad D14 smd circle (at -2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 110 FPGA_GPIO_B_3)) - (pad D13 smd circle (at -1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad D12 smd circle (at -0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad D11 smd circle (at 0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 529 "Net-(U13-PadD11)")) - (pad D10 smd circle (at 1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 530 "Net-(U13-PadD10)")) - (pad D9 smd circle (at 2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 531 "Net-(U13-PadD9)")) - (pad D8 smd circle (at 3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad D7 smd circle (at 4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 532 "Net-(U13-PadD7)")) - (pad D6 smd circle (at 5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 533 "Net-(U13-PadD6)")) - (pad D5 smd circle (at 6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 534 "Net-(U13-PadD5)")) - (pad D4 smd circle (at 7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad D3 smd circle (at 8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad D2 smd circle (at 9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 535 "Net-(U13-PadD2)")) - (pad D1 smd circle (at 10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 536 "Net-(U13-PadD1)")) - (pad C22 smd circle (at -10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 114 FPGA_GPIO_B_7)) - (pad C21 smd circle (at -9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 34.3522 -30.1482 270) + (path /57D85260/58023F36) + (attr smd) + (fp_text reference C110 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 1.0782 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad C20 smd circle (at -8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 113 FPGA_GPIO_B_6)) - (pad C19 smd circle (at -7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 537 "Net-(U13-PadC19)")) - (pad C18 smd circle (at -6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 111 FPGA_GPIO_B_4)) - (pad C17 smd circle (at -5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 591 ICE40_GPIO_FPGA_1)) - (pad C16 smd circle (at -4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad C15 smd circle (at -3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 108 FPGA_GPIO_B_1)) - (pad C14 smd circle (at -2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 123 FPGA_IRQ_N_3)) - (pad C13 smd circle (at -1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 103 FPGA_GPIO_A_4)) - (pad C12 smd circle (at -0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad C11 smd circle (at 0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 538 "Net-(U13-PadC11)")) - (pad C10 smd circle (at 1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad C9 smd circle (at 2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 539 "Net-(U13-PadC9)")) - (pad C8 smd circle (at 3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 540 "Net-(U13-PadC8)")) - (pad C7 smd circle (at 4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 541 "Net-(U13-PadC7)")) - (pad C6 smd circle (at 5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad C5 smd circle (at 6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 542 "Net-(U13-PadC5)")) - (pad C4 smd circle (at 7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 543 "Net-(U13-PadC4)")) - (pad C3 smd circle (at 8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad C2 smd circle (at 9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 544 "Net-(U13-PadC2)")) - (pad C1 smd circle (at 10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 66.2004 -88.4428 180) + (path /57D85260/58023F39) + (attr smd) + (fp_text reference C111 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.01uF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 2.4464 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad B22 smd circle (at -10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 545 "Net-(U13-PadB22)")) - (pad B21 smd circle (at -9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 546 "Net-(U13-PadB21)")) - (pad B20 smd circle (at -8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 612 "Net-(U13-PadB20)")) - (pad B19 smd circle (at -7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad B18 smd circle (at -6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 97 FPGA_ENTROPY_DISABLE)) - (pad B17 smd circle (at -5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 616 ICE40_GPIO_FPGA_4)) - (pad B16 smd circle (at -4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 109 FPGA_GPIO_B_2)) - (pad B15 smd circle (at -3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 106 FPGA_GPIO_A_7)) - (pad B14 smd circle (at -2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 48.55 -29.475) + (path /57D85260/58023F37) + (attr smd) + (fp_text reference C112 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 -1.005) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad B13 smd circle (at -1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 104 FPGA_GPIO_A_5)) - (pad B12 smd circle (at -0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad B11 smd circle (at 0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 547 "Net-(U13-PadB11)")) - (pad B10 smd circle (at 1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 548 "Net-(U13-PadB10)")) - (pad B9 smd circle (at 2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 549 "Net-(U13-PadB9)")) - (pad B8 smd circle (at 3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 550 "Net-(U13-PadB8)")) - (pad B7 smd circle (at 4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 551 "Net-(U13-PadB7)")) - (pad B6 smd circle (at 5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 552 "Net-(U13-PadB6)")) - (pad B5 smd circle (at 6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 553 "Net-(U13-PadB5)")) - (pad B4 smd circle (at 7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 554 "Net-(U13-PadB4)")) - (pad B3 smd circle (at 8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 32.1818 -75.8444 90) + (path /57D853B0/58023F13) + (attr smd) + (fp_text reference C115 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.047uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at -2.4384 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 159 "Net-(C115-Pad1)")) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad B2 smd circle (at 9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 555 "Net-(U13-PadB2)")) - (pad B1 smd circle (at 10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 556 "Net-(U13-PadB1)")) - (pad A22 smd circle (at -10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 13.95 -41.625 270) + (path /57D853B0/58023F12) + (attr smd) + (fp_text reference C116 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.047uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at -2.571 -0.02 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 160 "Net-(C116-Pad1)")) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad A21 smd circle (at -9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 112 FPGA_GPIO_B_5)) - (pad A20 smd circle (at -8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 613 ICE40_GPIO_FPGA_7)) - (pad A19 smd circle (at -7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 614 ICE40_GPIO_FPGA_5)) - (pad A18 smd circle (at -6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 615 ICE40_GPIO_FPGA_6)) - (pad A17 smd circle (at -5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 32.1818 -80.391 270) + (path /57D853B0/58023F10) + (attr smd) + (fp_text reference C117 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 27pF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at -2.413 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 162 "Net-(C117-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 13.975 -37.35 90) + (path /57D853B0/58023F11) + (attr smd) + (fp_text reference C118 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 27pF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at -2.552 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 164 "Net-(C118-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 71.075 -97.7 90) + (path /57D854CB/58023EF3) + (attr smd) + (fp_text reference C121 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at 0 -0.971 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad A16 smd circle (at -4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 107 FPGA_GPIO_B_0)) - (pad A15 smd circle (at -3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 105 FPGA_GPIO_A_6)) - (pad A14 smd circle (at -2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 102 FPGA_GPIO_A_3)) - (pad A13 smd circle (at -1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 101 FPGA_GPIO_A_2)) - (pad A12 smd circle (at -0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad A11 smd circle (at 0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad A10 smd circle (at 1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 557 "Net-(U13-PadA10)")) - (pad A9 smd circle (at 2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad A8 smd circle (at 3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 558 "Net-(U13-PadA8)")) - (pad A7 smd circle (at 4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad A6 smd circle (at 5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 559 "Net-(U13-PadA6)")) - (pad A5 smd circle (at 6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad A4 smd circle (at 7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 560 "Net-(U13-PadA4)")) - (pad A3 smd circle (at 8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad A2 smd circle (at 9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad A1 smd circle (at 10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) - (net 561 "Net-(U13-PadA1)")) - (model wrlshp/041B98A5-F02D.wrl + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:ASF (layer B.Cu) (tedit 60BDCC8E) (tstamp 539EEDBF) - (at 67.9704 -84.709) - (path /57D85260/58023F3D) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 42 -93.5 180) + (path /57D854CB/58023EF2) (attr smd) - (fp_text reference Q5 (at 0 0) (layer F.SilkS) hide + (fp_text reference C122 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value ASFL1-50.000MHZ-EK-T (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0.762) (layer B.Fab) - (effects (font (size 1.2 1.2) (thickness 0.15)) (justify mirror)) + (fp_text user %R (at 0.09 0.988) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -2.032 2.286) (end 2.032 2.286) (layer B.Fab) (width 0.12)) - (fp_line (start 2.032 2.286) (end 2.032 -2.286) (layer B.Fab) (width 0.12)) - (fp_line (start 2.032 -2.286) (end -2.032 -2.286) (layer B.Fab) (width 0.12)) - (fp_line (start -2.032 -2.286) (end -2.032 2.286) (layer B.Fab) (width 0.12)) - (fp_poly (pts (xy 2.032 -2.286) (xy 0.508 -2.286) (xy 0.508 -0.508) (xy 2.032 -0.508)) (layer B.Fab) (width 0.1)) - (pad 4 smd rect (at -1.0922 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 3 smd rect (at -1.0922 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) - (net 187 "Net-(Q5-Pad3)")) - (pad 1 smd rect (at 1.1302 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) - (net 186 "Net-(Q5-Pad1)")) - (pad 2 smd rect (at 1.1302 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:SOT95P280X100-5N (layer F.Cu) (tedit 60BD3E3A) (tstamp 5F036F55) - (at 71.1 -27.7) - (path /57D8509E/5F0932AD) - (fp_text reference U12 (at 1.755545 -3.587435) (layer F.SilkS) - (effects (font (size 1.642764 1.642764) (thickness 0.015))) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.9346 -69.8754 180) + (path /57D855DE/58023E90) + (attr smd) + (fp_text reference C124 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value ADP121-AUJZ25R7 (at 13.23165 3.409705) (layer F.Fab) hide - (effects (font (size 1.642937 1.642937) (thickness 0.015))) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) + (fp_text user %R (at -2.3114 -0.0254) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_text user Name (at 0.71248 -3.587855) (layer Dwgs.User) hide - (effects (font (size 1.642953 1.642953) (thickness 0.015))) - ) - (fp_arc (start 0 -1.446774) (end -0.1778 -1.2192) (angle -76) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -1.4478) (end -0.3048 -1.4478) (angle -180) (layer F.Fab) (width 0.1)) - (fp_arc (start 0 -1.4478) (end -0.3048 -1.4478) (angle -180) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.905 -1.524) (end 1.905 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 1.905 -1.524) (end 1.905 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 1.905 1.524) (end -1.905 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -1.905 1.524) (end -1.905 -1.524) (layer F.Fab) (width 0.1)) - (pad 5 smd rect (at 1.2192 -0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) - (net 572 "/Master Key Memory/MKM_VPP")) - (pad 4 smd rect (at 1.2192 0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) - (net 575 "Net-(U12-Pad4)")) - (pad 3 smd rect (at -1.2192 0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) - (pad 2 smd rect (at -1.2192 0) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at -1.2192 -0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:SOT95P280X100-5N (layer F.Cu) (tedit 60BD3E3A) (tstamp 5F036E6C) - (at 71.1 -30.9) - (path /57D8509E/5F031C66) - (fp_text reference U10 (at 1.755545 -3.587435) (layer F.SilkS) - (effects (font (size 1.642764 1.642764) (thickness 0.015))) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 57.9374 -72.898 180) + (path /57D855DE/58023EA6) + (attr smd) + (fp_text reference C125 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value ADP121-AUJZ12R7 (at 13.23165 3.409705) (layer F.Fab) hide - (effects (font (size 1.642937 1.642937) (thickness 0.015))) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer F.Fab) + (fp_text user %R (at -0.4826 6.096) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_text user Name (at 0.71248 -3.587855) (layer Dwgs.User) hide - (effects (font (size 1.642953 1.642953) (thickness 0.015))) - ) - (fp_arc (start 0 -1.446774) (end -0.1778 -1.2192) (angle -76) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -1.4478) (end -0.3048 -1.4478) (angle -180) (layer F.Fab) (width 0.1)) - (fp_arc (start 0 -1.4478) (end -0.3048 -1.4478) (angle -180) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.905 -1.524) (end 1.905 -1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 1.905 -1.524) (end 1.905 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start 1.905 1.524) (end -1.905 1.524) (layer F.Fab) (width 0.1)) - (fp_line (start -1.905 1.524) (end -1.905 -1.524) (layer F.Fab) (width 0.1)) - (pad 5 smd rect (at 1.2192 -0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) - (net 571 "/Master Key Memory/MKM_VCC")) - (pad 4 smd rect (at 1.2192 0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) - (net 574 "Net-(U10-Pad4)")) - (pad 3 smd rect (at -1.2192 0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) - (pad 2 smd rect (at -1.2192 0) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at -1.2192 -0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) ) - (module Cryptech_Alpha_Footprints:694106301002 (layer F.Cu) (tedit 60BDC87E) (tstamp 539EEDBF) - (at 20 18.4) - (path /57D84708/580240B4) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.9346 -70.9168) + (path /57D855DE/58023E8C) (attr smd) - (fp_text reference JP1 (at 0 0) (layer F.SilkS) hide + (fp_text reference C128 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 694106301002 (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 -6.7 90) (layer F.Fab) - (effects (font (size 5 5) (thickness 0.5))) + (fp_text user %R (at 2.3114 0.0508) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -4.8 -13.6) (end 4.8 -13.6) (layer F.Fab) (width 0.12)) - (fp_line (start 4.8 -13.6) (end 4.8 0) (layer F.Fab) (width 0.12)) - (fp_line (start 4.8 0) (end -4.8 0) (layer F.Fab) (width 0.12)) - (fp_line (start -4.8 0) (end -4.8 -13.6) (layer F.Fab) (width 0.12)) - (pad 3 thru_hole oval (at 4.8 -10.6 90) (size 4.5 2) (drill oval 3 0.8) (layers *.Cu *.Paste *.Mask) - (net 3 GND)) - (pad 2 thru_hole oval (at 0 -7.8 90) (size 2 4.5) (drill oval 0.8 3) (layers *.Cu *.Paste *.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 thru_hole oval (at 0 -13.6 90) (size 2 4.5) (drill oval 0.8 3) (layers *.Cu *.Paste *.Mask) - (net 202 PWR_18V)) - (model wrlshp/PJ-002A.wrl - (offset (xyz 0.0551179991722107 -0.01193799982070923 6.499999602379799)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 90 180 270)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/51D2E761-0F4D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 5F035EDF) - (at 86.2 -27.5 270) - (path /57D8509E/5F05B071) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.96 -63.8556) + (path /57D855DE/58023E89) (attr smd) - (fp_text reference C107 (at 1.846 -1.43 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) + (fp_text reference C129 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 10uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 2.286 0.1016) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 573 "/Master Key Memory/MKM_VCC_PLL")) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 72.5 -86.5 180) - (path /57D84708/580240BA) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 57.9374 -71.9074) + (path /57D855DE/58023E8B) (attr smd) - (fp_text reference C7 (at 0 0) (layer F.SilkS) hide + (fp_text reference C130 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at 0.4826 -5.8166) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 202 PWR_18V)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 76.25 -87.75 270) - (path /57D84708/580240B9) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 57.9628 -66.9036) + (path /57D855DE/58023E88) (attr smd) - (fp_text reference C13 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C131 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -1.5748 4.4196) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 2 15V_STABLE)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer B.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 29.718 -26.5684 270) - (path /57D849FD/5802406E) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 57.4548 -70.4088 90) + (path /57D855DE/58023E8A) (attr smd) - (fp_text reference C26 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C134 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 10uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 5.0292 0.2032 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer B.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end -1.651 -0.762) (layer B.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end 1.651 -0.762) (layer B.Fab) (width 0.1)) - (fp_line (start -1.651 0.762) (end 1.651 0.762) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer B.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 45.6946 -51.3334 180) - (path /57D849FD/58024063) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.96 -67.8942) + (path /57D855DE/58023EB0) (attr smd) - (fp_text reference C27 (at 0 0) (layer F.SilkS) hide + (fp_text reference C135 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 10uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at -0.254 -0.9398) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer B.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end -1.651 -0.762) (layer B.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end 1.651 -0.762) (layer B.Fab) (width 0.1)) - (fp_line (start -1.651 0.762) (end 1.651 0.762) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer B.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 19.77586 -5.96143) - (path /57D84CB3/58023FE6) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 61.9506 -66.8782) + (path /57D855DE/58023EAF) (attr smd) - (fp_text reference C72 (at 0 0) (layer F.SilkS) hide + (fp_text reference C138 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 2.3114 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer B.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end -1.651 -0.762) (layer B.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end 1.651 -0.762) (layer B.Fab) (width 0.1)) - (fp_line (start -1.651 0.762) (end 1.651 0.762) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask) - (net 144 FT_VREGIN)) - (pad 2 smd rect (at 1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 25.8074 -9.89 270) - (path /57D84CB3/58023FFC) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.9346 -65.8876) + (path /57D855DE/58023EAE) (attr smd) - (fp_text reference C77 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C142 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 10uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 2.3114 0.1016) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 142 FT_VPHY)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 24.2072 -15.8844 90) - (path /57D84CB3/58023FFA) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 55.4736 -71.3994 90) + (path /57D855DE/58023EA7) (attr smd) - (fp_text reference C80 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C143 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 10uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at -0.0254 -0.8636 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 143 FT_VPLL)) - (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 7.7734 -15.0716 90) - (path /57D84CB3/58023FFF) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 58.9788 -65.8876) + (path /57D855DE/58023EAD) (attr smd) - (fp_text reference C82 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C146 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -1.8288 4.9276) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer B.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 78.40381 -17.07095 90) - (path /57D84E30/58023FB0) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 55.4736 -73.406 90) + (path /57D855DE/58023EA5) (attr smd) - (fp_text reference C87 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C147 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + (fp_text user %R (at 0 0.9144 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer B.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end -1.651 -0.762) (layer B.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end 1.651 -0.762) (layer B.Fab) (width 0.1)) - (fp_line (start -1.651 0.762) (end 1.651 0.762) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask) - (net 137 FT_MGMT_VREGIN)) - (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 86.419 -7.0668 270) - (path /57D84E30/58023FC6) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 58.9534 -64.8462 180) + (path /57D855DE/58023EAC) (attr smd) - (fp_text reference C92 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C150 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 10uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 1.8034 -5.4102) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 135 FT_MGMT_VPHY)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 91.186 -7.207 270) - (path /57D84E30/58023FC4) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 58.9534 -70.8914) + (path /57D855DE/58023EA4) (attr smd) - (fp_text reference C95 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C151 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 10uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 0.7366 -4.8006) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 136 FT_MGMT_VPLL)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 90 -25 180) - (path /57D84E30/58023FC9) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.9346 -64.8462 180) + (path /57D855DE/58023EAB) (attr smd) - (fp_text reference C97 (at 0 0) (layer F.SilkS) hide + (fp_text reference C154 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at -2.3114 -0.0762) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 52.07 -83.0072) - (path /57D855DE/58023E94) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 57.4548 -65.3796 90) + (path /57D855DE/58023EA3) (attr smd) - (fp_text reference C132 (at 0 0) (layer F.SilkS) hide + (fp_text reference C155 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at -5.1816 -2.3368 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 125 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 43.9928 -71.6788 270) - (path /57D855DE/58023E93) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 57.9374 -63.881 180) + (path /57D855DE/58023EAA) (attr smd) - (fp_text reference C136 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C158 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 1.5494 -5.969) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 52.07 -85.725) - (path /57D855DE/58023E92) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 55.4228 -65.3796 270) + (path /57D855DE/58023EA2) (attr smd) - (fp_text reference C139 (at 0 0) (layer F.SilkS) hide + (fp_text reference C159 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at -0.1524 1.0668 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 125 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 61.849 -81.5594) - (path /57D855DE/58023EB1) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.9346 -71.9074 180) + (path /57D855DE/58023EA9) (attr smd) - (fp_text reference C140 (at 0 0) (layer F.SilkS) hide + (fp_text reference C162 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at -2.3114 -0.0254) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 60.1218 -55.118 270) - (path /57D855DE/58023E9A) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 59.436 -72.39 90) + (path /57D855DE/58023EA8) (attr smd) - (fp_text reference C141 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C163 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 5.588 1.27 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 71.6788 -71.0184 90) - (path /57D855DE/58023EA0) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.96 -72.898) + (path /57D855DE/58023EA1) (attr smd) - (fp_text reference C144 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C164 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 2.286 0) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 43.9166 -67.1068 270) - (path /57D855DE/58023E99) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 48.4378 -62.3824 270) + (path /57D8583B/58023E5E) (attr smd) - (fp_text reference C145 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C181 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 0 0.9398 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 41.4274 -67.1068 270) - (path /57D855DE/58023E9F) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 47.9552 -59.8678) + (path /57D8583B/58023E3B) (attr smd) - (fp_text reference C148 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C182 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 2.3368 0) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 69.2658 -70.9676 90) - (path /57D855DE/58023E98) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 53.467 -79.4258 90) + (path /57D8583B/58023E37) (attr smd) - (fp_text reference C149 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C183 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 0 1.143 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 57.3024 -84.0232 180) - (path /57D855DE/58023E9E) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 61.9506 -61.9244 180) + (path /57D8583B/58023E5A) (attr smd) - (fp_text reference C152 (at 0 0) (layer F.SilkS) hide + (fp_text reference C184 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at -2.3114 0.0516) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 70.485 -66.6496 270) - (path /57D855DE/58023E97) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 49.9364 -69.8754 180) + (path /57D8583B/58023E56) (attr smd) - (fp_text reference C153 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C185 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at -0.1016 0.9906) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 56.7436 -53.7972 180) - (path /57D855DE/58023E9D) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 55.4736 -75.4126 90) + (path /57D8583B/58023E51) (attr smd) - (fp_text reference C156 (at 0 0) (layer F.SilkS) hide + (fp_text reference C186 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at 0.0254 -0.8636 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 57.3024 -81.5594 180) - (path /57D855DE/58023E96) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 44.6786 -63.3984 270) + (path /57D8583B/58023E53) (attr smd) - (fp_text reference C157 (at 0 0) (layer F.SilkS) hide + (fp_text reference C187 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at -0.3556 -1.0414 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 41.402 -71.6788 90) - (path /57D855DE/58023E9C) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 53.0098 -56.9976 180) + (path /57D8583B/58023E3A) (attr smd) - (fp_text reference C160 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C188 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at -0.0762 0.9144) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 56.769 -56.1848 180) - (path /57D855DE/58023E95) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 52.451 -75.3872 270) + (path /57D8583B/58023E5D) (attr smd) - (fp_text reference C161 (at 0 0) (layer F.SilkS) hide + (fp_text reference C189 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at -0.0508 1.143 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 63.246 -54.74298 270) - (path /57D8583B/58023E4D) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 67.818 -64.7446) + (path /57D8583B/58023E59) (attr smd) - (fp_text reference C169 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C190 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 0 0.9906) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 42.7736 -82.0674 180) - (path /57D8583B/58023E4A) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 52.959 -67.9196 180) + (path /57D8583B/58023E55) (attr smd) - (fp_text reference C170 (at 0 0) (layer F.SilkS) hide + (fp_text reference C191 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at 0.127 0.9144) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 42.8244 -79.2734 180) - (path /57D8583B/58023E49) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 46.4312 -78.4098 90) + (path /57D8583B/58023E50) (attr smd) - (fp_text reference C171 (at 0 0) (layer F.SilkS) hide + (fp_text reference C192 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at 0 -0.9652 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 40.1574 -63.0428 270) - (path /57D8583B/58023E45) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 49.4538 -66.3956 90) + (path /57D8583B/58023E48) (attr smd) - (fp_text reference C172 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C193 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at -0.1016 1.0922 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 42.5958 -63.0428 270) - (path /57D8583B/58023E44) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 49.9364 -58.9026 180) + (path /57D8583B/58023E39) (attr smd) - (fp_text reference C173 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C194 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at -2.3876 0.0254) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 52.2986 -54.9148 180) - (path /57D8583B/58023E41) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 48.9458 -76.9112 180) + (path /57D8583B/58023E5C) (attr smd) - (fp_text reference C174 (at 0 0) (layer F.SilkS) hide + (fp_text reference C195 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at 0 1.0668) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 69.2658 -78.9432 90) - (path /57D8583B/58023E4C) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 60.452 -62.4078 270) + (path /57D8583B/58023E58) (attr smd) - (fp_text reference C175 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C196 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 2.4638 0 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 65.4558 -55.118 270) - (path /57D8583B/58023E4B) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 47.9552 -67.8942) + (path /57D8583B/58023E54) (attr smd) - (fp_text reference C176 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C197 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 0 -0.9398) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 66.1162 -81.5594) - (path /57D8583B/58023E47) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 50.927 -80.7974) + (path /57D8583B/58023E4F) (attr smd) - (fp_text reference C177 (at 0 0) (layer F.SilkS) hide + (fp_text reference C198 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at 0 1.0414) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 42.6212 -75.9206 90) - (path /57D8583B/58023E46) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 63.9318 -67.8942 180) + (path /57D8583B/58023E3D) (attr smd) - (fp_text reference C178 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C199 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at -0.0762 0.9398) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 69.2658 -74.8284 270) - (path /57D8583B/58023E43) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 50.9524 -61.8998 180) + (path /57D8583B/58023E38) (attr smd) - (fp_text reference C179 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C200 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) + (fp_text user %R (at 0 1.0922) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) - (at 47.4472 -56.0832) - (path /57D8583B/58023E42) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 51.4604 -72.39 270) + (path /57D8583B/58023E5B) (attr smd) - (fp_text reference C180 (at 0 0) (layer F.SilkS) hide + (fp_text reference C201 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 4.7uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) + (fp_text user %R (at 0 -1.1176 90) (layer F.Fab) (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) - (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" - (offset (xyz 0 -0.02489199962615967 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/68E8DA21-73BF.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BDC44F) (tstamp 5F035ED9) - (at 72.3 -28.2 180) - (path /57D8509E/5F090460) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 67.4624 -67.3862 90) + (path /57D8583B/58023E57) (attr smd) - (fp_text reference C106 (at -1.36 -0.006 90) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text reference C202 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 1uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer B.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05)) (justify mirror)) + (fp_text user %R (at -0.0762 1.1176 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) - (net 572 "/Master Key Memory/MKM_VPP")) - (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" - (at (xyz 0 0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/175C1D2E-5B2D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BDC44F) (tstamp 5F035EC9) - (at 72.3 -31.1 180) - (path /57D8509E/5F043BA5) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 45.9486 -66.8782 180) + (path /57D8583B/58023E52) (attr smd) - (fp_text reference C104 (at -1.36 1.158 90) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text reference C203 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 1uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer B.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05)) (justify mirror)) + (fp_text user %R (at -0.2794 -1.0922) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) - (net 571 "/Master Key Memory/MKM_VCC")) - (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" - (at (xyz 0 0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/175C1D2E-5B2D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BDC44F) (tstamp 5F035EC3) - (at 69.9 -28.2 180) - (path /57D8509E/5F09046A) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 44.59546 -75.27194 90) + (path /57D8583B/58023E4E) (attr smd) - (fp_text reference C103 (at 1.32 0.248 270) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text reference C204 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 1uF (at 0 0) (layer Cmts.User) + (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer B.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05)) (justify mirror)) + (fp_text user %R (at 0 1.12454 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) - (net 1 3V3_BATT)) - (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" - (at (xyz 0 0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/175C1D2E-5B2D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BDC44F) (tstamp 5F035EBD) - (at 69.9 -31.3 180) - (path /57D8509E/5F043CFB) + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 24.4856 -62.8904 180) + (path /57D85A75/58023E28) (attr smd) - (fp_text reference C102 (at 1.32 0.958 270) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text reference C207 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value 1uF (at 0 0) (layer Cmts.User) + (fp_text value 0.047uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 270) (layer B.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05)) (justify mirror)) + (fp_text user %R (at 3.9116 2.3876) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 165 "Net-(C207-Pad1)")) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) - (net 1 3V3_BATT)) - (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 26.924 -62.8904 180) + (path /57D85A75/58023E23) + (attr smd) + (fp_text reference C208 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value 27pF (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text user %R (at -3.302 4.6736) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 167 "Net-(C208-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/175C1D2E-5B2D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BDC44F) (tstamp 539EEDBF) - (at 47.7266 -14.2494 270) - (path /57D849FD/58024060) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 24.003 -63.0936 90) + (path /57D85B19/58023E13) (attr smd) - (fp_text reference C21 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C211 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05)) (justify mirror)) + (fp_text user %R (at 0 1.143 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -0.7) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 204 PWR_ENA_VCCINT)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 1 smd rect (at 0 0.7) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" - (at (xyz 0 0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/175C1D2E-5B2D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BDC44F) (tstamp 539EEDBF) - (at 55.0672 -51.5112 90) - (path /57D849FD/5802405E) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 14.8336 -47.2694 90) + (path /57D85B19/58023E12) (attr smd) - (fp_text reference C22 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C212 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 2.2uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05)) (justify mirror)) + (fp_text user %R (at -0.0254 1.1684 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -0.7 180) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) - (net 215 "/STM32 power/VCAP1")) - (pad 1 smd rect (at 0 0.7 180) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 205 PWR_ENA_VCCO)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" - (at (xyz 0 0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/175C1D2E-5B2D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BDC44F) (tstamp 539EEDBF) - (at 55.0672 -49.6824 90) - (path /57D849FD/5802405D) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 30.9118 -76.327 90) + (path /57D85B19/58023E11) (attr smd) - (fp_text reference C23 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C213 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 2.2uF (at 0 0 90) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 180) (layer B.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05)) (justify mirror)) + (fp_text user %R (at 0 -0.9398 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -0.7 180) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) - (net 215 "/STM32 power/VCAP1")) - (pad 1 smd rect (at 0 0.7 180) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 203 PWR_ENA_VCCAUX)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" - (at (xyz 0 0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/175C1D2E-5B2D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BDC44F) (tstamp 539EEDBF) - (at 65.9638 -24.384) - (path /57D849FD/5802405F) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 36 -14.5 90) + (path /57D84CB3/58023FEE) (attr smd) - (fp_text reference C24 (at 0 0) (layer F.SilkS) hide + (fp_text reference C214 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 2.2uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 -90) (layer B.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05)) (justify mirror)) + (fp_text user %R (at 0 -0.948 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -0.7 90) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) - (net 216 "/STM32 power/VCAP2")) - (pad 1 smd rect (at 0 0.7 90) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 144 FT_VREGIN)) + (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" - (at (xyz 0 0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/175C1D2E-5B2D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BDC44F) (tstamp 539EEDBF) - (at 67.7926 -24.384) - (path /57D849FD/5802405C) + (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BE4060) (tstamp 539EEDBF) + (at 72.9 -16.7) + (path /57D84E30/58023FB8) (attr smd) - (fp_text reference C25 (at 0 0) (layer F.SilkS) hide + (fp_text reference C215 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 2.2uF (at 0 0) (layer Cmts.User) + (fp_text value 0.1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 -90) (layer B.Fab) - (effects (font (size 0.5 0.5) (thickness 0.05)) (justify mirror)) + (fp_text user %R (at -0.002 -1.08) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) - (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) - (pad 2 smd rect (at 0 -0.7 90) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) - (net 216 "/STM32 power/VCAP2")) - (pad 1 smd rect (at 0 0.7 90) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 137 FT_MGMT_VREGIN)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" - (at (xyz 0 0 0)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 90)) + (rotate (xyz 270 360 0)) ) - (model wrlshp/175C1D2E-5B2D.wrl + (model wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 180)) + (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 5F27F142) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 5F27F142) (at 97.8 -23.2 90) (path /57D8509E/5F17FA51) (attr smd) - (fp_text reference R48 (at 0 1.26 90) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text reference R48 (at 0 0 90) (layer B.SilkS) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 4.7k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -0.086 1.006 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 1 3V3_BATT)) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8440,23 +6991,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 5F27F0BA) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 5F27F0BA) (at 97.8 -25.2 270) (path /57D8509E/5F1B0182) (attr smd) - (fp_text reference R34 (at -0.962 -1.26 90) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text reference R34 (at 0 0 90) (layer B.SilkS) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 10k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -0.2 -1.006 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 585 ICE40_CRESET)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8473,23 +7024,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 5F27F0B4) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 5F27F0B4) (at 97.8 -17.4 270) (path /57D8509E/5F1532CF) (attr smd) - (fp_text reference R33 (at 0.128 -1.26 90) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text reference R33 (at 0 0 90) (layer B.SilkS) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 4.7k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.906 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 582 "/Master Key Memory/ICE40_SPI_SCK")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8506,23 +7057,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 5F0366A7) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 5F0366A7) (at 85.7 -30.3 180) (path /57D8509E/5F057AAC) (attr smd) - (fp_text reference R24 (at -0.152 -1.344) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) + (fp_text reference R24 (at 0 0) (layer B.SilkS) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 100 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 0.942) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 571 "/Master Key Memory/MKM_VCC")) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8539,7 +7090,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 27.5 -81.4 270) (path /57D84708/580240AE) (attr smd) @@ -8549,13 +7100,13 @@ (fp_text value 56k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0.12 -0.948 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 188 "Net-(R1-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -8572,7 +7123,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 27.5 -79.2 270) (path /57D84708/580240AF) (attr smd) @@ -8582,13 +7133,13 @@ (fp_text value 4.64k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0.206 -0.948 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -8605,7 +7156,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 25.7048 -80.8308) (path /57D84708/580240B0) (attr smd) @@ -8615,13 +7166,13 @@ (fp_text value 100 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -0.0508 1.0748) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 188 "Net-(R1-Pad1)")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -8638,23 +7189,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 64.4906 -82.931 270) (path /57D85260/58023F41) (attr smd) (fp_text reference R4 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 0 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 0.9906 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 98 FPGA_GCLK)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8671,7 +7222,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 71.75 -99.5 180) (path /57D84708/580240BC) (attr smd) @@ -8681,13 +7232,13 @@ (fp_text value 1k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -1.656 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 97 FPGA_ENTROPY_DISABLE)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -8704,7 +7255,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 71.75 -98.25) (path /57D84708/580240BD) (attr smd) @@ -8714,13 +7265,13 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.656 -0.048) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 185 "Net-(Q1-Pad1)")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -8737,23 +7288,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 71 -89.5 270) (path /57D84708/580240B1) (attr smd) (fp_text reference R7 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 10k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -1.686 0.134 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 202 PWR_18V)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8770,23 +7321,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 25.5778 -73.1774) (path /57D84708/580240AC) (attr smd) (fp_text reference R8 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 6.3k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0.3302 -0.9906) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 190 "Net-(R8-Pad1)")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8803,23 +7354,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 28.194 -72.6186 270) (path /57D84708/580240AB) (attr smd) (fp_text reference R9 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 1.21k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -0.0254 -1.016 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8836,23 +7387,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 87.0966 -93.2434 270) (path /57D8488D/5802409A) (attr smd) (fp_text reference R10 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 470 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 0.9906 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 212 "/Entropy source/RAW_NOISE")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8869,23 +7420,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 90.9828 -84.6328) (path /57D8488D/58024099) (attr smd) (fp_text reference R11 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 1k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -0.0508 -0.9652) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 2 15V_STABLE)) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8902,23 +7453,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 84.6582 -86.106) (path /57D8488D/58024097) (attr smd) (fp_text reference R12 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -2.1082 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 4 "Net-(C15-Pad2)")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8935,23 +7486,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 80.6958 -81.8896 90) (path /57D8488D/58024096) (attr smd) (fp_text reference R13 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 1k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.9304 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 225 "/Entropy source/AMPLIFIED")) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -8968,23 +7519,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 31.9278 -34.671 90) (path /57D84936/5802407D) (attr smd) (fp_text reference R14 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 0 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.905 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 247 "/STM32 configuration/OSC_IN")) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -9001,7 +7552,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 40.9702 -20.0406 180) (path /57D84936/5802407F) (attr smd) @@ -9011,17 +7562,17 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) + (fp_text user %R (at -0.1778 1.0414) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 248 "/STM32 configuration/BOOT0")) + (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -9034,23 +7585,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 45 -7.5 270) (path /57D84936/58024082) (attr smd) (fp_text reference R16 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.912 0.042 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 173 "Net-(LED4-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -9067,7 +7618,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 27.4402 -50.393 180) (path /57D84C13/58024028) (attr smd) @@ -9077,13 +7628,13 @@ (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0.0082 0.915) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9100,7 +7651,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 27.425 -52.9 180) (path /57D84C13/5802402A) (attr smd) @@ -9110,17 +7661,17 @@ (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) + (fp_text user %R (at -0.007 0.948) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 145 KSM_PROM_CS_N)) + (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -9133,7 +7684,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 31.3086 -41.629) (path /57D84C55/5802401B) (attr smd) @@ -9143,13 +7694,13 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0 0.989) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9166,7 +7717,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 30.6832 -42.799) (path /57D84C55/5802401C) (attr smd) @@ -9176,17 +7727,17 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) + (fp_text user %R (at 0.5588 -2.921) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 207 RTC_SCL)) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -9199,7 +7750,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 30.6832 -44.0944) (path /57D84C55/5802401D) (attr smd) @@ -9209,17 +7760,17 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) + (fp_text user %R (at 0.5588 -2.6416) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 206 RTC_MFP)) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -9232,7 +7783,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 20.2956 -9.1534 180) (path /57D84CB3/58023FE9) (attr smd) @@ -9242,17 +7793,17 @@ (fp_text value 12k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 249 "/User USB UART/FT_REF")) + (fp_text user %R (at -2.5644 -0.5174) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) + (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 249 "/User USB UART/FT_REF")) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -9265,7 +7816,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 7.621 -7.3754 90) (path /57D84CB3/58023FF5) (attr smd) @@ -9275,13 +7826,13 @@ (fp_text value 10k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 2.0226 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 250 "/User USB UART/FT_RESET")) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9298,7 +7849,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 88.525 -9.4 180) (path /57D84E30/58023FB3) (attr smd) @@ -9308,13 +7859,13 @@ (fp_text value 12k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0.133 -1.018) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 251 "/MGMT USB UART/FT_REF1")) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9331,7 +7882,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 84.1756 -24.384) (path /57D84E30/58023FBF) (attr smd) @@ -9341,13 +7892,13 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.9304 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 252 "/MGMT USB UART/FT_RESET1")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9364,23 +7915,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 28 -7.5 270) (path /57D84FAD/58023F96) (attr smd) (fp_text reference R31 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.912 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 177 "Net-(LED12-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -9397,7 +7948,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 36.2204 -22.8854 90) (path /57D849FD/5802405B) (attr smd) @@ -9407,17 +7958,17 @@ (fp_text value 0 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) + (fp_text user %R (at 0.2286 -0.9144 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 191 "Net-(R32-Pad2)")) + (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -9430,7 +7981,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 79 -7.375 270) (path /57D85134/58023F58) (attr smd) @@ -9440,17 +7991,17 @@ (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 178 "Net-(LED13-Pad1)")) + (fp_text user %R (at 2.041 0.006 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) + (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 178 "Net-(LED13-Pad1)")) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -9463,7 +8014,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 39.25 -71.575 180) (path /57D85134/58023F69) (attr smd) @@ -9473,13 +8024,13 @@ (fp_text value 100 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.912 0.053) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 96 FPGA_DONE)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9496,7 +8047,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 84.209 -71.7296) (path /57D85134/58023F5C) (attr smd) @@ -9506,13 +8057,13 @@ (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.897 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 246 "/Config interface/FPGA_INIT_B_INT")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9529,7 +8080,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 35.2 -67.65) (path /57D85134/58023F5D) (attr smd) @@ -9539,13 +8090,13 @@ (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -1.926 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 124 FPGA_PROGRAM_B)) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9562,7 +8113,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 92.9132 -72.1106) (path /57D85134/58023F5A) (attr smd) @@ -9572,13 +8123,13 @@ (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0.3048 -1.0414) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9595,7 +8146,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 94.3356 -68.4022) (path /57D85134/58023F66) (attr smd) @@ -9605,13 +8156,13 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.9304 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 256 "/Config interface/FPGA_JTAG_TDI")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9628,7 +8179,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 94.3102 -65.8622) (path /57D85134/58023F65) (attr smd) @@ -9638,17 +8189,17 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 257 "/Config interface/FPGA_JTAG_TMS")) + (fp_text user %R (at 1.9558 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 257 "/Config interface/FPGA_JTAG_TMS")) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -9661,7 +8212,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 94.3102 -63.3476) (path /57D85134/58023F64) (attr smd) @@ -9671,13 +8222,13 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.9558 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 258 "/Config interface/FPGA_JTAG_TCK")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9694,7 +8245,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 12.9 -32.825 90) (path /57D85260/58023F35) (attr smd) @@ -9704,13 +8255,13 @@ (fp_text value 4.7k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0.195 -0.962 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 231 "/Config memory/SPI_A_TRISTATE")) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9727,7 +8278,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 12.875 -28.55 90) (path /57D85260/58023F34) (attr smd) @@ -9737,13 +8288,13 @@ (fp_text value 4.7k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0.152 -0.937 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 227 "/Config memory/SPI_B_TRISTATE")) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9760,23 +8311,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 68.58 -88.4428) (path /57D85260/58023F38) (attr smd) (fp_text reference R49 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 0 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 -0.9652) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 186 "Net-(Q5-Pad1)")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -9793,7 +8344,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 13 -24.2 270) (path /57D85260/58023F3A) (attr smd) @@ -9803,13 +8354,13 @@ (fp_text value 4.7k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -0.184 1.062 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9826,7 +8377,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 42.525 -29.475) (path /57D85260/58023F3B) (attr smd) @@ -9836,13 +8387,13 @@ (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0.147 -1.005) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 226 "/Config memory/FPGA_PROM_CS_N")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -9859,23 +8410,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 35.2298 -71.8058 180) (path /57D853B0/58023F0A) (attr smd) (fp_text reference R52 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 -1.1938) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 192 "Net-(R52-Pad1)")) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -9892,23 +8443,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 30.8102 -75.8444 90) (path /57D853B0/58023F0E) (attr smd) (fp_text reference R53 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 62k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -1.9304 -0.0762 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -9925,23 +8476,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 11.0918 -45.72) (path /57D853B0/58023F18) (attr smd) (fp_text reference R54 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 -1.016) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 194 "Net-(R54-Pad1)")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -9958,23 +8509,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 15.5194 -41.7322 270) (path /57D853B0/58023F04) (attr smd) (fp_text reference R55 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 62k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -2.2098 0.0254 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -9991,23 +8542,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 30.8102 -80.391 270) (path /57D853B0/58023F09) (attr smd) (fp_text reference R56 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 205k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -2.159 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 162 "Net-(C117-Pad2)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10024,23 +8575,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 31.5468 -78.105 270) (path /57D853B0/58023F08) (attr smd) (fp_text reference R57 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 147k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 1.0668 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10057,23 +8608,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 15.367 -37.338 90) (path /57D853B0/58023F17) (attr smd) (fp_text reference R58 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 205k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -2.032 0.127 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 164 "Net-(C118-Pad2)")) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10090,23 +8641,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 14.732 -39.5478 90) (path /57D853B0/58023F16) (attr smd) (fp_text reference R59 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 59k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 1.016 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10123,23 +8674,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 36.6 -81.475 180) (path /57D853B0/58023F07) (attr smd) (fp_text reference R60 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 470 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 1.075) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10156,23 +8707,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 9.525 -35.8648) (path /57D853B0/58023F15) (attr smd) (fp_text reference R61 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 470 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 1.0668) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10189,7 +8740,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 84.209 -73.1266) (path /57D85134/58023F63) (attr smd) @@ -10199,13 +8750,13 @@ (fp_text value 0 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.897 -0.0254) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 246 "/Config interface/FPGA_INIT_B_INT")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10222,7 +8773,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 37.225 -67.65 180) (path /57D85134/58023F62) (attr smd) @@ -10232,13 +8783,13 @@ (fp_text value 0 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -1.891 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 124 FPGA_PROGRAM_B)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10255,23 +8806,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 81 -7 270) (path /57D854CB/58023EF6) (attr smd) (fp_text reference R64 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.92 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 180 "Net-(LED15-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10288,7 +8839,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 44.7 -61.35 90) (path /57D8556F/58023EEB) (attr smd) @@ -10298,13 +8849,13 @@ (fp_text value 1k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -0.39 1.02 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 196 "Net-(R65-Pad1)")) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10321,23 +8872,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 22.0726 -62.8904 180) (path /57D85A75/58023E2C) (attr smd) (fp_text reference R66 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 2.0066 0.1016) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 197 "Net-(R66-Pad1)")) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10354,23 +8905,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 29.3116 -62.8904 180) (path /57D85A75/58023E20) (attr smd) (fp_text reference R67 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 0 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -2.1844 0.1016) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 198 "Net-(R67-Pad1)")) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10387,23 +8938,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 26.924 -64.5668 180) (path /57D85A75/58023E25) (attr smd) (fp_text reference R68 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 150k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0.254 0.9652) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 167 "Net-(C208-Pad2)")) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10420,23 +8971,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 24.4856 -64.5668 180) (path /57D85A75/58023E24) (attr smd) (fp_text reference R69 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 226k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0.3556 0.9652) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10453,23 +9004,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 30.3022 -64.5668) (path /57D85A75/58023E21) (attr smd) (fp_text reference R70 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 100 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -0.0762 -0.9652) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -10486,7 +9037,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 37.275 -69.025 180) (path /57D85134/58023F61) (attr smd) @@ -10496,13 +9047,13 @@ (fp_text value 0 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.969 0.063) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 95 FPGA_CFG_SCLK)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10519,7 +9070,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 17.78 -63.0936 90) (path /57D85B19/58023E17) (attr smd) @@ -10529,13 +9080,13 @@ (fp_text value 100k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0 -1.016 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 209 VCC_5V0)) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10552,7 +9103,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 10.9982 -50.165 180) (path /57D85B19/58023E0C) (attr smd) @@ -10562,13 +9113,13 @@ (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0 0.889) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 199 POK_VCCAUX)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10585,7 +9136,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 11.5 -44.7 180) (path /57D85B19/58023E0B) (attr smd) @@ -10595,13 +9146,13 @@ (fp_text value 100k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -0.184 -1.012) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 199 POK_VCCAUX)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10618,7 +9169,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 12.9712 -42.1566 90) (path /57D85B19/58023E09) (attr smd) @@ -10628,13 +9179,13 @@ (fp_text value 4.7k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -2.0246 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 201 POK_VCCO)) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10651,7 +9202,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 83.4 -4.8) (path /57D85B19/58023E14) (attr smd) @@ -10661,17 +9212,17 @@ (fp_text value 330 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 209 VCC_5V0)) + (fp_text user %R (at -0.088 0.99) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 183 "Net-(LED18-Pad1)")) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 209 VCC_5V0)) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -10684,27 +9235,27 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 76.8 -26.8) (path /57D84FAD/58023F99) (attr smd) (fp_text reference R82 (at 0 0) (layer B.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + (effects (font (size 1.524 1.524) (thickness 0.05))) ) (fp_text value 15k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 604 ICE40_PANIC)) + (fp_text user %R (at 1.94 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) + ) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 1 3V3_BATT)) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 604 ICE40_PANIC)) (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) @@ -10717,7 +9268,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 37.15 -66 180) (path /57D8556F/58023EEA) (attr smd) @@ -10727,13 +9278,13 @@ (fp_text value 0 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 2.098 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 94 FPGA_CFG_MOSI)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10750,7 +9301,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 37.15 -64.56067 180) (path /57D8556F/58023EE9) (attr smd) @@ -10760,13 +9311,13 @@ (fp_text value 0 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 2.098 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 93 FPGA_CFG_MISO)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10783,7 +9334,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 37.15 -63.05 180) (path /57D8556F/58023EE8) (attr smd) @@ -10793,13 +9344,13 @@ (fp_text value 0 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 2.098 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 90 FPGA_CFG_CS_N)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10816,7 +9367,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 16.7523 -16.24 90) (path /57D84CB3/58023FF1) (attr smd) @@ -10826,13 +9377,13 @@ (fp_text value 100 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 3.064 -6.3383 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 140 FT_TXD)) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10849,7 +9400,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 15.495 -16.24 90) (path /57D84CB3/58023FF0) (attr smd) @@ -10859,13 +9410,13 @@ (fp_text value 100 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 3.064 -6.097 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 139 FT_RXD)) (pad 2 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10882,7 +9433,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 92.6084 -15.1318) (path /57D84E30/58023FBB) (attr smd) @@ -10892,13 +9443,13 @@ (fp_text value 100 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 6.7056 -1.1242) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 133 FT_MGMT_TXD)) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10915,7 +9466,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 92.6084 -16.605) (path /57D84E30/58023FBA) (attr smd) @@ -10925,13 +9476,13 @@ (fp_text value 100 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 6.7056 -0.667) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 132 FT_MGMT_RXD)) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10948,7 +9499,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 92.6084 -13.6332 180) (path /57D84E30/58023FB7) (attr smd) @@ -10958,13 +9509,13 @@ (fp_text value 10k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -6.7056 1.6068) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -10981,7 +9532,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 18.0096 -16.24 270) (path /57D84CB3/58023FED) (attr smd) @@ -10991,13 +9542,13 @@ (fp_text value 10k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -3.064 6.5796 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -11014,23 +9565,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 47 -7.5 270) (path /57D84936/58024083) (attr smd) (fp_text reference R92 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.912 0.01 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 170 "Net-(LED1-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -11047,23 +9598,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 41 -7.5 270) (path /57D84936/58024084) (attr smd) (fp_text reference R93 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.912 0.106 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 172 "Net-(LED3-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -11080,23 +9631,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 43 -7.5 270) (path /57D84936/58024081) (attr smd) (fp_text reference R94 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.912 0.074 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 171 "Net-(LED2-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -11113,23 +9664,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 30 -7.5 270) (path /57D84FAD/58023F97) (attr smd) (fp_text reference R95 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.912 0.028 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 174 "Net-(LED9-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -11146,23 +9697,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 24 -7.5 270) (path /57D84FAD/58023F98) (attr smd) (fp_text reference R96 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.912 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 176 "Net-(LED11-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -11179,23 +9730,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 26 -7.5 270) (path /57D84FAD/58023F95) (attr smd) (fp_text reference R97 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.912 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 175 "Net-(LED10-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -11212,23 +9763,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 79 -7 270) (path /57D854CB/58023EF7) (attr smd) (fp_text reference R98 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.92 0.006 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 181 "Net-(LED16-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -11245,23 +9796,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 77 -7 270) (path /57D854CB/58023EF8) (attr smd) (fp_text reference R99 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.92 0.038 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 179 "Net-(LED14-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -11278,23 +9829,23 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer B.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 75 -7 270) (path /57D854CB/58023EF5) (attr smd) (fp_text reference R100 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) (fp_text value 330 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 2.428 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 182 "Net-(LED17-Pad1)")) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) @@ -11311,7 +9862,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 59.4 -62.4 270) (path /57D85134/58023F6A) (attr smd) @@ -11321,13 +9872,13 @@ (fp_text value 1k (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.948 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -11344,7 +9895,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 37.091 -59.1757 180) (path /57D85134/58023F5F) (attr smd) @@ -11354,13 +9905,13 @@ (fp_text value 1k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 2.039 0.0063) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -11377,7 +9928,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 37.091 -60.4076) (path /57D85134/58023F5E) (attr smd) @@ -11387,13 +9938,13 @@ (fp_text value 1k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -2.039 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 255 "/Config interface/FPGA_M0")) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -11410,7 +9961,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 32.475 -75.625) (path /57D85B19/58023E0E) (attr smd) @@ -11420,13 +9971,13 @@ (fp_text value 100k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 0.291 -1.083) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 200 POK_VCCINT)) (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -11443,7 +9994,7 @@ ) ) - (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BD3D76) (tstamp 539EEDBF) + (module Cryptech_Alpha_Footprints:R_0402 (layer F.Cu) (tedit 60BE39E7) (tstamp 539EEDBF) (at 34.417 -70.358 180) (path /57D85B19/58023E0F) (attr smd) @@ -11453,13 +10004,13 @@ (fp_text value 4.7k (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at 1.905 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) (pad 1 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 200 POK_VCCINT)) (pad 2 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) @@ -11476,5148 +10027,6597 @@ ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 5F27EC88) - (at 93.2 -33 270) - (path /57D8509E/5F112F44) + (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BE3769) (tstamp 5F035ED9) + (at 72.3 -28.2 180) + (path /57D8509E/5F090460) (attr smd) - (fp_text reference C228 (at 0.234 2.776 90) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) - ) - (fp_text value 0.1uF (at 0 0 270) (layer Cmts.User) + (fp_text reference C106 (at 0 0) (layer B.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 1 3V3_BATT)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 5F27EC82) - (at 94.2 -33 90) - (path /57D8509E/5F112F4E) - (attr smd) - (fp_text reference C227 (at -0.234 -2.506 90) (layer B.SilkS) - (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) - ) - (fp_text value 0.01uF (at 0 0 270) (layer Cmts.User) + (fp_text value 1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -1.36 -0.26 270) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) + (pad 2 smd rect (at 0 -0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 1 3V3_BATT)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (pad 1 smd rect (at 0 0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (net 572 "/Master Key Memory/MKM_VPP")) + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F048F99) - (at 76.8 -29) - (path /57D8509E/5F14E9EA) - (attr smd) - (fp_text reference C226 (at 0 -4.572) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/175C1D2E-5B2D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F048F93) - (at 76.8 -28 180) - (path /57D8509E/5F154973) + (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BE3769) (tstamp 5F035EC9) + (at 72.3 -31.1 180) + (path /57D8509E/5F043BA5) (attr smd) - (fp_text reference C225 (at 0 4.318) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.01uF (at 0 0) (layer Cmts.User) + (fp_text reference C104 (at 0 0) (layer B.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F048F8D) - (at 81 -33.2 270) - (path /57D8509E/5F149FB8) - (attr smd) - (fp_text reference C224 (at -1.524 -2.312 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -1.36 0.142 270) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) + (pad 2 smd rect (at 0 -0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (pad 1 smd rect (at 0 0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (net 571 "/Master Key Memory/MKM_VCC")) + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F048F87) - (at 83.2 -28 180) - (path /57D8509E/5F13FBA7) - (attr smd) - (fp_text reference C223 (at 2.936 -0.314) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/175C1D2E-5B2D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F048F81) - (at 82 -33.2 90) - (path /57D8509E/5F15426E) + (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BE3769) (tstamp 5F035EC3) + (at 69.9 -28.2 180) + (path /57D8509E/5F09046A) (attr smd) - (fp_text reference C222 (at 1.524 2.582 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.01uF (at 0 0 90) (layer Cmts.User) + (fp_text reference C103 (at 0 0) (layer B.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 1 3V3_BATT)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F048F7B) - (at 83.2 -29) - (path /57D8509E/5F153C00) - (attr smd) - (fp_text reference C221 (at -2.936 0.044) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.01uF (at 0 0) (layer Cmts.User) + (fp_text value 1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -1.22 -0.26 270) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) + (pad 2 smd rect (at 0 -0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 1 3V3_BATT)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F045642) - (at 83.2 -30) - (path /57D8509E/5F11DC09) - (attr smd) - (fp_text reference C220 (at -2.936 -0.226) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.01uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 571 "/Master Key Memory/MKM_VCC")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/175C1D2E-5B2D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F04563C) - (at 76.8 -31) - (path /57D8509E/5F11E1B4) + (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BE3769) (tstamp 5F035EBD) + (at 69.9 -31.3 180) + (path /57D8509E/5F043CFB) (attr smd) - (fp_text reference C219 (at 0 -5.068) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text reference C102 (at 0 0) (layer B.SilkS) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 571 "/Master Key Memory/MKM_VCC")) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F036329) - (at 76.8 -30 180) - (path /57D8509E/5F0798C6) - (attr smd) - (fp_text reference C218 (at 0 4.826) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.01uF (at 0 0) (layer Cmts.User) + (fp_text value 1uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -1.22 -0.058 270) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) + (pad 2 smd rect (at 0 -0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 571 "/Master Key Memory/MKM_VCC")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (pad 1 smd rect (at 0 0.7 270) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (net 1 3V3_BATT)) + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F036323) - (at 83.2 -31 180) - (path /57D8509E/5F077BE8) - (attr smd) - (fp_text reference C217 (at 2.936 0.496) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 571 "/Master Key Memory/MKM_VCC")) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 5F03631D) - (at 86.7 -30.4) - (path /57D8509E/5F05C031) - (attr smd) - (fp_text reference C216 (at 1.692 0.936 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.1))) - ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 573 "/Master Key Memory/MKM_VCC_PLL")) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/175C1D2E-5B2D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 26.1 -84.7) - (path /57D84708/580240C2) + (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BE3769) (tstamp 539EEDBF) + (at 47.7266 -14.2494 270) + (path /57D849FD/58024060) (attr smd) - (fp_text reference C4 (at 0 0) (layer F.SilkS) hide + (fp_text reference C21 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.047uF (at 0 0) (layer Cmts.User) + (fp_text value 1uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 1.2954 0 180) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 202 PWR_18V)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) + (pad 2 smd rect (at 0 -0.7) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 0.7) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" + (at (xyz 0 0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/175C1D2E-5B2D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 25.55 -75.725) - (path /57D84708/580240B6) + (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BE3769) (tstamp 539EEDBF) + (at 55.0672 -51.5112 90) + (path /57D849FD/5802405E) (attr smd) - (fp_text reference C5 (at 0 0) (layer F.SilkS) hide + (fp_text reference C22 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 2.2uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 -2.2352 180) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 149 "Net-(C5-Pad1)")) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) + (pad 2 smd rect (at 0 -0.7 180) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (net 215 "/STM32 power/VCAP1")) + (pad 1 smd rect (at 0 0.7 180) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" + (at (xyz 0 0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/175C1D2E-5B2D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 25.5778 -71.8312) - (path /57D84708/580240C3) + (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BE3769) (tstamp 539EEDBF) + (at 55.0672 -49.6824 90) + (path /57D849FD/5802405D) (attr smd) - (fp_text reference C6 (at 0 0) (layer F.SilkS) hide + (fp_text reference C23 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.047uF (at 0 0) (layer Cmts.User) + (fp_text value 2.2uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at 0 -2.2352 180) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 209 VCC_5V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) + (pad 2 smd rect (at 0 -0.7 180) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (net 215 "/STM32 power/VCAP1")) + (pad 1 smd rect (at 0 0.7 180) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 74.5 -89.5 270) - (path /57D84708/580240C4) - (attr smd) - (fp_text reference C11 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.01uF (at 0 0 90) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 150 "Net-(C11-Pad1)")) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 2 15V_STABLE)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/175C1D2E-5B2D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 71.25 -92.5) - (path /57D84708/580240B5) + (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BE3769) (tstamp 539EEDBF) + (at 65.9638 -24.384) + (path /57D849FD/5802405F) (attr smd) - (fp_text reference C12 (at 0 0) (layer F.SilkS) hide + (fp_text reference C24 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.01uF (at 0 0) (layer Cmts.User) + (fp_text value 2.2uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text user %R (at -0.1778 -2.286 -90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) + (pad 2 smd rect (at 0 -0.7 90) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (net 216 "/STM32 power/VCAP2")) + (pad 1 smd rect (at 0 0.7 90) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 151 "Net-(C12-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" + (at (xyz 0 0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/175C1D2E-5B2D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 89.9922 -96.2152 180) - (path /57D8488D/5802409B) + (module Cryptech_Alpha_Footprints:C_0603 (layer B.Cu) (tedit 60BE3769) (tstamp 539EEDBF) + (at 67.7926 -24.384) + (path /57D849FD/5802405C) (attr smd) - (fp_text reference C14 (at 0 0) (layer F.SilkS) hide + (fp_text reference C25 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value 2.2uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_text user %R (at -0.2286 -2.286 -90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (fp_line (start -0.508 -1.143) (end -0.508 1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 -1.143) (end -0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start 0.508 1.143) (end 0.508 -1.143) (layer B.Fab) (width 0.1)) + (fp_line (start -0.508 1.143) (end 0.508 1.143) (layer B.Fab) (width 0.1)) + (pad 2 smd rect (at 0 -0.7 90) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) + (net 216 "/STM32 power/VCAP2")) + (pad 1 smd rect (at 0 0.7 90) (size 0.8 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 211 "/Entropy source/NOISE_IN")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 89.4842 -81.6864 180) - (path /57D8488D/58024098) - (attr smd) - (fp_text reference C15 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 212 "/Entropy source/RAW_NOISE")) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 4 "Net-(C15-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/175C1D2E-5B2D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 77.343 -88.5444 180) - (path /57D8488D/580240A3) + (module Cryptech_Alpha_Footprints:WE-SHC_36103205_NO_CREAM (layer B.Cu) (tedit 60BDE566) (tstamp 539EEDBF) + (at 83.82 -87.7454) + (path /57D8488D/580240A2) (attr smd) - (fp_text reference C16 (at 0 0) (layer F.SilkS) hide + (fp_text reference S1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value 36103205 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -11.176 -12.192) (end -11.176 9.652) (layer B.Fab) (width 0.1)) + (fp_line (start 11.176 -12.192) (end -11.176 -12.192) (layer B.Fab) (width 0.1)) + (fp_line (start 11.176 9.652) (end 11.176 -12.192) (layer B.Fab) (width 0.1)) + (fp_line (start -11.176 9.652) (end 11.176 9.652) (layer B.Fab) (width 0.1)) + (fp_text user %R (at -5.588 -7.2506) (layer B.Fab) + (effects (font (size 5 5) (thickness 0.5)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 10.2616 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at -10.25 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at -10.25 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at 10.2616 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at 9.1186 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at -9.1 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at -9.1 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at 9.1186 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at 3.7592 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at 3.7592 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at -3.75 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at -3.75 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at 10.2616 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at 10.2616 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at -10.25 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at -10.25 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 28.925 -32.05) - (path /57D84936/58024080) + (module Cryptech_Alpha_Footprints:XTAL3215 (layer F.Cu) (tedit 60BDE4F3) (tstamp 539EEDBF) + (at 19.275 -45.6) + (path /57D84C55/5802401E) (attr smd) - (fp_text reference C17 (at 0 0) (layer F.SilkS) hide + (fp_text reference X1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 5.1pF (at 0 0) (layer Cmts.User) + (fp_text value ABS07-32.768KHZ-T (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 152 "Net-(C17-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (fp_line (start -1.27 2.032) (end -1.27 -2.032) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 2.032) (end -1.27 2.032) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -2.032) (end 1.27 2.032) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -2.032) (end 1.27 -2.032) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) + (pad P$1 smd rect (at 0 -1.2192 90) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) + (net 153 "Net-(C70-Pad2)")) + (pad P$2 smd rect (at 0 1.2 270) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) + (net 154 "Net-(C71-Pad2)")) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 28.175 -38.55 180) - (path /57D84936/58024089) + (module Cryptech_Alpha_Footprints:USB-MINIB (layer F.Cu) (tedit 60BDE442) (tstamp 539EEDBF) + (at 65 14.9) + (path /57D84CB3/58023FF3) (attr smd) - (fp_text reference C18 (at 0 0) (layer F.SilkS) hide + (fp_text reference CN1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 5.1pF (at 0 0) (layer Cmts.User) + (fp_text value 690-005-299-043 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -5.588 5.08) (end -5.588 -5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 5.588 5.08) (end -5.588 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 5.588 -5.08) (end 5.588 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start -5.588 -5.08) (end 5.588 -5.08) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 3 3) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad GND smd rect (at -4.34 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 213 "/STM32 configuration/OSC_OUT")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 144 FT_VREGIN)) + (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 221 "/User USB UART/D1_N")) + (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 222 "/User USB UART/D1_P")) + (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 266 "Net-(CN1-PadID)")) + (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad GND smd rect (at -4.34 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad GND smd rect (at 4.36 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad GND smd rect (at 4.36 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model wrlshp/c-1734035-2-e-3d.wrl + (offset (xyz 0.02539999961853028 -5.009133924770355 2.000001049962997)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 360)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/23D50C2B-5C98.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 13.125 -20.45 180) - (path /57D84936/58024087) + (module Cryptech_Alpha_Footprints:USB-MINIB (layer F.Cu) (tedit 60BDE442) (tstamp 539EEDBF) + (at 85 14.9) + (path /57D84E30/58023FBD) (attr smd) - (fp_text reference C19 (at 0 0) (layer F.SilkS) hide + (fp_text reference CN2 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value 690-005-299-043 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -5.588 5.08) (end -5.588 -5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 5.588 5.08) (end -5.588 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 5.588 -5.08) (end 5.588 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start -5.588 -5.08) (end 5.588 -5.08) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 3 3) (thickness 0.15))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad GND smd rect (at -4.34 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 137 FT_MGMT_VREGIN)) + (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 223 "/MGMT USB UART/DM_N")) + (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 224 "/MGMT USB UART/DM_P")) + (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 267 "Net-(CN2-PadID)")) + (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad GND smd rect (at -4.34 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad GND smd rect (at 4.36 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad GND smd rect (at 4.36 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model wrlshp/c-1734035-2-e-3d.wrl + (offset (xyz 0.02539999961853028 -5.009133924770355 2.000001049962997)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 360)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/23D50C2B-5C98.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 26.6 -23.3 90) - (path /57D84936/5802407E) + (module Cryptech_Alpha_Footprints:TSSOP50P1180X120-86N (layer F.Cu) (tedit 60BDE398) (tstamp 539EEDBF) + (at 86.1704 -49.8264 180) + (path /57D84B22/58024046) (attr smd) - (fp_text reference C20 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference U5 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value IS45S32160F-*** (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_poly (pts (xy -5.08 -10.16) (xy -6.604 -10.16) (xy -6.604 -10.922) (xy -5.08 -10.922)) (layer F.Fab) (width 0.1)) + (fp_line (start 6.604 -10.922) (end -6.604 -10.922) (layer F.Fab) (width 0.1)) + (fp_line (start 6.604 10.922) (end 6.604 -10.922) (layer F.Fab) (width 0.1)) + (fp_line (start -6.604 10.922) (end 6.604 10.922) (layer F.Fab) (width 0.1)) + (fp_line (start -6.604 -10.922) (end -6.604 10.922) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 5 5) (thickness 0.5))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 214 "/STM32 configuration/NRST")) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 41 FMC_D0)) + (pad 3 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 4 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 42 FMC_D1)) + (pad 5 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 43 FMC_D2)) + (pad 6 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 50.6476 -49.3522 180) - (path /57D849FD/58024069) - (attr smd) - (fp_text reference C28 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 7 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 44 FMC_D3)) + (pad 8 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 45 FMC_D4)) + (pad 9 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 46 FMC_D5)) + (pad 11 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 47 FMC_D6)) + (pad 12 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 13 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 48 FMC_D7)) + (pad 14 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 16 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 73 FMC_NBL0)) + (pad 17 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 89 FMC_SDNWE)) + (pad 18 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 85 FMC_SDNCAS)) + (pad 19 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 88 FMC_SDNRAS)) + (pad 20 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 86 FMC_SDNE0)) + (pad 21 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 25 FMC_A11)) + (pad 22 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 28 FMC_A14)) + (pad 23 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 29 FMC_A15)) + (pad 24 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 24 FMC_A10)) + (pad 25 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 14 FMC_A0)) + (pad 26 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 15 FMC_A1)) + (pad 27 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 16 FMC_A2)) + (pad 28 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 75 FMC_NBL2)) + (pad 29 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 30 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 57 FMC_D16)) + (pad 32 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 65.4304 -35.6616 270) - (path /57D849FD/5802406A) - (attr smd) - (fp_text reference C29 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 33 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 58 FMC_D17)) + (pad 34 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 59 FMC_D18)) + (pad 35 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 36 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 60 FMC_D19)) + (pad 37 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 61 FMC_D20)) + (pad 38 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (pad 39 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 62 FMC_D21)) + (pad 40 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 63 FMC_D22)) + (pad 41 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 42 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 64 FMC_D23)) + (pad 43 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 86 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 85 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 56 FMC_D15)) + (pad 84 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 83 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 55 FMC_D14)) + (pad 82 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 54 FMC_D13)) + (pad 81 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 80 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 53 FMC_D12)) + (pad 79 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 52 FMC_D11)) + (pad 78 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 77 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 51 FMC_D10)) + (pad 76 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 50 FMC_D9)) + (pad 75 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 74 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 49 FMC_D8)) + (pad 73 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 72 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 71 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 74 FMC_NBL1)) + (pad 70 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 69 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 26 FMC_A12)) + (pad 68 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 84 FMC_SDCLK)) + (pad 67 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 82 FMC_SDCKE0)) + (pad 66 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 23 FMC_A9)) + (pad 65 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 22 FMC_A8)) + (pad 64 smd oval (at 5.75 0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 21 FMC_A7)) + (pad 63 smd oval (at 5.75 1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 20 FMC_A6)) + (pad 62 smd oval (at 5.75 1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 19 FMC_A5)) + (pad 61 smd oval (at 5.75 2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 18 FMC_A4)) + (pad 60 smd oval (at 5.75 2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 17 FMC_A3)) + (pad 59 smd oval (at 5.75 3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 76 FMC_NBL3)) + (pad 58 smd oval (at 5.75 3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 57 smd oval (at 5.75 4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 56 smd oval (at 5.75 4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 72 FMC_D31)) + (pad 55 smd oval (at 5.75 5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 54 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 71 FMC_D30)) + (pad 53 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 70 FMC_D29)) + (pad 52 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 51 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 69 FMC_D28)) + (pad 50 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 68 FMC_D27)) + (pad 49 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 48 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 67 FMC_D26)) + (pad 47 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 66 FMC_D25)) + (pad 46 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 45 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 65 FMC_D24)) + (pad 44 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model wrlshp/D87FE1D2-D8B7.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 57.3532 -49.784 90) - (path /57D849FD/5802406B) + (module Cryptech_Alpha_Footprints:TSSOP50P1180X120-86N (layer B.Cu) (tedit 60BDE398) (tstamp 539EEDBF) + (at 80.6704 -49.8264) + (path /57D84B22/58024042) (attr smd) - (fp_text reference C30 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference U6 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value IS45S32160F-*** (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_poly (pts (xy -5.08 10.16) (xy -6.604 10.16) (xy -6.604 10.922) (xy -5.08 10.922)) (layer B.Fab) (width 0.1)) + (fp_line (start 6.604 10.922) (end -6.604 10.922) (layer B.Fab) (width 0.1)) + (fp_line (start 6.604 -10.922) (end 6.604 10.922) (layer B.Fab) (width 0.1)) + (fp_line (start -6.604 -10.922) (end 6.604 -10.922) (layer B.Fab) (width 0.1)) + (fp_line (start -6.604 10.922) (end -6.604 -10.922) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 -90) (layer B.Fab) + (effects (font (size 5 5) (thickness 0.5)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 1 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 41 FMC_D0)) + (pad 3 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 4 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 42 FMC_D1)) + (pad 5 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 43 FMC_D2)) + (pad 6 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (pad 7 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_D3)) + (pad 8 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_D4)) + (pad 9 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 10 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_D5)) + (pad 11 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_D6)) + (pad 12 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 13 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_D7)) + (pad 14 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 15 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 16 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_NBL0)) + (pad 17 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_SDNWE)) + (pad 18 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_SDNCAS)) + (pad 19 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_SDNRAS)) + (pad 20 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_SDNE1)) + (pad 21 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 25 FMC_A11)) + (pad 22 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 28 FMC_A14)) + (pad 23 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 29 FMC_A15)) + (pad 24 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 24 FMC_A10)) + (pad 25 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 14 FMC_A0)) + (pad 26 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 15 FMC_A1)) + (pad 27 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 16 FMC_A2)) + (pad 28 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_NBL2)) + (pad 29 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 30 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 31 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 57 FMC_D16)) + (pad 32 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 33 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_D17)) + (pad 34 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_D18)) + (pad 35 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 36 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 60 FMC_D19)) + (pad 37 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 61 FMC_D20)) + (pad 38 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 39 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 62 FMC_D21)) + (pad 40 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 63 FMC_D22)) + (pad 41 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 42 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 64 FMC_D23)) + (pad 43 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 86 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 85 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_D15)) + (pad 84 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 83 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_D14)) + (pad 82 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_D13)) + (pad 81 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 80 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_D12)) + (pad 79 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_D11)) + (pad 78 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 77 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_D10)) + (pad 76 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_D9)) + (pad 75 smd oval (at 5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 74 smd oval (at 5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_D8)) + (pad 73 smd oval (at 5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 72 smd oval (at 5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 71 smd oval (at 5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_NBL1)) + (pad 70 smd oval (at 5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 69 smd oval (at 5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 26 FMC_A12)) + (pad 68 smd oval (at 5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_SDCLK)) + (pad 67 smd oval (at 5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_SDCKE1)) + (pad 66 smd oval (at 5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 23 FMC_A9)) + (pad 65 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 22 FMC_A8)) + (pad 64 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 21 FMC_A7)) + (pad 63 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 20 FMC_A6)) + (pad 62 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 19 FMC_A5)) + (pad 61 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 18 FMC_A4)) + (pad 60 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 17 FMC_A3)) + (pad 59 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_NBL3)) + (pad 58 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 57 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 56 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D31)) + (pad 55 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 54 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D30)) + (pad 53 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 70 FMC_D29)) + (pad 52 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 51 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 69 FMC_D28)) + (pad 50 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 68 FMC_D27)) + (pad 49 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 48 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 67 FMC_D26)) + (pad 47 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 66 FMC_D25)) + (pad 46 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 45 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 65 FMC_D24)) + (pad 44 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (model wrlshp/D87FE1D2-D8B7.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 61.341 -15.9512) - (path /57D849FD/5802406D) + (module Cryptech_Alpha_Footprints:TSQFP50P3000X3000X160-208N (layer B.Cu) (tedit 60BDE330) (tstamp 539EEDBF) + (at 48.6918 -32.6136) + (path /57D84936/58024086) (attr smd) - (fp_text reference C31 (at 0 0) (layer F.SilkS) hide + (fp_text reference U4 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value STM32F429BIT6 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_poly (pts (xy -13.208 13.208) (xy -15.748 13.208) (xy -15.748 15.748) (xy -13.208 15.748)) (layer B.Fab) (width 0.1)) + (fp_line (start 15.748 15.748) (end -15.748 15.748) (layer B.Fab) (width 0.1)) + (fp_line (start 15.748 -15.748) (end 15.748 15.748) (layer B.Fab) (width 0.1)) + (fp_line (start -15.748 -15.748) (end 15.748 -15.748) (layer B.Fab) (width 0.1)) + (fp_line (start -15.748 15.748) (end -15.748 -15.748) (layer B.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (effects (font (size 10 10) (thickness 0.5)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 208 smd oval (at -12.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 70 FMC_D29)) + (pad 207 smd oval (at -12.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 69 FMC_D28)) + (pad 206 smd oval (at -11.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_NBL3)) + (pad 205 smd oval (at -11.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_NBL2)) + (pad 204 smd oval (at -10.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 203 smd oval (at -10.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 202 smd oval (at -9.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 31.9278 -26.6192 270) - (path /57D849FD/5802406C) - (attr smd) - (fp_text reference C32 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 201 smd oval (at -9.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_NBL1)) + (pad 200 smd oval (at -8.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_NBL0)) + (pad 199 smd oval (at -8.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 272 "Net-(U4-Pad199)")) + (pad 198 smd oval (at -7.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 273 "Net-(U4-Pad198)")) + (pad 197 smd oval (at -7.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 248 "/STM32 configuration/BOOT0")) + (pad 196 smd oval (at -6.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_NL)) + (pad 195 smd oval (at -6.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_SDNE1)) + (pad 194 smd oval (at -5.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_SDCKE1)) + (pad 193 smd oval (at -5.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 274 "Net-(U4-Pad193)")) + (pad 192 smd oval (at -4.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 275 "Net-(U4-Pad192)")) + (pad 191 smd oval (at -4.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_SDNCAS)) + (pad 190 smd oval (at -3.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 12 ARM_LED4)) + (pad 189 smd oval (at -3.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 11 ARM_LED3)) + (pad 188 smd oval (at -2.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 10 ARM_LED2)) + (pad 187 smd oval (at -2.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 9 ARM_LED1)) + (pad 186 smd oval (at -1.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 276 "Net-(U4-Pad186)")) + (pad 185 smd oval (at -1.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 184 smd oval (at -0.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 30.5308 -41.4782 90) - (path /57D849FD/58024053) - (attr smd) - (fp_text reference C33 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 183 smd oval (at -0.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 39 FMC_A25)) + (pad 182 smd oval (at 0.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 38 FMC_A24)) + (pad 181 smd oval (at 0.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 277 "Net-(U4-Pad181)")) + (pad 180 smd oval (at 1.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 278 "Net-(U4-Pad180)")) + (pad 179 smd oval (at 1.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 279 "Net-(U4-Pad179)")) + (pad 178 smd oval (at 2.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 280 "Net-(U4-Pad178)")) + (pad 177 smd oval (at 2.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 96 FPGA_DONE)) + (pad 176 smd oval (at 3.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 281 "Net-(U4-Pad176)")) + (pad 175 smd oval (at 3.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 123 FPGA_IRQ_N_3)) + (pad 174 smd oval (at 4.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 122 FPGA_IRQ_N_2)) + (pad 173 smd oval (at 4.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_NE1)) + (pad 172 smd oval (at 5.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_NWAIT)) + (pad 171 smd oval (at 5.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 170 smd oval (at 6.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.9346 -49.784 90) - (path /57D849FD/58024061) - (attr smd) - (fp_text reference C34 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 169 smd oval (at 6.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_NWE)) + (pad 168 smd oval (at 7.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_NOE)) + (pad 167 smd oval (at 7.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 40 FMC_CLK)) + (pad 166 smd oval (at 8.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 282 "Net-(U4-Pad166)")) + (pad 165 smd oval (at 8.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_D3)) + (pad 164 smd oval (at 9.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 43 FMC_D2)) + (pad 163 smd oval (at 9.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 576 ARM_SPI3_MOSI)) + (pad 162 smd oval (at 10.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 577 ARM_SPI3_MISO)) + (pad 161 smd oval (at 10.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 578 ARM_SPI3_SCK)) + (pad 160 smd oval (at 11.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 283 "Net-(U4-Pad160)")) + (pad 159 smd oval (at 11.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 238 "/STM32 configuration/SWDCLK")) + (pad 158 smd oval (at 12.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 157 smd oval (at 12.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 68 FMC_D27)) + (pad 156 smd oval (at 14.75 12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 67 FMC_D26)) + (pad 155 smd oval (at 14.75 12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 66 FMC_D25)) + (pad 154 smd oval (at 14.75 11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 65 FMC_D24)) + (pad 153 smd oval (at 14.75 11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 64 FMC_D23)) + (pad 152 smd oval (at 14.75 10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 63 FMC_D22)) + (pad 151 smd oval (at 14.75 10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 62 FMC_D21)) + (pad 150 smd oval (at 14.75 9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 149 smd oval (at 14.75 9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 37.8 -20.5 90) - (path /57D849FD/58024054) - (attr smd) - (fp_text reference C35 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 148 smd oval (at 14.75 8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 216 "/STM32 power/VCAP2")) + (pad 147 smd oval (at 14.75 8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 237 "/STM32 configuration/SWDIO")) + (pad 146 smd oval (at 14.75 7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 129 FT_MGMT_CTS)) + (pad 145 smd oval (at 14.75 7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 131 FT_MGMT_RTS)) + (pad 144 smd oval (at 14.75 6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 133 FT_MGMT_TXD)) + (pad 143 smd oval (at 14.75 6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 132 FT_MGMT_RXD)) + (pad 142 smd oval (at 14.75 5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 130 FT_MGMT_DTR)) + (pad 141 smd oval (at 14.75 5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 579 ARM_SPI3_CS_N)) + (pad 140 smd oval (at 14.75 4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 585 ICE40_CRESET)) + (pad 139 smd oval (at 14.75 4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 284 "Net-(U4-Pad139)")) + (pad 138 smd oval (at 14.75 3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 285 "Net-(U4-Pad138)")) + (pad 137 smd oval (at 14.75 3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 136 smd oval (at 14.75 2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 65.4304 -29.7434 90) - (path /57D849FD/58024062) - (attr smd) - (fp_text reference C36 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 135 smd oval (at 14.75 2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_SDCLK)) + (pad 134 smd oval (at 14.75 1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 286 "Net-(U4-Pad134)")) + (pad 133 smd oval (at 14.75 1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 287 "Net-(U4-Pad133)")) + (pad 132 smd oval (at 14.75 0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 29 FMC_A15)) + (pad 131 smd oval (at 14.75 0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 28 FMC_A14)) + (pad 130 smd oval (at 14.75 -0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 27 FMC_A13)) + (pad 129 smd oval (at 14.75 -0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 26 FMC_A12)) + (pad 128 smd oval (at 14.75 -1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 288 "Net-(U4-Pad128)")) + (pad 127 smd oval (at 14.75 -1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 289 "Net-(U4-Pad127)")) + (pad 126 smd oval (at 14.75 -2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 290 "Net-(U4-Pad126)")) + (pad 125 smd oval (at 14.75 -2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 124 smd oval (at 14.75 -3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 123 smd oval (at 14.75 -3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 121 FPGA_IRQ_N_1)) + (pad 122 smd oval (at 14.75 -4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 120 FPGA_IRQ_N_0)) + (pad 121 smd oval (at 14.75 -4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 291 "Net-(U4-Pad121)")) + (pad 120 smd oval (at 14.75 -5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 124 FPGA_PROGRAM_B)) + (pad 119 smd oval (at 14.75 -5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 119 FPGA_INIT_B)) + (pad 118 smd oval (at 14.75 -6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 292 "Net-(U4-Pad118)")) + (pad 117 smd oval (at 14.75 -6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 42 FMC_D1)) + (pad 116 smd oval (at 14.75 -7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 41 FMC_D0)) + (pad 115 smd oval (at 14.75 -7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 114 smd oval (at 14.75 -8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (pad 113 smd oval (at 14.75 -8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 32 FMC_A18)) + (pad 112 smd oval (at 14.75 -9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 31 FMC_A17)) + (pad 111 smd oval (at 14.75 -9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 30 FMC_A16)) + (pad 110 smd oval (at 14.75 -10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_D15)) + (pad 109 smd oval (at 14.75 -10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_D14)) + (pad 108 smd oval (at 14.75 -11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_D13)) + (pad 107 smd oval (at 14.75 -11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 ARM_FPGA_CFG_MOSI)) + (pad 106 smd oval (at 14.75 -12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 6 ARM_FPGA_CFG_MISO)) + (pad 105 smd oval (at 14.75 -12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 8 ARM_FPGA_CFG_SCLK)) + (pad 104 smd oval (at 12.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 5 ARM_FPGA_CFG_CS_N)) + (pad 103 smd oval (at 12.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 102 smd oval (at 11.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 61 FMC_D20)) + (pad 101 smd oval (at 11.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 60 FMC_D19)) + (pad 100 smd oval (at 10.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_D18)) + (pad 99 smd oval (at 10.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_D17)) + (pad 98 smd oval (at 9.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 57 FMC_D16)) + (pad 97 smd oval (at 9.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 586 ICE40_GPIO_ARM_0)) + (pad 96 smd oval (at 8.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 587 ICE40_GPIO_ARM_1)) + (pad 95 smd oval (at 8.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 293 "Net-(U4-Pad95)")) + (pad 94 smd oval (at 7.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 93 smd oval (at 7.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 92 smd oval (at 6.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 215 "/STM32 power/VCAP1")) + (pad 91 smd oval (at 6.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 588 ICE40_GPIO_ARM_2)) + (pad 90 smd oval (at 5.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 589 ICE40_GPIO_ARM_3)) + (pad 89 smd oval (at 5.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_D12)) + (pad 88 smd oval (at 4.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_D11)) + (pad 87 smd oval (at 4.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_D10)) + (pad 86 smd oval (at 3.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_D9)) + (pad 85 smd oval (at 3.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_D8)) + (pad 84 smd oval (at 2.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_D7)) + (pad 83 smd oval (at 2.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 82 smd oval (at 1.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 81 smd oval (at 1.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_D6)) + (pad 80 smd oval (at 0.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_D5)) + (pad 79 smd oval (at 0.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_D4)) + (pad 78 smd oval (at -0.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 25 FMC_A11)) + (pad 77 smd oval (at -0.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 24 FMC_A10)) + (pad 76 smd oval (at -1.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 23 FMC_A9)) + (pad 75 smd oval (at -1.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 22 FMC_A8)) + (pad 74 smd oval (at -2.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 21 FMC_A7)) + (pad 73 smd oval (at -2.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 72 smd oval (at -3.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 71 smd oval (at -3.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 20 FMC_A6)) + (pad 70 smd oval (at -4.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_SDNRAS)) + (pad 69 smd oval (at -4.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 294 "Net-(U4-Pad69)")) + (pad 68 smd oval (at -5.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 295 "Net-(U4-Pad68)")) + (pad 67 smd oval (at -5.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 296 "Net-(U4-Pad67)")) + (pad 66 smd oval (at -6.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 297 "Net-(U4-Pad66)")) + (pad 65 smd oval (at -6.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 298 "Net-(U4-Pad65)")) + (pad 64 smd oval (at -7.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 299 "Net-(U4-Pad64)")) + (pad 63 smd oval (at -7.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 300 "Net-(U4-Pad63)")) + (pad 62 smd oval (at -8.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 301 "Net-(U4-Pad62)")) + (pad 61 smd oval (at -8.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 145 KSM_PROM_CS_N)) + (pad 60 smd oval (at -9.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 59 smd oval (at -9.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 58 smd oval (at -10.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 302 "Net-(U4-Pad58)")) + (pad 57 smd oval (at -10.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 "Net-(U4-Pad57)")) + (pad 56 smd oval (at -11.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 147 KSM_PROM_MOSI)) + (pad 55 smd oval (at -11.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 146 KSM_PROM_MISO)) + (pad 54 smd oval (at -12.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 148 KSM_PROM_SCLK)) + (pad 53 smd oval (at -12.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 128 FT_DTR)) + (pad 52 smd oval (at -14.75 -12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 51 smd oval (at -14.75 -12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 50 smd oval (at -14.75 -11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 140 FT_TXD)) + (pad 49 smd oval (at -14.75 -11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 208 RTC_SDA)) + (pad 48 smd oval (at -14.75 -10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 207 RTC_SCL)) + (pad 47 smd oval (at -14.75 -10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 206 RTC_MFP)) + (pad 46 smd oval (at -14.75 -9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 304 "Net-(U4-Pad46)")) + (pad 45 smd oval (at -14.75 -9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 139 FT_RXD)) + (pad 44 smd oval (at -14.75 -8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 127 FT_CTS)) + (pad 43 smd oval (at -14.75 -8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 138 FT_RTS)) + (pad 42 smd oval (at -14.75 -7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 41 smd oval (at -14.75 -7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 40 smd oval (at -14.75 -6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 39 smd oval (at -14.75 -6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 38 smd oval (at -14.75 -5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 82 FMC_SDCKE0)) + (pad 37 smd oval (at -14.75 -5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 86 FMC_SDNE0)) + (pad 36 smd oval (at -14.75 -4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 305 "Net-(U4-Pad36)")) + (pad 35 smd oval (at -14.75 -4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_SDNWE)) + (pad 34 smd oval (at -14.75 -3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 214 "/STM32 configuration/NRST")) + (pad 33 smd oval (at -14.75 -3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 213 "/STM32 configuration/OSC_OUT")) + (pad 32 smd oval (at -14.75 -2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 247 "/STM32 configuration/OSC_IN")) + (pad 31 smd oval (at -14.75 -2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 306 "Net-(U4-Pad31)")) + (pad 30 smd oval (at -14.75 -1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 307 "Net-(U4-Pad30)")) + (pad 29 smd oval (at -14.75 -1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 308 "Net-(U4-Pad29)")) + (pad 28 smd oval (at -14.75 -0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 309 "Net-(U4-Pad28)")) + (pad 27 smd oval (at -14.75 -0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 91 FPGA_CFG_CTRL_ARM_ENA)) + (pad 26 smd oval (at -14.75 0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 25 smd oval (at -14.75 0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 24 smd oval (at -14.75 1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 19 FMC_A5)) + (pad 23 smd oval (at -14.75 1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 18 FMC_A4)) + (pad 22 smd oval (at -14.75 2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 17 FMC_A3)) + (pad 21 smd oval (at -14.75 2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 92 FPGA_CFG_CTRL_FPGA_DIS)) + (pad 20 smd oval (at -14.75 3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 310 "Net-(U4-Pad20)")) + (pad 19 smd oval (at -14.75 3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 311 "Net-(U4-Pad19)")) + (pad 18 smd oval (at -14.75 4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 16 FMC_A2)) + (pad 17 smd oval (at -14.75 4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 15 FMC_A1)) + (pad 16 smd oval (at -14.75 5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 14 FMC_A0)) + (pad 15 smd oval (at -14.75 5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 14 smd oval (at -14.75 6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 13 smd oval (at -14.75 6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 312 "Net-(U4-Pad13)")) + (pad 12 smd oval (at -14.75 7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D31)) + (pad 11 smd oval (at -14.75 7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D30)) + (pad 10 smd oval (at -14.75 8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 313 "Net-(U4-Pad10)")) + (pad 9 smd oval (at -14.75 8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 314 "Net-(U4-Pad9)")) + (pad 8 smd oval (at -14.75 9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 584 ICE40_CDONE)) + (pad 7 smd oval (at -14.75 9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 315 "Net-(U4-Pad7)")) + (pad 6 smd oval (at -14.75 10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 191 "Net-(R32-Pad2)")) + (pad 5 smd oval (at -14.75 10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 36 FMC_A22)) + (pad 4 smd oval (at -14.75 11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 35 FMC_A21)) + (pad 3 smd oval (at -14.75 11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 34 FMC_A20)) + (pad 2 smd oval (at -14.75 12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 33 FMC_A19)) + (pad 1 smd oval (at -14.75 12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 37 FMC_A23)) + (model wrlshp/1B9BC620-BA33.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 39.2 -20.3 90) - (path /57D849FD/58024055) + (module Cryptech_Alpha_Footprints:TACTILE_SWITCH (layer F.Cu) (tedit 60BDE2C1) (tstamp 539EEDBF) + (at 62.8 -5.3608) + (path /57D84FAD/58023F9C) (attr smd) - (fp_text reference C37 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference S2 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value EVQPT9A15 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -3.048 3.048) (end -3.048 -3.048) (layer F.Fab) (width 0.1)) + (fp_line (start 3.048 3.048) (end -3.048 3.048) (layer F.Fab) (width 0.1)) + (fp_line (start 3.048 -3.048) (end 3.048 3.048) (layer F.Fab) (width 0.1)) + (fp_line (start -3.048 -3.048) (end 3.048 -3.048) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 2 2) (thickness 0.15))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad B2 smd rect (at -1.8542 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad B1 smd rect (at -1.8542 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad A1 smd rect (at 1.85 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 618 "Net-(S2-PadA1)")) + (pad A2 smd rect (at 1.85 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 604 ICE40_PANIC)) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 47.7266 -15.9512) - (path /57D849FD/58024064) + (module Cryptech_Alpha_Footprints:TSOT-8-23 (layer F.Cu) (tedit 60BDE0CF) (tstamp 539EEDBF) + (at 70.5 -89.75) + (path /57D84708/580240B8) (attr smd) - (fp_text reference C38 (at 0 0) (layer F.SilkS) hide + (fp_text reference U2 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value LT3060ITS8-15#TRMPBF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_poly (pts (xy -0.508 -0.762) (xy -2.286 -0.762) (xy -2.286 -1.524) (xy -0.508 -1.524)) (layer F.Fab) (width 0.1)) + (fp_line (start -2.286 1.524) (end -2.286 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 2.286 1.524) (end -2.286 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 2.286 -1.524) (end 2.286 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -2.286 -1.524) (end 2.286 -1.524) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0.254) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -1.3 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 243 /Power/15V_LDO_ENABLE)) + (pad 2 smd rect (at -1.3 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 3 smd rect (at -1.3 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 4 smd rect (at -1.3 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 5 smd rect (at 1.3208 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 202 PWR_18V)) + (pad 6 smd rect (at 1.3208 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 2 15V_STABLE)) + (pad 7 smd rect (at 1.3208 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 150 "Net-(C11-Pad1)")) + (pad 8 smd rect (at 1.3208 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 151 "Net-(C12-Pad2)")) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 54.6862 -15.9512) - (path /57D849FD/58024056) + (module Cryptech_Alpha_Footprints:SOT-23-5 (layer B.Cu) (tedit 60BDE057) (tstamp 539EEDBF) + (at 77.3684 -85.1408) + (path /57D8488D/5802409C) (attr smd) - (fp_text reference C39 (at 0 0) (layer F.SilkS) hide + (fp_text reference U3 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value MC74HC1G14DTT1G (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_poly (pts (xy 2.032 -1.524) (xy 0.762 -1.524) (xy 0.762 -1.27) (xy 1.778 -1.27) + (xy 1.778 -0.508) (xy 2.032 -0.508)) (layer B.Fab) (width 0.1)) + (fp_line (start -2.032 -1.524) (end -2.032 1.524) (layer B.Fab) (width 0.1)) + (fp_line (start 2.032 -1.524) (end -2.032 -1.524) (layer B.Fab) (width 0.1)) + (fp_line (start 2.032 1.524) (end 2.032 -1.524) (layer B.Fab) (width 0.1)) + (fp_line (start -2.032 1.524) (end 2.032 1.524) (layer B.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 5 smd rect (at -1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 4 smd rect (at -1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 13 DIGITIZED_NOISE)) + (pad 3 smd rect (at 1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (pad 2 smd rect (at 1.35 0 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 225 "/Entropy source/AMPLIFIED")) + (pad 1 smd oval (at 1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 271 "Net-(U3-Pad1)")) + (model "wrlshp/User Library-SOT23-5-1.wrl" (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 31.9278 -45.1358 270) - (path /57D849FD/58024065) - (attr smd) - (fp_text reference C40 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/612DFB50-5309.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 31.9278 -41.4782 90) - (path /57D849FD/58024057) + (module Cryptech_Alpha_Footprints:SOT-23 (layer B.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 82.8548 -89.1794 90) + (path /57D8488D/58024095) (attr smd) - (fp_text reference C41 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference D1 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value BAT54LT1G (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 1.778) (end -1.524 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 -1.778) (end 1.524 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end 1.524 1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end -1.524 1.778) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 -90) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 3 smd rect (at 0 -1.1 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 225 "/Entropy source/AMPLIFIED")) + (pad 2 smd rect (at -0.95 1.1 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask)) + (pad 1 smd rect (at 0.95 1.1 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 4 "Net-(C15-Pad2)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 66.294 -21.971) - (path /57D849FD/58024066) + (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 20.9804 -63.5508 270) + (path /57D85B19/58023E10) (attr smd) - (fp_text reference C42 (at 0 0) (layer F.SilkS) hide + (fp_text reference D2 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value BAT54LT1G (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 3 smd rect (at 0 1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 209 VCC_5V0)) + (pad 2 smd rect (at -0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 204 PWR_ENA_VCCINT)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 39.2176 -49.3522) - (path /57D849FD/58024058) + (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 11.6078 -47.2694 270) + (path /57D85B19/58023E0A) (attr smd) - (fp_text reference C43 (at 0 0) (layer F.SilkS) hide + (fp_text reference D3 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value BAT54LT1G (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 3 smd rect (at 0 1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 199 POK_VCCAUX)) + (pad 2 smd rect (at -0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 205 PWR_ENA_VCCO)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 45.6438 -49.3522 180) - (path /57D849FD/58024067) + (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 32.8168 -72.9234 90) + (path /57D85B19/58023E0D) (attr smd) - (fp_text reference C44 (at 0 0) (layer F.SilkS) hide + (fp_text reference D4 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value BAT54LT1G (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 3 smd rect (at 0 1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 200 POK_VCCINT)) + (pad 2 smd rect (at -0.95 -1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 0.95 -1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 203 PWR_ENA_VCCAUX)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 65.4304 -40.6146 90) - (path /57D849FD/58024059) + (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 72.452 -95.2388) + (path /57D84708/580240BE) (attr smd) - (fp_text reference C45 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference Q1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 2N7002 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 3 smd rect (at 0 1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 169 "Net-(JP2-Pad2)")) + (pad 2 smd rect (at -0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 185 "Net-(Q1-Pad1)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 31.9278 -31.877 270) - (path /57D849FD/58024068) + (module Cryptech_Alpha_Footprints:SOT-23 (layer B.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 90.3732 -92.7862 270) + (path /57D8488D/580240A1) (attr smd) - (fp_text reference C46 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference Q2 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value BC818-40LT1G (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 1.778) (end -1.524 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 -1.778) (end 1.524 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end 1.524 1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end -1.524 1.778) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 3 smd rect (at 0 -1.1) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 269 "Net-(Q2-Pad3)")) + (pad 2 smd rect (at -0.95 1.1) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 211 "/Entropy source/NOISE_IN")) + (pad 1 smd rect (at 0.95 1.1) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 245 "/Entropy source/NOISE_OUT")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 94.0562 -38.608 270) - (path /57D84B22/5802402F) + (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 89.3064 -73.0504 270) + (path /57D85134/58023F5B) (attr smd) - (fp_text reference C47 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference Q4 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 2N7002 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 3 smd rect (at 0 1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 246 "/Config interface/FPGA_INIT_B_INT")) + (pad 2 smd rect (at -0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0.95 -1.1 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 119 FPGA_INIT_B)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 78.105 -41.2274 270) - (path /57D84B22/58024030) + (module Cryptech_Alpha_Footprints:SOT-23 (layer F.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 15.7398 -42.4106 90) + (path /57D85B19/58023E16) (attr smd) - (fp_text reference C48 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference Q6 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 2N7002 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -1.778) (end -1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 1.778) (end 1.524 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end 1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end -1.524 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 3 smd rect (at 0 1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 184 "Net-(LED18-Pad2)")) + (pad 2 smd rect (at -0.95 -1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0.95 -1.1) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 201 POK_VCCO)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 94.0562 -55.9054 270) - (path /57D84B22/58024031) + (module Cryptech_Alpha_Footprints:SOT-23 (layer B.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 90.2208 -88.1634 180) + (path /57D8488D/580240A0) (attr smd) - (fp_text reference C49 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference T1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value BC847BLT3G (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 1.778) (end -1.524 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 -1.778) (end 1.524 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end 1.524 1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end -1.524 1.778) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 3 smd rect (at 0 -1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 212 "/Entropy source/RAW_NOISE")) + (pad 2 smd rect (at -0.95 1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0.95 1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 245 "/Entropy source/NOISE_OUT")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 78.105 -58.3946 90) - (path /57D84B22/58024033) + (module Cryptech_Alpha_Footprints:SOT-23 (layer B.Cu) (tedit 60BDDFDC) (tstamp 539EEDBF) + (at 84.201 -82.7532) + (path /57D8488D/5802409F) (attr smd) - (fp_text reference C50 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference T2 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value BC847BLT3G (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 1.778) (end -1.524 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 -1.778) (end 1.524 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -1.778) (end 1.524 1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 1.778) (end -1.524 1.778) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 -180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 3 smd rect (at 0 -1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 225 "/Entropy source/AMPLIFIED")) + (pad 2 smd rect (at -0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 4 "Net-(C15-Pad2)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/04B9CA18-3B1B.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 94.0562 -45.9232 270) - (path /57D84B22/58024032) + (module Cryptech_Alpha_Footprints:SOIC127P600X175-8N (layer F.Cu) (tedit 60BDDF09) (tstamp 539EEDBF) + (at 25.6 -43.45 270) + (path /57D84C55/58024021) (attr smd) - (fp_text reference C51 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference U7 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value MCP79412-I_SN (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy -1.016 4.064) (xy -2.794 4.064) (xy -2.794 1.778) (xy -1.016 1.778)) (layer F.Fab) (width 0.1)) + (fp_line (start -2.794 4.064) (end -2.794 -4.064) (layer F.Fab) (width 0.1)) + (fp_line (start 2.794 4.064) (end -2.794 4.064) (layer F.Fab) (width 0.1)) + (fp_line (start 2.794 -4.064) (end 2.794 4.064) (layer F.Fab) (width 0.1)) + (fp_line (start -2.794 -4.064) (end 2.794 -4.064) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0.762 0) (layer F.Fab) + (effects (font (size 2 2) (thickness 0.15))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1.905 2.7178) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 153 "Net-(C70-Pad2)")) + (pad 2 smd rect (at -0.635 2.7178) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 154 "Net-(C71-Pad2)")) + (pad 3 smd rect (at 0.635 2.7178) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) + (pad 4 smd rect (at 1.905 2.7178) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 5 smd rect (at 1.905 -2.6924) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 208 RTC_SDA)) + (pad 6 smd rect (at 0.635 -2.6924) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 207 RTC_SCL)) + (pad 7 smd rect (at -0.635 -2.6924) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 206 RTC_MFP)) + (pad 8 smd rect (at -1.905 -2.6924) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 78.105 -55.5244 90) - (path /57D84B22/58024034) + (module Cryptech_Alpha_Footprints:SO20W (layer F.Cu) (tedit 60BDDB8C) (tstamp 539EEDBF) + (at 39.356 -38.3524 90) + (path /57D85260/58023F40) (attr smd) - (fp_text reference C52 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference IC2 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value MC74AC244DW* (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_poly (pts (xy -4.826 6.604) (xy -6.604 6.604) (xy -6.604 3.556) (xy -4.826 3.556)) (layer F.Fab) (width 0.1)) + (fp_line (start 6.604 -6.604) (end -6.604 -6.604) (layer F.Fab) (width 0.1)) + (fp_line (start 6.604 6.604) (end 6.604 -6.604) (layer F.Fab) (width 0.1)) + (fp_line (start -6.604 6.604) (end 6.604 6.604) (layer F.Fab) (width 0.1)) + (fp_line (start -6.604 -6.604) (end -6.604 6.604) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 4 4) (thickness 0.3))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 11 smd rect (at 5.715 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 90 FPGA_CFG_CS_N)) + (pad 12 smd rect (at 4.445 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 6 ARM_FPGA_CFG_MISO)) + (pad 10 smd rect (at 5.715 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 9 smd rect (at 4.445 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 226 "/Config memory/FPGA_PROM_CS_N")) + (pad 20 smd rect (at -5.715 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 19 smd rect (at -4.445 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 227 "/Config memory/SPI_B_TRISTATE")) + (pad 18 smd rect (at -3.175 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 226 "/Config memory/FPGA_PROM_CS_N")) + (pad 17 smd rect (at -1.905 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 228 "/Config memory/FPGA_PROM_MISO")) + (pad 16 smd rect (at -0.635 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 229 "/Config memory/FPGA_PROM_SCLK")) + (pad 15 smd rect (at 0.635 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 94 FPGA_CFG_MOSI)) + (pad 14 smd rect (at 1.905 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 230 "/Config memory/FPGA_PROM_MOSI")) + (pad 13 smd rect (at 3.175 -5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 95 FPGA_CFG_SCLK)) + (pad 8 smd rect (at 3.175 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 228 "/Config memory/FPGA_PROM_MISO")) + (pad 7 smd rect (at 1.905 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 229 "/Config memory/FPGA_PROM_SCLK")) + (pad 6 smd rect (at 0.635 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 ARM_FPGA_CFG_MOSI)) + (pad 5 smd rect (at -0.635 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 230 "/Config memory/FPGA_PROM_MOSI")) + (pad 4 smd rect (at -1.905 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 8 ARM_FPGA_CFG_SCLK)) + (pad 3 smd rect (at -3.175 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 93 FPGA_CFG_MISO)) + (pad 2 smd rect (at -4.445 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 5 ARM_FPGA_CFG_CS_N)) + (pad 1 smd rect (at -5.715 5.0292 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 231 "/Config memory/SPI_A_TRISTATE")) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 94.0562 -60.9934 90) - (path /57D84B22/58024043) + (module Cryptech_Alpha_Footprints:SO08 (layer F.Cu) (tedit 60BDDB3A) (tstamp 539EEDBF) + (at 33.1552 -51.028) + (path /57D84C13/5802402B) (attr smd) - (fp_text reference C53 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference IC1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value MT25QL128ABA1ESE (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy -2.032 -1.524) (xy -4.572 -1.524) (xy -4.572 -2.794) (xy -2.032 -2.794)) (layer F.Fab) (width 0.1)) + (fp_line (start 4.572 2.794) (end 4.572 -2.794) (layer F.Fab) (width 0.1)) + (fp_line (start -4.572 2.794) (end 4.572 2.794) (layer F.Fab) (width 0.1)) + (fp_line (start -4.572 -2.794) (end -4.572 2.794) (layer F.Fab) (width 0.1)) + (fp_line (start 4.572 -2.794) (end -4.572 -2.794) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 2 2) (thickness 0.2))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 147 KSM_PROM_MOSI)) + (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 148 KSM_PROM_SCLK)) + (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 168 "Net-(IC1-Pad3)")) + (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 146 KSM_PROM_MISO)) + (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 145 KSM_PROM_CS_N)) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 94.0562 -40.9956 90) - (path /57D84B22/58024035) + (module Cryptech_Alpha_Footprints:SO08 (layer F.Cu) (tedit 60BDDB3A) (tstamp 539EEDBF) + (at 45.5368 -25.2832) + (path /57D85260/58023F42) (attr smd) - (fp_text reference C54 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference IC3 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value MT25QL128ABA1ESE (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy -2.032 -1.524) (xy -4.572 -1.524) (xy -4.572 -2.794) (xy -2.032 -2.794)) (layer F.Fab) (width 0.1)) + (fp_line (start 4.572 2.794) (end 4.572 -2.794) (layer F.Fab) (width 0.1)) + (fp_line (start -4.572 2.794) (end 4.572 2.794) (layer F.Fab) (width 0.1)) + (fp_line (start -4.572 -2.794) (end -4.572 2.794) (layer F.Fab) (width 0.1)) + (fp_line (start 4.572 -2.794) (end -4.572 -2.794) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 2 2) (thickness 0.2))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 230 "/Config memory/FPGA_PROM_MOSI")) + (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 229 "/Config memory/FPGA_PROM_SCLK")) + (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 232 "/Config memory/FPGA_PROM_W_N")) + (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 228 "/Config memory/FPGA_PROM_MISO")) + (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 226 "/Config memory/FPGA_PROM_CS_N")) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 94.0562 -58.8772 270) - (path /57D84B22/58024044) + (module Cryptech_Alpha_Footprints:RCLAMP0502A (layer F.Cu) (tedit 60BDDAD0) (tstamp 539EEDBF) + (at 51.816 -11.0744) + (path /57D84CB3/58023FF2) (attr smd) - (fp_text reference C55 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference IC5 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value RCLAMP0502A.TCT (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start 0.254 -1.27) (end -0.762 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.762) (end 0.254 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.27) (end 0.762 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.27) (end 0.762 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.27) (end -0.762 1.27) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer F.Fab) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 222 "/User USB UART/D1_P")) + (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 144 FT_VREGIN)) + (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 221 "/User USB UART/D1_N")) + (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 233 "/User USB UART/USB_N")) + (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 234 "/User USB UART/USB_P")) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 78.105 -45.3644 90) - (path /57D84B22/5802403B) + (module Cryptech_Alpha_Footprints:RCLAMP0502A (layer F.Cu) (tedit 60BDDAD0) (tstamp 539EEDBF) + (at 69.1134 -11.0744) + (path /57D84E30/58023FBC) (attr smd) - (fp_text reference C56 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference IC6 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value RCLAMP0502A.TCT (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start 0.254 -1.27) (end -0.762 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -0.762) (end 0.254 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.27) (end 0.762 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 1.27) (end 0.762 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.27) (end -0.762 1.27) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer F.Fab) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 224 "/MGMT USB UART/DM_P")) + (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 137 FT_MGMT_VREGIN)) + (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 223 "/MGMT USB UART/DM_N")) + (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 235 "/MGMT USB UART/USB_MGMT_N")) + (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 236 "/MGMT USB UART/USB_MGMT_P")) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 94.0562 -52.9082 270) - (path /57D84B22/58024045) + (module Cryptech_Alpha_Footprints:QFN68 (layer B.Cu) (tedit 60BDDA1D) (tstamp 539EEDBF) + (at 25.9842 -57.4802) + (path /57D85A75/58023E29) (attr smd) - (fp_text reference C57 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference U16 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value EN5364QI (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 6.096 -4.572) (xy 4.826 -4.572) (xy 4.826 -3.81) (xy 6.096 -3.81)) (layer B.Fab) (width 0.1)) + (fp_line (start 6.096 4.572) (end -6.096 4.572) (layer B.Fab) (width 0.1)) + (fp_line (start 6.096 -4.572) (end 6.096 4.572) (layer B.Fab) (width 0.1)) + (fp_line (start -6.096 -4.572) (end 6.096 -4.572) (layer B.Fab) (width 0.1)) + (fp_line (start -6.096 4.572) (end -6.096 -4.572) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer B.Fab) + (effects (font (size 3 3) (thickness 0.2)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd oval (at 5.5 -3.5052 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 2 smd oval (at 5.5 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 3 smd oval (at 5.5 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 4 smd oval (at 5.5 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 5 smd oval (at 5.5 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 6 smd oval (at 5.5 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 7 smd oval (at 5.5 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 8 smd oval (at 5.5 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 9 smd oval (at 5.5 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 10 smd oval (at 5.5 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 11 smd oval (at 5.5 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 12 smd oval (at 5.5 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 13 smd oval (at 5.5 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (pad 14 smd oval (at 5.5 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 15 smd oval (at 5.5 3.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 16 smd oval (at 4.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 17 smd oval (at 4 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 18 smd oval (at 3.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 19 smd oval (at 3 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 20 smd oval (at 2.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 21 smd oval (at 2 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 22 smd oval (at 1.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at 1 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at 0.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 25 smd oval (at 0 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 26 smd oval (at -0.508 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 27 smd oval (at -1.016 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 28 smd oval (at -1.524 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 29 smd oval (at -2.0066 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 30 smd oval (at -2.5146 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 31 smd oval (at -3.0226 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 32 smd oval (at -3.5052 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 33 smd oval (at -4.0132 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 34 smd oval (at -4.5212 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 35 smd oval (at -5.5118 3.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 36 smd oval (at -5.5118 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 37 smd oval (at -5.5118 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 38 smd oval (at -5.5118 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 39 smd oval (at -5.5118 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 40 smd oval (at -5.5118 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 41 smd oval (at -5.5118 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 42 smd oval (at -5.5118 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 43 smd oval (at -5.5118 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 44 smd oval (at -5.5118 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 45 smd oval (at -5.5118 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 46 smd oval (at -5.5118 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 47 smd oval (at -5.5118 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 48 smd oval (at -5.5118 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 562 "Net-(U16-Pad48)")) + (pad 49 smd oval (at -5.5118 -3.5052) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 563 "Net-(U16-Pad49)")) + (pad 50 smd oval (at -4.5212 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 564 "Net-(U16-Pad50)")) + (pad 51 smd oval (at -4.0132 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 197 "Net-(R66-Pad1)")) + (pad 52 smd oval (at -3.5052 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 204 PWR_ENA_VCCINT)) + (pad 53 smd oval (at -3.0226 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 54 smd oval (at -2.5146 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 200 POK_VCCINT)) + (pad 55 smd oval (at -2.0066 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 56 smd oval (at -1.524 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 167 "Net-(C208-Pad2)")) + (pad 57 smd oval (at -1.016 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 565 "Net-(U16-Pad57)")) + (pad 58 smd oval (at -0.508 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 566 "Net-(U16-Pad58)")) + (pad 59 smd oval (at 0 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 165 "Net-(C207-Pad1)")) + (pad 60 smd oval (at 0.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 567 "Net-(U16-Pad60)")) + (pad 61 smd oval (at 1 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 568 "Net-(U16-Pad61)")) + (pad 62 smd oval (at 1.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 569 "Net-(U16-Pad62)")) + (pad 63 smd oval (at 2 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 198 "Net-(R67-Pad1)")) + (pad 64 smd oval (at 2.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 65 smd oval (at 3 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 66 smd oval (at 3.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 67 smd oval (at 4 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 68 smd oval (at 4.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad PAD69 smd oval (at -2.175 0.625 90) (size 5.35 2.35) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad PAD70 smd oval (at 3.55 -2.65 180) (size 2.5 1.3) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 72.8222 -40.8924 90) - (path /57D84B22/58024039) + (module Cryptech_Alpha_Footprints:QFN38 (layer B.Cu) (tedit 60BDD9B9) (tstamp 539EEDBF) + (at 35.4584 -76.5556 180) + (path /57D853B0/58023F0C) (attr smd) - (fp_text reference C58 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference U14 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value EN6347QI (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_poly (pts (xy 2.286 3.302) (xy 1.778 3.302) (xy 1.778 3.81) (xy 2.286 3.81)) (layer B.Fab) (width 0.1)) + (fp_line (start 2.286 3.81) (end -2.286 3.81) (layer B.Fab) (width 0.1)) + (fp_line (start 2.286 -3.81) (end 2.286 3.81) (layer B.Fab) (width 0.1)) + (fp_line (start -2.286 -3.81) (end 2.286 -3.81) (layer B.Fab) (width 0.1)) + (fp_line (start -2.286 3.81) (end -2.286 -3.81) (layer B.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (effects (font (size 2 2) (thickness 0.15)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 1 smd oval (at 1.27 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 2 smd oval (at 0.762 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 3 smd oval (at 0.254 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 4 smd oval (at -0.25 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 5 smd oval (at -0.75 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (pad 6 smd oval (at -1.25 3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (pad 7 smd oval (at -1.9 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (pad 8 smd oval (at -1.9 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (pad 9 smd oval (at -1.9 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (pad 10 smd oval (at -1.9 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (pad 11 smd oval (at -1.9 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (pad 12 smd oval (at -1.9 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 13 smd oval (at -1.9 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 14 smd oval (at -1.9 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 15 smd oval (at -1.9 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 16 smd oval (at -1.9 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 17 smd oval (at -1.9 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 18 smd oval (at -1.9 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 19 smd oval (at -1.9 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 20 smd oval (at -1.25 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 21 smd oval (at -0.75 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 22 smd oval (at -0.25 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at 0.254 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at 0.762 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 25 smd oval (at 1.27 -3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 26 smd oval (at 1.905 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 192 "Net-(R52-Pad1)")) + (pad 27 smd oval (at 1.905 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 203 PWR_ENA_VCCAUX)) + (pad 28 smd oval (at 1.905 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 199 POK_VCCAUX)) + (pad 29 smd oval (at 1.905 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 193 "Net-(R53-Pad2)")) + (pad 30 smd oval (at 1.905 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 159 "Net-(C115-Pad1)")) + (pad 31 smd oval (at 1.905 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 162 "Net-(C117-Pad2)")) + (pad 32 smd oval (at 1.905 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 33 smd oval (at 1.905 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 34 smd oval (at 1.905 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at 1.905 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 36 smd oval (at 1.905 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 37 smd oval (at 1.905 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 38 smd oval (at 1.905 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad PAD39 smd oval (at 0 -1.26 180) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 72.8472 -38.6826 270) - (path /57D84B22/5802403A) + (module Cryptech_Alpha_Footprints:QFN38 (layer B.Cu) (tedit 60BDD9B9) (tstamp 539EEDBF) + (at 10.8458 -41.0972) + (path /57D853B0/58023F0B) (attr smd) - (fp_text reference C59 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference U15 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value EN6347QI (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_poly (pts (xy 2.286 3.302) (xy 1.778 3.302) (xy 1.778 3.81) (xy 2.286 3.81)) (layer B.Fab) (width 0.1)) + (fp_line (start 2.286 3.81) (end -2.286 3.81) (layer B.Fab) (width 0.1)) + (fp_line (start 2.286 -3.81) (end 2.286 3.81) (layer B.Fab) (width 0.1)) + (fp_line (start -2.286 -3.81) (end 2.286 -3.81) (layer B.Fab) (width 0.1)) + (fp_line (start -2.286 3.81) (end -2.286 -3.81) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 -270) (layer B.Fab) + (effects (font (size 2 2) (thickness 0.15)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 1 smd oval (at 1.27 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 2 smd oval (at 0.762 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 3 smd oval (at 0.254 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 4 smd oval (at -0.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 5 smd oval (at -0.75 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (pad 6 smd oval (at -1.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (pad 7 smd oval (at -1.9 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (pad 8 smd oval (at -1.9 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (pad 9 smd oval (at -1.9 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (pad 10 smd oval (at -1.9 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (pad 11 smd oval (at -1.9 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (pad 12 smd oval (at -1.9 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 13 smd oval (at -1.9 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 14 smd oval (at -1.9 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 15 smd oval (at -1.9 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 16 smd oval (at -1.9 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 17 smd oval (at -1.9 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 18 smd oval (at -1.9 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 19 smd oval (at -1.9 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 20 smd oval (at -1.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 21 smd oval (at -0.75 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 22 smd oval (at -0.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at 0.254 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at 0.762 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 25 smd oval (at 1.27 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 26 smd oval (at 1.905 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 194 "Net-(R54-Pad1)")) + (pad 27 smd oval (at 1.905 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 205 PWR_ENA_VCCO)) + (pad 28 smd oval (at 1.905 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 201 POK_VCCO)) + (pad 29 smd oval (at 1.905 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 195 "Net-(R55-Pad2)")) + (pad 30 smd oval (at 1.905 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 160 "Net-(C116-Pad1)")) + (pad 31 smd oval (at 1.905 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 164 "Net-(C118-Pad2)")) + (pad 32 smd oval (at 1.905 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 33 smd oval (at 1.905 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 34 smd oval (at 1.905 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at 1.905 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 36 smd oval (at 1.905 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 37 smd oval (at 1.905 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 38 smd oval (at 1.905 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad PAD39 smd oval (at 0 -1.26) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 72.8472 -60.9568 90) - (path /57D84B22/5802403C) + (module Cryptech_Alpha_Footprints:PLS-8 (layer F.Cu) (tedit 60BDD914) (tstamp 539EEDBF) + (at 40.3 -1.3) + (path /57D85134/58023F68) (attr smd) - (fp_text reference C60 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference SV1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start 10.16 -1.27) (end -10.16 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 1.27) (end 10.16 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -8.89 1.27) (end 10.16 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -10.16 0) (end -8.89 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -10.16 -1.27) (end -10.16 0) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 3 GND)) + (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 258 "/Config interface/FPGA_JTAG_TCK")) + (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 257 "/Config interface/FPGA_JTAG_TMS")) + (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 256 "/Config interface/FPGA_JTAG_TDI")) + (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 265 "/Config interface/FPGA_JTAG_TDO")) + (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 3 GND)) + (model wrlshp/PLS-8.wrl + (offset (xyz 8.889999866485596 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/A962434E-CFE5.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 88.7222 -58.666 90) - (path /57D84B22/5802403E) + (module Cryptech_Alpha_Footprints:PLS-6 (layer F.Cu) (tedit 60BDD8EC) (tstamp 539EEDBF) + (at 22.78379 -20.4216) + (path /57D84936/58024085) (attr smd) - (fp_text reference C61 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference J1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value "STM32 SWD connector" (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start 7.62 -1.27) (end -7.62 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 7.62 1.27) (end 7.62 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -6.35 1.27) (end 7.62 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -7.62 0) (end -6.35 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -7.62 -1.27) (end -7.62 0) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 268 "Net-(J1-Pad6)")) + (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 214 "/STM32 configuration/NRST")) + (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 237 "/STM32 configuration/SWDIO")) + (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 238 "/STM32 configuration/SWDCLK")) + (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 210 VCCO_3V3)) + (model wrlshp/pin_header_a-sl254-ea-g06mp1.wrl + (offset (xyz 0.006349999904632569 0.08635999870300293 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 90 360 360)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/670BFB14-85C2.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 72.8472 -52.6288 270) - (path /57D84B22/5802403D) + (module Cryptech_Alpha_Footprints:PLS-3 (layer F.Cu) (tedit 60BDD856) (tstamp 539EEDBF) + (at 88.67933 1.5) + (path /57D84FAD/58023F9B) (attr smd) - (fp_text reference C62 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference JP4 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value "Standard 3-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115). Molex polarized connector foot print use with SKU : PRT-08232 with associated crimp pins and housings." (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start 3.81 -1.27) (end -3.81 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 3.81 1.27) (end 3.81 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 1.27) (end 3.81 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -3.81 0) (end -2.54 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -3.81 -1.27) (end -3.81 0) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 1 3V3_BATT)) + (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 210 VCCO_3V3)) + (model wrlshp/pin_header_aw_108_03-t.wrl + (offset (xyz 0.05003799924850464 0.05003799924850464 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 90 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/836C6F64-A2E5.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 88.7222 -41.148 270) - (path /57D84B22/5802403F) + (module Cryptech_Alpha_Footprints:PLS-2 (layer F.Cu) (tedit 60BDD824) (tstamp 5F27EE3C) + (at 75 -19.8 180) + (path /57D84FAD/5F27A891) (attr smd) - (fp_text reference C63 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference JP3 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 1.27) (end 2.54 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 1.27) (end 2.54 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 0) (end -1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 -1.27) (end -2.54 0) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 thru_hole circle (at 1.27 0 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 594 ICE40_JUMPER)) + (pad 1 thru_hole rect (at -1.27 0 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/User Library-Header1x2.wrl" + (offset (xyz 5.675121914768218 11.80693582267761 -6.799998997874261)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/3416A7AC-A52A.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 72.8472 -58.5978 270) - (path /57D84B22/58024036) + (module Cryptech_Alpha_Footprints:PLS-2 (layer F.Cu) (tedit 60BDD824) (tstamp 539EEDBF) + (at 64.6468 -91.7448) + (path /57D84708/580240BB) (attr smd) - (fp_text reference C64 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference JP2 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 1.27) (end 2.54 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 1.27) (end 2.54 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 0) (end -1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 -1.27) (end -2.54 0) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 169 "Net-(JP2-Pad2)")) + (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 243 /Power/15V_LDO_ENABLE)) + (model "wrlshp/User Library-Header1x2.wrl" + (offset (xyz 5.675121914768218 11.80693582267761 -6.799998997874261)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/3416A7AC-A52A.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 88.7222 -55.5458 90) - (path /57D84B22/58024040) + (module Cryptech_Alpha_Footprints:PLD-6 (layer F.Cu) (tedit 60BDD7F2) (tstamp 539EEDBF) + (at 41.04639 -12.5222 90) + (path /57D84CB3/58023FEF) (attr smd) - (fp_text reference C65 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference J2 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value "2x3 .1\" header" (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -2.54 -2.54) (end -2.54 3.81) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -3.81) (end -2.54 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 -3.81) (end -1.27 -3.81) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 3.81) (end 2.54 -3.81) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 3.81) (end 2.54 3.81) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 1 thru_hole rect (at -1.27 -2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 thru_hole circle (at 1.27 -2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 144 FT_VREGIN)) + (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 234 "/User USB UART/USB_P")) + (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 233 "/User USB UART/USB_N")) + (pad 5 thru_hole circle (at -1.27 2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 239 "/User USB UART/FT_RXD1")) + (pad 6 thru_hole circle (at 1.27 2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 240 "/User USB UART/FT_TXD1")) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 90 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/B3089A96-FA19.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 72.8472 -45.5422 270) - (path /57D84B22/58024037) + (module Cryptech_Alpha_Footprints:PLD-6 (layer F.Cu) (tedit 60BDD7F2) (tstamp 539EEDBF) + (at 74.90459 -12.5222 90) + (path /57D84E30/58023FB9) (attr smd) - (fp_text reference C66 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference J3 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value "2x3 .1\" header" (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -2.54 -2.54) (end -2.54 3.81) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -3.81) (end -2.54 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 -3.81) (end -1.27 -3.81) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 3.81) (end 2.54 -3.81) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 3.81) (end 2.54 3.81) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 1 thru_hole rect (at -1.27 -2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 thru_hole circle (at 1.27 -2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 137 FT_MGMT_VREGIN)) + (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 236 "/MGMT USB UART/USB_MGMT_P")) + (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 235 "/MGMT USB UART/USB_MGMT_N")) + (pad 5 thru_hole circle (at -1.27 2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 241 "/MGMT USB UART/FT_MGMT_RXD1")) + (pad 6 thru_hole circle (at 1.27 2.54) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 242 "/MGMT USB UART/FT_MGMT_TXD1")) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 90 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/B3089A96-FA19.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 88.7222 -45.4874 90) - (path /57D84B22/58024041) + (module Cryptech_Alpha_Footprints:PLD-6 (layer F.Cu) (tedit 60BDD7F2) (tstamp 539EEDBF) + (at 18.25 -29.475) + (path /57D85260/58023F3C) (attr smd) - (fp_text reference C67 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference JP7 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -2.54 -2.54) (end -2.54 3.81) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -3.81) (end -2.54 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 -3.81) (end -1.27 -3.81) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 3.81) (end 2.54 -3.81) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 3.81) (end 2.54 3.81) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 91 FPGA_CFG_CTRL_ARM_ENA)) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 231 "/Config memory/SPI_A_TRISTATE")) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 92 FPGA_CFG_CTRL_FPGA_DIS)) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 227 "/Config memory/SPI_B_TRISTATE")) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 232 "/Config memory/FPGA_PROM_W_N")) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 90 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/B3089A96-FA19.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 72.8472 -55.6514 270) - (path /57D84B22/58024038) + (module Cryptech_Alpha_Footprints:PLD-16 (layer F.Cu) (tedit 60BDD74B) (tstamp 539EEDBF) + (at 59.58299 -97.7646) + (path /57D854CB/58023EF9) (attr smd) - (fp_text reference C68 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference SV2 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -10.16 -2.54) (end -10.16 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start -10.16 2.54) (end 10.16 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 2.54) (end 10.16 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 -1.27) (end 8.89 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 8.89 -2.54) (end -10.16 -2.54) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 210 VCCO_3V3)) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 210 VCCO_3V3)) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 210 VCCO_3V3)) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 3 GND)) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 99 FPGA_GPIO_A_0)) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 100 FPGA_GPIO_A_1)) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 101 FPGA_GPIO_A_2)) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 102 FPGA_GPIO_A_3)) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 3 GND)) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 3 GND)) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 103 FPGA_GPIO_A_4)) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 104 FPGA_GPIO_A_5)) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 105 FPGA_GPIO_A_6)) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 106 FPGA_GPIO_A_7)) + (model wrlshp/pin_header_awl254-dg-g16d.wrl + (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 90 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/B280C847-2543.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 39.1 -51.675) - (path /57D84C13/58024029) + (module Cryptech_Alpha_Footprints:PLD-16 (layer F.Cu) (tedit 60BDD74B) (tstamp 539EEDBF) + (at 36.79919 -97.7646) + (path /57D854CB/58023EF4) (attr smd) - (fp_text reference C69 (at 0 0) (layer F.SilkS) hide + (fp_text reference SV3 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -10.16 -2.54) (end -10.16 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start -10.16 2.54) (end 10.16 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 2.54) (end 10.16 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 -1.27) (end 8.89 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 8.89 -2.54) (end -10.16 -2.54) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 210 VCCO_3V3)) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 210 VCCO_3V3)) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 210 VCCO_3V3)) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 3 GND)) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 107 FPGA_GPIO_B_0)) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 108 FPGA_GPIO_B_1)) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 109 FPGA_GPIO_B_2)) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 110 FPGA_GPIO_B_3)) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 3 GND)) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 3 GND)) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 111 FPGA_GPIO_B_4)) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 112 FPGA_GPIO_B_5)) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 113 FPGA_GPIO_B_6)) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 114 FPGA_GPIO_B_7)) + (model wrlshp/pin_header_awl254-dg-g16d.wrl + (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 90 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/B280C847-2543.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 22.1 -47.875 270) - (path /57D84C55/5802401F) + (module Cryptech_Alpha_Footprints:NDY (layer B.Cu) (tedit 60BDD618) (tstamp 539EEDBF) + (at 22.2758 -78.2828) + (path /57D84708/580240B7) (attr smd) - (fp_text reference C70 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference U1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 5.1pF (at 0 0 90) (layer Cmts.User) + (fp_text value LMZ13608TZ/NOPB (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 2.54 -7.62) (xy -2.54 -7.62) (xy -2.54 -5.08) (xy 2.54 -5.08)) (layer B.Fab) (width 0.1)) + (fp_line (start 2.54 -7.62) (end 2.54 7.62) (layer B.Fab) (width 0.1)) + (fp_line (start -16.51 -7.62) (end 2.54 -7.62) (layer B.Fab) (width 0.1)) + (fp_line (start -16.51 7.62) (end -16.51 -7.62) (layer B.Fab) (width 0.1)) + (fp_line (start 2.54 7.62) (end -16.51 7.62) (layer B.Fab) (width 0.1)) + (fp_text user %R (at -7.62 0) (layer B.Fab) + (effects (font (size 5 5) (thickness 0.5)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 202 PWR_18V)) + (pad 2 smd rect (at 0 -5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 202 PWR_18V)) + (pad 3 smd rect (at 0 -3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 153 "Net-(C70-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 4 smd rect (at 0 -2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 189 "Net-(R3-Pad2)")) + (pad 5 smd rect (at 0 -1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 6 smd rect (at 0 0 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 7 smd rect (at 0 1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 190 "Net-(R8-Pad1)")) + (pad TP1 smd rect (at -9.525 0 90) (size 9.144 13.3858) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 8 smd rect (at 0 2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 149 "Net-(C5-Pad1)")) + (pad 9 smd rect (at 0 3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 270 "Net-(U1-Pad9)")) + (pad 10 smd rect (at 0 5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (pad 11 smd rect (at 0 6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 19.3 -40.9 90) - (path /57D84C55/58024020) + (module Cryptech_Alpha_Footprints:LQFP-48 (layer F.Cu) (tedit 60BDD4EE) (tstamp 539EEDBF) + (at 13.8186 -9.636 90) + (path /57D84CB3/58024000) (attr smd) - (fp_text reference C71 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference U8 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 5.1pF (at 0 0 90) (layer Cmts.User) + (fp_text value FT232HL-REEL (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_poly (pts (xy -3.048 5.08) (xy -5.08 5.08) (xy -5.08 3.048) (xy -3.048 3.048)) (layer F.Fab) (width 0.1)) + (fp_line (start -5.08 5.08) (end -5.08 -5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 5.08 5.08) (end -5.08 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 5.08 -5.08) (end 5.08 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start -5.08 -5.08) (end 5.08 -5.08) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 4 4) (thickness 0.2))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -2.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 155 "Net-(C75-Pad2)")) + (pad 2 smd rect (at -2.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 156 "Net-(C78-Pad2)")) + (pad 3 smd rect (at -1.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 142 FT_VPHY)) + (pad 4 smd rect (at -1.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 154 "Net-(C71-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 12.37202 -7.06602 180) - (path /57D84CB3/58023FE5) - (attr smd) - (fp_text reference C73 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 5 smd rect (at -0.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 249 "/User USB UART/FT_REF")) + (pad 6 smd rect (at -0.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 233 "/User USB UART/USB_N")) + (pad 7 smd rect (at 0.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 234 "/User USB UART/USB_P")) + (pad 8 smd rect (at 0.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 143 FT_VPLL)) + (pad 9 smd rect (at 1.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 10 smd rect (at 1.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 11 smd rect (at 2.25 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 12 smd rect (at 2.75 4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (pad 13 smd rect (at 4.05 2.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 240 "/User USB UART/FT_TXD1")) + (pad 14 smd rect (at 4.05 2.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 239 "/User USB UART/FT_RXD1")) + (pad 15 smd rect (at 4.05 1.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 138 FT_RTS)) + (pad 16 smd rect (at 4.05 1.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 127 FT_CTS)) + (pad 17 smd rect (at 4.05 0.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 128 FT_DTR)) + (pad 18 smd rect (at 4.05 0.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 316 "Net-(U8-Pad18)")) + (pad 19 smd rect (at 4.05 -0.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 317 "Net-(U8-Pad19)")) + (pad 20 smd rect (at 4.05 -0.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 318 "Net-(U8-Pad20)")) + (pad 21 smd rect (at 4.05 -1.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 319 "Net-(U8-Pad21)")) + (pad 22 smd rect (at 4.05 -1.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 23 smd rect (at 4.05 -2.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 24 smd rect (at 4.05 -2.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (pad 25 smd rect (at 2.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 320 "Net-(U8-Pad25)")) + (pad 26 smd rect (at 2.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 321 "Net-(U8-Pad26)")) + (pad 27 smd rect (at 1.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 322 "Net-(U8-Pad27)")) + (pad 28 smd rect (at 1.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 323 "Net-(U8-Pad28)")) + (pad 29 smd rect (at 0.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 324 "Net-(U8-Pad29)")) + (pad 30 smd rect (at 0.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 325 "Net-(U8-Pad30)")) + (pad 31 smd rect (at -0.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 326 "Net-(U8-Pad31)")) + (pad 32 smd rect (at -0.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 327 "Net-(U8-Pad32)")) + (pad 33 smd rect (at -1.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 328 "Net-(U8-Pad33)")) + (pad 34 smd rect (at -1.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 250 "/User USB UART/FT_RESET")) + (pad 35 smd rect (at -2.25 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 36 smd rect (at -2.75 -4.05 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 37 smd rect (at -4.05 -2.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 218 "/User USB UART/FT_VCCA")) + (pad 38 smd rect (at -4.05 -2.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 217 "/User USB UART/FT_VCCORE")) + (pad 39 smd rect (at -4.05 -1.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (pad 40 smd rect (at -4.05 -1.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) (net 144 FT_VREGIN)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 41 smd rect (at -4.05 -0.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (pad 42 smd rect (at -4.05 -0.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 43 smd rect (at -4.05 0.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 329 "Net-(U8-Pad43)")) + (pad 44 smd rect (at -4.05 0.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 330 "Net-(U8-Pad44)")) + (pad 45 smd rect (at -4.05 1.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 331 "Net-(U8-Pad45)")) + (pad 46 smd rect (at -4.05 1.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (pad 47 smd rect (at -4.05 2.25 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 48 smd rect (at -4.05 2.75 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model wrlshp/SW3dPS-LQFP48.wrl (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/6B6B27F8-B7AC.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 10.7198 -3.1844 270) - (path /57D84CB3/58023FEA) + (module Cryptech_Alpha_Footprints:LQFP-48 (layer F.Cu) (tedit 60BDD4EE) (tstamp 539EEDBF) + (at 86.3854 -17.8496) + (path /57D84E30/58023FCA) (attr smd) - (fp_text reference C74 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference U9 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value FT232HL-REEL (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy -3.048 5.08) (xy -5.08 5.08) (xy -5.08 3.048) (xy -3.048 3.048)) (layer F.Fab) (width 0.1)) + (fp_line (start -5.08 5.08) (end -5.08 -5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 5.08 5.08) (end -5.08 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 5.08 -5.08) (end 5.08 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start -5.08 -5.08) (end 5.08 -5.08) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 4 4) (thickness 0.2))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 217 "/User USB UART/FT_VCCORE")) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 157 "Net-(C90-Pad2)")) + (pad 2 smd rect (at -2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 158 "Net-(C93-Pad2)")) + (pad 3 smd rect (at -1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 135 FT_MGMT_VPHY)) + (pad 4 smd rect (at -1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (pad 5 smd rect (at -0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 251 "/MGMT USB UART/FT_REF1")) + (pad 6 smd rect (at -0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 235 "/MGMT USB UART/USB_MGMT_N")) + (pad 7 smd rect (at 0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 236 "/MGMT USB UART/USB_MGMT_P")) + (pad 8 smd rect (at 0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 136 FT_MGMT_VPLL)) + (pad 9 smd rect (at 1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 10 smd rect (at 1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 11 smd rect (at 2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 12 smd rect (at 2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (pad 13 smd rect (at 4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 242 "/MGMT USB UART/FT_MGMT_TXD1")) + (pad 14 smd rect (at 4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 241 "/MGMT USB UART/FT_MGMT_RXD1")) + (pad 15 smd rect (at 4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 131 FT_MGMT_RTS)) + (pad 16 smd rect (at 4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 129 FT_MGMT_CTS)) + (pad 17 smd rect (at 4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 130 FT_MGMT_DTR)) + (pad 18 smd rect (at 4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 332 "Net-(U9-Pad18)")) + (pad 19 smd rect (at 4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 333 "Net-(U9-Pad19)")) + (pad 20 smd rect (at 4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 334 "Net-(U9-Pad20)")) + (pad 21 smd rect (at 4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 335 "Net-(U9-Pad21)")) + (pad 22 smd rect (at 4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 23 smd rect (at 4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 24 smd rect (at 4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (pad 25 smd rect (at 2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 336 "Net-(U9-Pad25)")) + (pad 26 smd rect (at 2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 337 "Net-(U9-Pad26)")) + (pad 27 smd rect (at 1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 338 "Net-(U9-Pad27)")) + (pad 28 smd rect (at 1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 339 "Net-(U9-Pad28)")) + (pad 29 smd rect (at 0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 340 "Net-(U9-Pad29)")) + (pad 30 smd rect (at 0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 341 "Net-(U9-Pad30)")) + (pad 31 smd rect (at -0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 342 "Net-(U9-Pad31)")) + (pad 32 smd rect (at -0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 343 "Net-(U9-Pad32)")) + (pad 33 smd rect (at -1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 344 "Net-(U9-Pad33)")) + (pad 34 smd rect (at -1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 252 "/MGMT USB UART/FT_RESET1")) + (pad 35 smd rect (at -2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 36 smd rect (at -2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 37 smd rect (at -4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 220 "/MGMT USB UART/FT_VCCA1")) + (pad 38 smd rect (at -4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 219 "/MGMT USB UART/FT_VCCORE1")) + (pad 39 smd rect (at -4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (pad 40 smd rect (at -4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 137 FT_MGMT_VREGIN)) + (pad 41 smd rect (at -4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 42 smd rect (at -4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 43 smd rect (at -4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 345 "Net-(U9-Pad43)")) + (pad 44 smd rect (at -4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 346 "Net-(U9-Pad44)")) + (pad 45 smd rect (at -4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 347 "Net-(U9-Pad45)")) + (pad 46 smd rect (at -4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (pad 47 smd rect (at -4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 48 smd rect (at -4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (model wrlshp/SW3dPS-LQFP48.wrl (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/6B6B27F8-B7AC.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 19.8892 -4.8608 90) - (path /57D84CB3/58023FE7) + (module Cryptech_Alpha_Footprints:L_1206 (layer B.Cu) (tedit 60BDD442) (tstamp 539EEDBF) + (at 41.4528 -84.2772 270) + (path /57D853B0/58023F06) (attr smd) - (fp_text reference C75 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference FB5 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 5.1pF (at 0 0 90) (layer Cmts.User) + (fp_text value BLM31PG330SN1 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.016 -2.286) (end -1.016 2.286) (layer B.Fab) (width 0.1)) + (fp_line (start 1.016 -2.286) (end -1.016 -2.286) (layer B.Fab) (width 0.1)) + (fp_line (start 1.016 2.286) (end 1.016 -2.286) (layer B.Fab) (width 0.1)) + (fp_line (start -1.016 2.286) (end 1.016 2.286) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 155 "Net-(C75-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 smd rect (at 0 -1.4 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad 1 smd rect (at 0 1.4 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0.05003799924850464 0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 270)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/76148CD0-6DD3.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 9.2974 -3.1844 270) - (path /57D84CB3/58023FEB) + (module Cryptech_Alpha_Footprints:L_1206 (layer B.Cu) (tedit 60BDD442) (tstamp 539EEDBF) + (at 7.7978 -33.147 270) + (path /57D853B0/58023F14) (attr smd) - (fp_text reference C76 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference FB6 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value BLM31PG330SN1 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.016 -2.286) (end -1.016 2.286) (layer B.Fab) (width 0.1)) + (fp_line (start 1.016 -2.286) (end -1.016 -2.286) (layer B.Fab) (width 0.1)) + (fp_line (start 1.016 2.286) (end 1.016 -2.286) (layer B.Fab) (width 0.1)) + (fp_line (start -1.016 2.286) (end 1.016 2.286) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 218 "/User USB UART/FT_VCCA")) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 smd rect (at 0 -1.4 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 1 smd rect (at 0 1.4 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0.05003799924850464 0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 270)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/76148CD0-6DD3.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 19.8892 -7.1976 270) - (path /57D84CB3/58023FE8) + (module Cryptech_Alpha_Footprints:L_1206 (layer B.Cu) (tedit 60BDD442) (tstamp 539EEDBF) + (at 39.624 -58.2168) + (path /57D85A75/58023E22) (attr smd) - (fp_text reference C78 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference FB7 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 5.1pF (at 0 0 90) (layer Cmts.User) + (fp_text value BLM31PG330SN1 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.016 -2.286) (end -1.016 2.286) (layer B.Fab) (width 0.1)) + (fp_line (start 1.016 -2.286) (end -1.016 -2.286) (layer B.Fab) (width 0.1)) + (fp_line (start 1.016 2.286) (end 1.016 -2.286) (layer B.Fab) (width 0.1)) + (fp_line (start -1.016 2.286) (end 1.016 2.286) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 -90) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 156 "Net-(C78-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 smd rect (at 0 -1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 1 smd rect (at 0 1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0.05003799924850464 0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 270)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/76148CD0-6DD3.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 22.325 -10.025 90) - (path /57D84CB3/58023FFD) + (module Cryptech_Alpha_Footprints:L_0603 (layer F.Cu) (tedit 60BDD397) (tstamp 539EEDBF) + (at 27.3512 -15.7226) + (path /57D84CB3/58023FF4) (attr smd) - (fp_text reference C79 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference FB1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value FBMH1608HL601-T (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) (net 142 FT_VPHY)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/AF13F747-700F.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 19.8892 -10.7282 90) - (path /57D84CB3/58023FFB) + (module Cryptech_Alpha_Footprints:L_0603 (layer F.Cu) (tedit 60BDD397) (tstamp 539EEDBF) + (at 20.7528 -14.9192 90) + (path /57D84CB3/58023FF6) (attr smd) - (fp_text reference C81 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference FB2 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value FBMH1608HL601-T (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.85 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) (net 143 FT_VPLL)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (pad 1 smd rect (at 0 -0.85 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/AF13F747-700F.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 12.5486 -3.5654) - (path /57D84CB3/58023FFE) + (module Cryptech_Alpha_Footprints:L_0603 (layer F.Cu) (tedit 60BDD397) (tstamp 539EEDBF) + (at 93.218 -10.9662) + (path /57D84E30/58023FBE) (attr smd) - (fp_text reference C83 (at 0 0) (layer F.SilkS) hide + (fp_text reference FB3 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value FBMH1608HL601-T (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 135 FT_MGMT_VPHY)) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/AF13F747-700F.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 16.0792 -3.5908) - (path /57D84CB3/58023FF9) + (module Cryptech_Alpha_Footprints:L_0603 (layer F.Cu) (tedit 60BDD397) (tstamp 539EEDBF) + (at 91.186 -10.9662) + (path /57D84E30/58023FC0) (attr smd) - (fp_text reference C84 (at 0 0) (layer F.SilkS) hide + (fp_text reference FB4 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value FBMH1608HL601-T (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -0.762 1.524) (end -0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 1.524) (end -0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 0.762 -1.524) (end 0.762 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -0.762 -1.524) (end 0.762 -1.524) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.5 0.5) (thickness 0.05))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 136 FT_MGMT_VPLL)) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" (at (xyz 0 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 360 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/AF13F747-700F.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 19.8892 -12.8364 270) - (path /57D84CB3/58023FF8) + (module Cryptech_Alpha_Footprints:HDR1X10 (layer F.Cu) (tedit 60BDD308) (tstamp 539EEDBF) + (at 31.5 6) + (path /57D84FAD/58023F9D) (attr smd) - (fp_text reference C85 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference JP5 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value PLS-10 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start 24.13 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 24.13 1.27) (end 24.13 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 0 1.27) (end 24.13 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 0) (end 0 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -1.27) (end -1.27 0) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 11.43 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 595 ICE40_GPIO_1)) + (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 596 ICE40_GPIO_7)) + (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 597 ICE40_GPIO_6)) + (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 598 ICE40_GPIO_5)) + (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 599 ICE40_GPIO_4)) + (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 600 ICE40_GPIO_3)) + (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 601 ICE40_GPIO_2)) + (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 602 ICE40_GPIO_0)) + (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 1 3V3_BATT)) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 11.5326 -15.7828) - (path /57D84CB3/58023FF7) + (module Cryptech_Alpha_Footprints:CRYSTAL_3.2X2.5 (layer F.Cu) (tedit 60BDD26D) (tstamp 539EEDBF) + (at 82.525 -8.8) + (path /57D84E30/58023FB6) (attr smd) - (fp_text reference C86 (at 0 0) (layer F.SilkS) hide + (fp_text reference Y2 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value ABM8G-12.000MHZ-4Y-T3 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 2.286 -0.254) (xy 0.508 -0.254) (xy 0.508 -1.778) (xy 2.286 -1.778)) (layer F.Fab) (width 0.1)) + (fp_line (start -2.286 1.778) (end -2.286 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 2.286 1.778) (end -2.286 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 2.286 -1.778) (end 2.286 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -2.286 -1.778) (end 2.286 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0.762) (layer F.Fab) + (effects (font (size 1.2 1.2) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 141 FT_VCC3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 4 smd rect (at 1.1176 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 3 smd rect (at -1.0922 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 157 "Net-(C90-Pad2)")) + (pad 2 smd rect (at -1.0922 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 1 smd rect (at 1.1176 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 158 "Net-(C93-Pad2)")) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 82.50838 -18.33486 270) - (path /57D84E30/58023FAF) + (module Cryptech_Alpha_Footprints:CRYSTAL_3.2X2.5 (layer F.Cu) (tedit 60BDD26D) (tstamp 539EEDBF) + (at 23.075 -5.5 90) + (path /57D84CB3/58023FEC) (attr smd) - (fp_text reference C88 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference Y1 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value ABM8G-12.000MHZ-4Y-T3 (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_poly (pts (xy 2.286 -0.254) (xy 0.508 -0.254) (xy 0.508 -1.778) (xy 2.286 -1.778)) (layer F.Fab) (width 0.1)) + (fp_line (start -2.286 1.778) (end -2.286 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 2.286 1.778) (end -2.286 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 2.286 -1.778) (end 2.286 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -2.286 -1.778) (end 2.286 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0.762 90) (layer F.Fab) + (effects (font (size 1.2 1.2) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 137 FT_MGMT_VREGIN)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 4 smd rect (at 1.1176 0.8636 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 3 smd rect (at -1.0922 0.8636 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 155 "Net-(C75-Pad2)")) + (pad 2 smd rect (at -1.0922 -0.8382 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 1 smd rect (at 1.1176 -0.8382 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 156 "Net-(C78-Pad2)")) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 79.9592 -20.8976 180) - (path /57D84E30/58023FB4) + (module Cryptech_Alpha_Footprints:CRYSTAL_3.2X2.5 (layer B.Cu) (tedit 60BDD26D) (tstamp 539EEDBF) + (at 28.3 -34.975) + (path /57D84936/58024088) (attr smd) - (fp_text reference C89 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference Q3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value ABM8G-25.000MHZ-4Y-T3 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 2.286 0.254) (xy 0.508 0.254) (xy 0.508 1.778) (xy 2.286 1.778)) (layer B.Fab) (width 0.1)) + (fp_line (start -2.286 -1.778) (end -2.286 1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 2.286 -1.778) (end -2.286 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 2.286 1.778) (end 2.286 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start -2.286 1.778) (end 2.286 1.778) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 -0.762) (layer B.Fab) + (effects (font (size 1.2 1.2) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 219 "/MGMT USB UART/FT_VCCORE1")) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 4 smd rect (at 1.1176 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) + (pad 3 smd rect (at -1.0922 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 213 "/STM32 configuration/OSC_OUT")) + (pad 2 smd rect (at -1.0922 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at 1.1176 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 152 "Net-(C17-Pad2)")) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 81.8 -11.825) - (path /57D84E30/58023FB1) + (module Cryptech_Alpha_Footprints:C_D (layer B.Cu) (tedit 60BDD1BE) (tstamp 539EEDBF) + (at 10.4648 -54.5846) + (path /57D84708/580240B3) (attr smd) - (fp_text reference C90 (at 0 0) (layer F.SilkS) hide + (fp_text reference C9 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 5.1pF (at 0 0) (layer Cmts.User) + (fp_text value 330uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 4.826 -1.778) (xy 4.318 -1.778) (xy 4.318 1.778) (xy 4.826 1.778)) (layer B.Fab) (width 0.1)) + (fp_line (start 4.064 2.54) (end 5.08 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 4.572 2.032) (end 4.572 3.048) (layer B.Fab) (width 0.1)) + (fp_line (start -4.826 -1.778) (end -4.826 1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 4.826 -1.778) (end -4.826 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 4.826 1.778) (end 4.826 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start -4.826 1.778) (end 4.826 1.778) (layer B.Fab) (width 0.1)) + (fp_text user %R (at -0.254 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 157 "Net-(C90-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (model wrlshp/SW3dPS-cap_d.wrl + (offset (xyz -0.05003799924850464 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/5917D381-109F.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 79.925 -22.15 180) - (path /57D84E30/58023FB5) + (module Cryptech_Alpha_Footprints:C_D (layer B.Cu) (tedit 60BDD1BE) (tstamp 539EEDBF) + (at 10.4648 -61.0616) + (path /57D84708/580240B2) (attr smd) - (fp_text reference C91 (at 0 0) (layer F.SilkS) hide + (fp_text reference C10 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value 330uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 4.826 -1.778) (xy 4.318 -1.778) (xy 4.318 1.778) (xy 4.826 1.778)) (layer B.Fab) (width 0.1)) + (fp_line (start 4.064 2.54) (end 5.08 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 4.572 2.032) (end 4.572 3.048) (layer B.Fab) (width 0.1)) + (fp_line (start -4.826 -1.778) (end -4.826 1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 4.826 -1.778) (end -4.826 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start 4.826 1.778) (end 4.826 -1.778) (layer B.Fab) (width 0.1)) + (fp_line (start -4.826 1.778) (end 4.826 1.778) (layer B.Fab) (width 0.1)) + (fp_text user %R (at -0.254 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 220 "/MGMT USB UART/FT_VCCA1")) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (model wrlshp/SW3dPS-cap_d.wrl + (offset (xyz -0.05003799924850464 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/5917D381-109F.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 84.0994 -11.8298 180) - (path /57D84E30/58023FB2) + (module Cryptech_Alpha_Footprints:C_D (layer F.Cu) (tedit 60BDD1BE) (tstamp 539EEDBF) + (at 79.7052 -71.501 270) + (path /57D855DE/58023E8E) (attr smd) - (fp_text reference C93 (at 0 0) (layer F.SilkS) hide + (fp_text reference C123 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 5.1pF (at 0 0) (layer Cmts.User) + (fp_text value 330uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 4.826 1.778) (xy 4.318 1.778) (xy 4.318 -1.778) (xy 4.826 -1.778)) (layer F.Fab) (width 0.1)) + (fp_line (start 4.064 -2.54) (end 5.08 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 4.572 -2.032) (end 4.572 -3.048) (layer F.Fab) (width 0.1)) + (fp_line (start -4.826 1.778) (end -4.826 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 4.826 1.778) (end -4.826 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 4.826 -1.778) (end 4.826 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -4.826 -1.778) (end 4.826 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.254 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -3.25 0 90) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 158 "Net-(C93-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 3.25 0 90) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (model wrlshp/SW3dPS-cap_d.wrl + (offset (xyz -0.05003799924850464 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/5917D381-109F.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 86.1314 -11.4234 270) - (path /57D84E30/58023FC7) + (module Cryptech_Alpha_Footprints:C_D (layer F.Cu) (tedit 60BDD1BE) (tstamp 539EEDBF) + (at 54.8754 -90.997) + (path /57D855DE/58023E8D) (attr smd) - (fp_text reference C94 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C127 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 330uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 4.826 1.778) (xy 4.318 1.778) (xy 4.318 -1.778) (xy 4.826 -1.778)) (layer F.Fab) (width 0.1)) + (fp_line (start 4.064 -2.54) (end 5.08 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 4.572 -2.032) (end 4.572 -3.048) (layer F.Fab) (width 0.1)) + (fp_line (start -4.826 1.778) (end -4.826 -1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 4.826 1.778) (end -4.826 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start 4.826 -1.778) (end 4.826 1.778) (layer F.Fab) (width 0.1)) + (fp_line (start -4.826 -1.778) (end 4.826 -1.778) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.254 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 135 FT_MGMT_VPHY)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -3.25 0 180) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 3.25 0 180) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (model wrlshp/SW3dPS-cap_d.wrl + (offset (xyz -0.05003799924850464 -0 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 180)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/5917D381-109F.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 87.7824 -11.4234 270) - (path /57D84E30/58023FC5) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 21.463 -99.0854 270) + (path /57D84708/580240AD) (attr smd) - (fp_text reference C96 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C1 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 10uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 136 FT_MGMT_VPLL)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 202 PWR_18V)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 80.391 -16.097 270) - (path /57D84E30/58023FC8) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 21.463 -94.0689 270) + (path /57D84708/580240C1) (attr smd) - (fp_text reference C98 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C2 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 10uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 202 PWR_18V)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 89.2302 -11.4234 270) - (path /57D84E30/58023FC3) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 21.463 -89.0524 270) + (path /57D84708/580240C0) (attr smd) - (fp_text reference C99 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C3 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 10uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 202 PWR_18V)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 92.202 -20.3134 270) - (path /57D84E30/58023FC2) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 15.2908 -67.3354 90) + (path /57D84708/580240BF) (attr smd) - (fp_text reference C100 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C8 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1.5 180) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5 180) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 80.391 -19.1196 270) - (path /57D84E30/58023FC1) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 40.0558 -72.6186) + (path /57D853B0/58023F19) (attr smd) - (fp_text reference C101 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C113 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 22uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 -90) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 134 FT_MGMT_VCC3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 31.5 8.5 270) - (path /57D84FAD/58023F9A) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 6.4008 -44.9326 180) + (path /57D853B0/58023F05) (attr smd) - (fp_text reference C105 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C114 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 22uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 1 3V3_BATT)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 31.4842 1 270) - (path /57D85134/58023F67) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 40.0558 -79.4004 180) + (path /57D853B0/58023F0F) (attr smd) - (fp_text reference C108 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C119 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 161 "Net-(C117-Pad1)")) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 55.9562 -67.8942) - (path /57D85217/58023F53) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 6.4008 -38.5826) + (path /57D853B0/58023F0D) (attr smd) - (fp_text reference C109 (at 0 0) (layer F.SilkS) hide + (fp_text reference C120 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value 47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 -90) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 163 "Net-(C118-Pad1)")) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 34.3522 -30.1482 270) - (path /57D85260/58023F36) + (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 47.9298 -84.5566 180) + (path /57D855DE/58023E8F) (attr smd) - (fp_text reference C110 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C126 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 1 1) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1.5 90) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 -1.5 90) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 66.2004 -88.4428 180) - (path /57D85260/58023F39) + (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 42.8498 -56.09135) + (path /57D855DE/58023E9B) (attr smd) - (fp_text reference C111 (at 0 0) (layer F.SilkS) hide + (fp_text reference C133 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.01uF (at 0 0) (layer Cmts.User) + (fp_text value 47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 48.55 -29.475) - (path /57D85260/58023F37) + (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 74.5236 -65.8114) + (path /57D855DE/58023E91) (attr smd) - (fp_text reference C112 (at 0 0) (layer F.SilkS) hide + (fp_text reference C137 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value 47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 32.1818 -75.8444 90) - (path /57D853B0/58023F13) + (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 63.7794 -85.0646 270) + (path /57D8583B/58023E40) (attr smd) - (fp_text reference C115 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C165 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.047uF (at 0 0 90) (layer Cmts.User) + (fp_text value 47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 159 "Net-(C115-Pad1)")) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 1.5 180) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 -1.5 180) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 13.95 -41.625 270) - (path /57D853B0/58023F12) + (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 68.834 -54.383) + (path /57D8583B/58023E3E) (attr smd) - (fp_text reference C116 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C167 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.047uF (at 0 0 90) (layer Cmts.User) + (fp_text value 47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 160 "Net-(C116-Pad1)")) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 32.1818 -80.391 270) - (path /57D853B0/58023F10) + (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 73.0758 -75.9714) + (path /57D8583B/58023E3C) (attr smd) - (fp_text reference C117 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C168 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 27pF (at 0 0 90) (layer Cmts.User) + (fp_text value 47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.1))) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 161 "Net-(C117-Pad1)")) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 162 "Net-(C117-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 13.975 -37.35 90) - (path /57D853B0/58023F11) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 22.0472 -50.6476 270) + (path /57D85A75/58023E27) (attr smd) - (fp_text reference C118 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C205 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 27pF (at 0 0 90) (layer Cmts.User) + (fp_text value 22uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 163 "Net-(C118-Pad1)")) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 164 "Net-(C118-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 71.075 -97.7 90) - (path /57D854CB/58023EF3) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 22.0472 -46.2788 270) + (path /57D85A75/58023E26) (attr smd) - (fp_text reference C121 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C206 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 22uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 209 VCC_5V0)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 42 -93.5 180) - (path /57D854CB/58023EF2) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 34.6964 -55.3466 180) + (path /57D85A75/58023E2B) (attr smd) - (fp_text reference C122 (at 0 0) (layer F.SilkS) hide + (fp_text reference C209 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value 47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 270) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.9346 -69.8754 180) - (path /57D855DE/58023E90) + (module Cryptech_Alpha_Footprints:C_1210 (layer B.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 34.7472 -62.4078) + (path /57D85A75/58023E2A) (attr smd) - (fp_text reference C124 (at 0 0) (layer F.SilkS) hide + (fp_text reference C210 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 47uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.524 -2.54) (end -1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end -1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end 1.524 -2.54) (layer B.Fab) (width 0.1)) + (fp_line (start -1.524 2.54) (end 1.524 2.54) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 -90) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 166 "Net-(C208-Pad1)")) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 57.9374 -72.898 180) - (path /57D855DE/58023EA6) + (module Cryptech_Alpha_Footprints:C_1210 (layer F.Cu) (tedit 60BDCE00) (tstamp 539EEDBF) + (at 42.291 -85.6996 270) + (path /57D8583B/58023E3F) (attr smd) - (fp_text reference C125 (at 0 0) (layer F.SilkS) hide + (fp_text reference C166 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 47uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.524 2.54) (end -1.524 -2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 2.54) (end -1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start 1.524 -2.54) (end 1.524 2.54) (layer F.Fab) (width 0.1)) + (fp_line (start -1.524 -2.54) (end 1.524 -2.54) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 1 1) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1.5 180) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 1 smd rect (at 0 -1.5 180) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 270 360 90)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/F26EE9BE-B6B0.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.9346 -70.9168) - (path /57D855DE/58023E8C) + (module Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254 (layer B.Cu) (tedit 60BDCD8B) (tstamp 539EEDBF) + (at 56.4534 -68.8848) + (path /57D85134/58023F60) (attr smd) - (fp_text reference C128 (at 0 0) (layer F.SilkS) hide + (fp_text reference U13 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value XC7A200T-1FBG484C (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 10.922 -10.922) (xy 9.906 -10.922) (xy 9.906 -9.906) (xy 10.922 -9.906)) (layer B.Fab) (width 0.1)) + (fp_line (start -10.922 -10.922) (end -10.922 10.922) (layer B.Fab) (width 0.1)) + (fp_line (start 10.922 -10.922) (end -10.922 -10.922) (layer B.Fab) (width 0.1)) + (fp_line (start 10.922 10.922) (end 10.922 -10.922) (layer B.Fab) (width 0.1)) + (fp_line (start -10.922 10.922) (end 10.922 10.922) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer B.Fab) + (effects (font (size 5 5) (thickness 0.5)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad AB22 smd circle (at -10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 34 FMC_A20)) + (pad AB21 smd circle (at -9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 33 FMC_A19)) + (pad AB20 smd circle (at -8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 35 FMC_A21)) + (pad AB19 smd circle (at -7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad AB18 smd circle (at -6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 38 FMC_A24)) + (pad AB17 smd circle (at -5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 18 FMC_A4)) + (pad AB16 smd circle (at -4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 15 FMC_A1)) + (pad AB15 smd circle (at -3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 22 FMC_A8)) + (pad AB14 smd circle (at -2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad AB13 smd circle (at -1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 20 FMC_A6)) + (pad AB12 smd circle (at -0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 28 FMC_A14)) + (pad AB11 smd circle (at 0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_D4)) + (pad AB10 smd circle (at 1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 26 FMC_A12)) + (pad AB9 smd circle (at 2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad AB8 smd circle (at 3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 29 FMC_A15)) + (pad AB7 smd circle (at 4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 41 FMC_D0)) + (pad AB6 smd circle (at 5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 42 FMC_D1)) + (pad AB5 smd circle (at 6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 61 FMC_D20)) + (pad AB4 smd circle (at 7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad AB3 smd circle (at 8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 57 FMC_D16)) + (pad AB2 smd circle (at 9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_D15)) + (pad AB1 smd circle (at 10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_D14)) + (pad AA22 smd circle (at -10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad AA21 smd circle (at -9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_D9)) + (pad AA20 smd circle (at -8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 118 FPGA_GPIO_LED_3)) + (pad AA19 smd circle (at -7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 39 FMC_A25)) + (pad AA18 smd circle (at -6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 351 "Net-(U13-PadAA18)")) + (pad AA17 smd circle (at -5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad AA16 smd circle (at -4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 16 FMC_A2)) + (pad AA15 smd circle (at -3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 21 FMC_A7)) + (pad AA14 smd circle (at -2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 24 FMC_A10)) + (pad AA13 smd circle (at -1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 19 FMC_A5)) + (pad AA12 smd circle (at -0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad AA11 smd circle (at 0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_D5)) + (pad AA10 smd circle (at 1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 352 "Net-(U13-PadAA10)")) + (pad AA9 smd circle (at 2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 30 FMC_A16)) + (pad AA8 smd circle (at 3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 31 FMC_A17)) + (pad AA7 smd circle (at 4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad AA6 smd circle (at 5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_NWE)) + (pad AA5 smd circle (at 6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 60 FMC_D19)) + (pad AA4 smd circle (at 7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 63 FMC_D22)) + (pad AA3 smd circle (at 8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_D18)) + (pad AA2 smd circle (at 9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad AA1 smd circle (at 10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_D13)) + (pad Y22 smd circle (at -10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 37 FMC_A23)) + (pad Y21 smd circle (at -9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 36 FMC_A22)) + (pad Y20 smd circle (at -8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad Y19 smd circle (at -7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 353 "Net-(U13-PadY19)")) + (pad Y18 smd circle (at -6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_D8)) + (pad Y17 smd circle (at -5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 14 FMC_A0)) + (pad Y16 smd circle (at -4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 17 FMC_A3)) + (pad Y15 smd circle (at -3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad Y14 smd circle (at -2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 25 FMC_A11)) + (pad Y13 smd circle (at -1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 23 FMC_A9)) + (pad Y12 smd circle (at -0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_D7)) + (pad Y11 smd circle (at 0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_D6)) + (pad Y10 smd circle (at 1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad Y9 smd circle (at 2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 354 "Net-(U13-PadY9)")) + (pad Y8 smd circle (at 3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 355 "Net-(U13-PadY8)")) + (pad Y7 smd circle (at 4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 32 FMC_A18)) + (pad Y6 smd circle (at 5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_NWAIT)) + (pad Y5 smd circle (at 6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad Y4 smd circle (at 7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 62 FMC_D21)) + (pad Y3 smd circle (at 8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_D17)) + (pad Y2 smd circle (at 9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 356 "Net-(U13-PadY2)")) + (pad Y1 smd circle (at 10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 608 ICE40_FPGA_MISO)) + (pad W22 smd circle (at -10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 117 FPGA_GPIO_LED_2)) + (pad W21 smd circle (at -9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 357 "Net-(U13-PadW21)")) + (pad W20 smd circle (at -8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_D10)) + (pad W19 smd circle (at -7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 13 DIGITIZED_NOISE)) + (pad W18 smd circle (at -6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad W17 smd circle (at -5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_NL)) + (pad W16 smd circle (at -4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_NOE)) + (pad W15 smd circle (at -3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 358 "Net-(U13-PadW15)")) + (pad W14 smd circle (at -2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 68 FMC_D27)) + (pad W13 smd circle (at -1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad W12 smd circle (at -0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 67 FMC_D26)) + (pad W11 smd circle (at 0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 40 FMC_CLK)) + (pad W10 smd circle (at 1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 65 FMC_D24)) + (pad W9 smd circle (at 2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 359 "Net-(U13-PadW9)")) + (pad W8 smd circle (at 3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad W7 smd circle (at 4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 360 "Net-(U13-PadW7)")) + (pad W6 smd circle (at 5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 361 "Net-(U13-PadW6)")) + (pad W5 smd circle (at 6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 362 "Net-(U13-PadW5)")) + (pad W4 smd circle (at 7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 363 "Net-(U13-PadW4)")) + (pad W3 smd circle (at 8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad W2 smd circle (at 9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 609 ICE40_FPGA_CS_N)) + (pad W1 smd circle (at 10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 610 ICE40_FPGA_MOSI)) + (pad V22 smd circle (at -10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 364 "Net-(U13-PadV22)")) + (pad V21 smd circle (at -9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad V20 smd circle (at -8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 69 FMC_D28)) + (pad V19 smd circle (at -7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 365 "Net-(U13-PadV19)")) + (pad V18 smd circle (at -6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 70 FMC_D29)) + (pad V17 smd circle (at -5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 366 "Net-(U13-PadV17)")) + (pad V16 smd circle (at -4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad V15 smd circle (at -3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 367 "Net-(U13-PadV15)")) + (pad V14 smd circle (at -2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 368 "Net-(U13-PadV14)")) + (pad V13 smd circle (at -1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 369 "Net-(U13-PadV13)")) + (pad V12 smd circle (at -0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 258 "/Config interface/FPGA_JTAG_TCK")) + (pad V11 smd circle (at 0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad V10 smd circle (at 1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 370 "Net-(U13-PadV10)")) + (pad V9 smd circle (at 2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 371 "Net-(U13-PadV9)")) + (pad V8 smd circle (at 3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 372 "Net-(U13-PadV8)")) + (pad V7 smd circle (at 4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 373 "Net-(U13-PadV7)")) + (pad V6 smd circle (at 5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad V5 smd circle (at 6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_NE1)) + (pad V4 smd circle (at 7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 64 FMC_D23)) + (pad V3 smd circle (at 8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 611 ICE40_FPGA_SCK)) + (pad V2 smd circle (at 9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 27 FMC_A13)) + (pad V1 smd circle (at 10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad U22 smd circle (at -10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 196 "Net-(R65-Pad1)")) + (pad U21 smd circle (at -9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 374 "Net-(U13-PadU21)")) + (pad U20 smd circle (at -8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_D12)) + (pad U19 smd circle (at -7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad U18 smd circle (at -6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 375 "Net-(U13-PadU18)")) + (pad U17 smd circle (at -5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 376 "Net-(U13-PadU17)")) + (pad U16 smd circle (at -4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 377 "Net-(U13-PadU16)")) + (pad U15 smd circle (at -3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 378 "Net-(U13-PadU15)")) + (pad U14 smd circle (at -2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad U13 smd circle (at -1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 265 "/Config interface/FPGA_JTAG_TDO")) + (pad U12 smd circle (at -0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 259 "/Config interface/FPGA_INIT_B_INT1")) + (pad U11 smd circle (at 0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 255 "/Config interface/FPGA_M0")) + (pad U10 smd circle (at 1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 254 "/Config interface/FPGA_M1")) + (pad U9 smd circle (at 2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 253 "/Config interface/FPGA_M2")) + (pad U8 smd circle (at 3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad U7 smd circle (at 4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 379 "Net-(U13-PadU7)")) + (pad U6 smd circle (at 5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 380 "Net-(U13-PadU6)")) + (pad U5 smd circle (at 6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 381 "Net-(U13-PadU5)")) + (pad U4 smd circle (at 7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad U3 smd circle (at 8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 115 FPGA_GPIO_LED_0)) + (pad U2 smd circle (at 9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_D3)) + (pad U1 smd circle (at 10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 43 FMC_D2)) + (pad T22 smd circle (at -10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad T21 smd circle (at -9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 382 "Net-(U13-PadT21)")) + (pad T20 smd circle (at -8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 383 "Net-(U13-PadT20)")) + (pad T19 smd circle (at -7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 264 "/MKM interface/FPGA_CFG_CS_N1")) + (pad T18 smd circle (at -6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 384 "Net-(U13-PadT18)")) + (pad T17 smd circle (at -5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad T16 smd circle (at -4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 385 "Net-(U13-PadT16)")) + (pad T15 smd circle (at -3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 386 "Net-(U13-PadT15)")) + (pad T14 smd circle (at -2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 387 "Net-(U13-PadT14)")) + (pad T13 smd circle (at -1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 257 "/Config interface/FPGA_JTAG_TMS")) + (pad T12 smd circle (at -0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad T11 smd circle (at 0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad T10 smd circle (at 1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad T9 smd circle (at 2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.96 -63.8556) - (path /57D855DE/58023E89) - (attr smd) - (fp_text reference C129 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad T8 smd circle (at 3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad T7 smd circle (at 4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 57.9374 -71.9074) - (path /57D855DE/58023E8B) - (attr smd) - (fp_text reference C130 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad T6 smd circle (at 5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 388 "Net-(U13-PadT6)")) + (pad T5 smd circle (at 6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 389 "Net-(U13-PadT5)")) + (pad T4 smd circle (at 7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 390 "Net-(U13-PadT4)")) + (pad T3 smd circle (at 8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 391 "Net-(U13-PadT3)")) + (pad T2 smd circle (at 9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad T1 smd circle (at 10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 116 FPGA_GPIO_LED_1)) + (pad R22 smd circle (at -10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 263 "/MKM interface/FPGA_CFG_MISO1")) + (pad R21 smd circle (at -9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D30)) + (pad R20 smd circle (at -8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad R19 smd circle (at -7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 392 "Net-(U13-PadR19)")) + (pad R18 smd circle (at -6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 393 "Net-(U13-PadR18)")) + (pad R17 smd circle (at -5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 394 "Net-(U13-PadR17)")) + (pad R16 smd circle (at -4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 395 "Net-(U13-PadR16)")) + (pad R15 smd circle (at -3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad R14 smd circle (at -2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 396 "Net-(U13-PadR14)")) + (pad R13 smd circle (at -1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 256 "/Config interface/FPGA_JTAG_TDI")) + (pad R12 smd circle (at -0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad R11 smd circle (at 0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad R10 smd circle (at 1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad R9 smd circle (at 2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad R8 smd circle (at 3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 57.9628 -66.9036) - (path /57D855DE/58023E88) - (attr smd) - (fp_text reference C131 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad R7 smd circle (at 4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad R6 smd circle (at 5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 397 "Net-(U13-PadR6)")) + (pad R5 smd circle (at 6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad R4 smd circle (at 7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 66 FMC_D25)) + (pad R3 smd circle (at 8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 398 "Net-(U13-PadR3)")) + (pad R2 smd circle (at 9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 399 "Net-(U13-PadR2)")) + (pad R1 smd circle (at 10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 400 "Net-(U13-PadR1)")) + (pad P22 smd circle (at -10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 262 "/MKM interface/FPGA_CFG_MOSI1")) + (pad P21 smd circle (at -9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D31)) + (pad P20 smd circle (at -8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 401 "Net-(U13-PadP20)")) + (pad P19 smd circle (at -7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 402 "Net-(U13-PadP19)")) + (pad P18 smd circle (at -6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad P17 smd circle (at -5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 403 "Net-(U13-PadP17)")) + (pad P16 smd circle (at -4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 404 "Net-(U13-PadP16)")) + (pad P15 smd circle (at -3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 405 "Net-(U13-PadP15)")) + (pad P14 smd circle (at -2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 406 "Net-(U13-PadP14)")) + (pad P13 smd circle (at -1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (pad P12 smd circle (at -0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad P11 smd circle (at 0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad P10 smd circle (at 1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad P9 smd circle (at 2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad P8 smd circle (at 3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad P7 smd circle (at 4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad P6 smd circle (at 5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 407 "Net-(U13-PadP6)")) + (pad P5 smd circle (at 6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 408 "Net-(U13-PadP5)")) + (pad P4 smd circle (at 7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 409 "Net-(U13-PadP4)")) + (pad P3 smd circle (at 8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad P2 smd circle (at 9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 410 "Net-(U13-PadP2)")) + (pad P1 smd circle (at 10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 411 "Net-(U13-PadP1)")) + (pad N22 smd circle (at -10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 412 "Net-(U13-PadN22)")) + (pad N21 smd circle (at -9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad N20 smd circle (at -8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 413 "Net-(U13-PadN20)")) + (pad N19 smd circle (at -7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 414 "Net-(U13-PadN19)")) + (pad N18 smd circle (at -6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 415 "Net-(U13-PadN18)")) + (pad N17 smd circle (at -5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 416 "Net-(U13-PadN17)")) + (pad N16 smd circle (at -4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad N15 smd circle (at -3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_D11)) + (pad N14 smd circle (at -2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 417 "Net-(U13-PadN14)")) + (pad N13 smd circle (at -1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 418 "Net-(U13-PadN13)")) + (pad N12 smd circle (at -0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 260 "/Config interface/FPGA_PROGRAM_B1")) + (pad N11 smd circle (at 0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad N10 smd circle (at 1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad N9 smd circle (at 2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad N8 smd circle (at 3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad N7 smd circle (at 4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad N6 smd circle (at 5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad N5 smd circle (at 6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 419 "Net-(U13-PadN5)")) + (pad N4 smd circle (at 7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 420 "Net-(U13-PadN4)")) + (pad N3 smd circle (at 8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 421 "Net-(U13-PadN3)")) + (pad N2 smd circle (at 9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 422 "Net-(U13-PadN2)")) + (pad N1 smd circle (at 10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad M22 smd circle (at -10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 423 "Net-(U13-PadM22)")) + (pad M21 smd circle (at -9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 424 "Net-(U13-PadM21)")) + (pad M20 smd circle (at -8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 425 "Net-(U13-PadM20)")) + (pad M19 smd circle (at -7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad M18 smd circle (at -6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 426 "Net-(U13-PadM18)")) + (pad M17 smd circle (at -5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 427 "Net-(U13-PadM17)")) + (pad M16 smd circle (at -4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 428 "Net-(U13-PadM16)")) + (pad M15 smd circle (at -3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 429 "Net-(U13-PadM15)")) + (pad M14 smd circle (at -2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad M13 smd circle (at -1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 430 "Net-(U13-PadM13)")) + (pad M12 smd circle (at -0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad M11 smd circle (at 0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad M10 smd circle (at 1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad M9 smd circle (at 2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 431 "Net-(U13-PadM9)")) + (pad M8 smd circle (at 3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad M7 smd circle (at 4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad M6 smd circle (at 5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 432 "Net-(U13-PadM6)")) + (pad M5 smd circle (at 6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 433 "Net-(U13-PadM5)")) + (pad M4 smd circle (at 7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad M3 smd circle (at 8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 434 "Net-(U13-PadM3)")) + (pad M2 smd circle (at 9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 435 "Net-(U13-PadM2)")) + (pad M1 smd circle (at 10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 436 "Net-(U13-PadM1)")) + (pad L22 smd circle (at -10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad L21 smd circle (at -9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 437 "Net-(U13-PadL21)")) + (pad L20 smd circle (at -8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 438 "Net-(U13-PadL20)")) + (pad L19 smd circle (at -7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 439 "Net-(U13-PadL19)")) + (pad L18 smd circle (at -6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 440 "Net-(U13-PadL18)")) + (pad L17 smd circle (at -5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad L16 smd circle (at -4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 441 "Net-(U13-PadL16)")) + (pad L15 smd circle (at -3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 442 "Net-(U13-PadL15)")) + (pad L14 smd circle (at -2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 443 "Net-(U13-PadL14)")) + (pad L13 smd circle (at -1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 444 "Net-(U13-PadL13)")) + (pad L12 smd circle (at -0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 261 "/Config interface/FPGA_CFG_SCLK1")) + (pad L11 smd circle (at 0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad L10 smd circle (at 1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 445 "Net-(U13-PadL10)")) + (pad L9 smd circle (at 2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad L8 smd circle (at 3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad L7 smd circle (at 4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad L6 smd circle (at 5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 446 "Net-(U13-PadL6)")) + (pad L5 smd circle (at 6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 447 "Net-(U13-PadL5)")) + (pad L4 smd circle (at 7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 448 "Net-(U13-PadL4)")) + (pad L3 smd circle (at 8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 449 "Net-(U13-PadL3)")) + (pad L2 smd circle (at 9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad L1 smd circle (at 10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 450 "Net-(U13-PadL1)")) + (pad K22 smd circle (at -10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 451 "Net-(U13-PadK22)")) + (pad K21 smd circle (at -9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 452 "Net-(U13-PadK21)")) + (pad K20 smd circle (at -8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad K19 smd circle (at -7.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 453 "Net-(U13-PadK19)")) + (pad K18 smd circle (at -6.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 454 "Net-(U13-PadK18)")) + (pad K17 smd circle (at -5.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 455 "Net-(U13-PadK17)")) + (pad K16 smd circle (at -4.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 456 "Net-(U13-PadK16)")) + (pad K15 smd circle (at -3.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad K14 smd circle (at -2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 457 "Net-(U13-PadK14)")) + (pad K13 smd circle (at -1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 458 "Net-(U13-PadK13)")) + (pad K12 smd circle (at -0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad K11 smd circle (at 0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad K10 smd circle (at 1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad K9 smd circle (at 2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad K8 smd circle (at 3.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad K7 smd circle (at 4.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad K6 smd circle (at 5.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 459 "Net-(U13-PadK6)")) + (pad K5 smd circle (at 6.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad K4 smd circle (at 7.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 460 "Net-(U13-PadK4)")) + (pad K3 smd circle (at 8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 461 "Net-(U13-PadK3)")) + (pad K2 smd circle (at 9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 462 "Net-(U13-PadK2)")) + (pad K1 smd circle (at 10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 463 "Net-(U13-PadK1)")) + (pad J22 smd circle (at -10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 464 "Net-(U13-PadJ22)")) + (pad J21 smd circle (at -9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 465 "Net-(U13-PadJ21)")) + (pad J20 smd circle (at -8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 466 "Net-(U13-PadJ20)")) + (pad J19 smd circle (at -7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 467 "Net-(U13-PadJ19)")) + (pad J18 smd circle (at -6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad J17 smd circle (at -5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 468 "Net-(U13-PadJ17)")) + (pad J16 smd circle (at -4.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 469 "Net-(U13-PadJ16)")) + (pad J15 smd circle (at -3.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 470 "Net-(U13-PadJ15)")) + (pad J14 smd circle (at -2.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 471 "Net-(U13-PadJ14)")) + (pad J13 smd circle (at -1.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad J12 smd circle (at -0.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad J11 smd circle (at 0.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad J10 smd circle (at 1.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad J9 smd circle (at 2.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad J8 smd circle (at 3.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad J7 smd circle (at 4.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad J6 smd circle (at 5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 472 "Net-(U13-PadJ6)")) + (pad J5 smd circle (at 6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 473 "Net-(U13-PadJ5)")) + (pad J4 smd circle (at 7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 474 "Net-(U13-PadJ4)")) + (pad J3 smd circle (at 8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad J2 smd circle (at 9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 475 "Net-(U13-PadJ2)")) + (pad J1 smd circle (at 10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 476 "Net-(U13-PadJ1)")) + (pad H22 smd circle (at -10.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 477 "Net-(U13-PadH22)")) + (pad H21 smd circle (at -9.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad H20 smd circle (at -8.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 478 "Net-(U13-PadH20)")) + (pad H19 smd circle (at -7.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 479 "Net-(U13-PadH19)")) + (pad H18 smd circle (at -6.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 480 "Net-(U13-PadH18)")) + (pad H17 smd circle (at -5.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 481 "Net-(U13-PadH17)")) + (pad H16 smd circle (at -4.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad H15 smd circle (at -3.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 482 "Net-(U13-PadH15)")) + (pad H14 smd circle (at -2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 483 "Net-(U13-PadH14)")) + (pad H13 smd circle (at -1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 484 "Net-(U13-PadH13)")) + (pad H12 smd circle (at -0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad H11 smd circle (at 0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad H10 smd circle (at 1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad H9 smd circle (at 2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad H8 smd circle (at 3.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad H7 smd circle (at 4.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad H6 smd circle (at 5.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad H5 smd circle (at 6.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 485 "Net-(U13-PadH5)")) + (pad H4 smd circle (at 7.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 486 "Net-(U13-PadH4)")) + (pad H3 smd circle (at 8.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 487 "Net-(U13-PadH3)")) + (pad H2 smd circle (at 9.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 488 "Net-(U13-PadH2)")) + (pad H1 smd circle (at 10.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad G22 smd circle (at -10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 489 "Net-(U13-PadG22)")) + (pad G21 smd circle (at -9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 490 "Net-(U13-PadG21)")) + (pad G20 smd circle (at -8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 491 "Net-(U13-PadG20)")) + (pad G19 smd circle (at -7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad G18 smd circle (at -6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 492 "Net-(U13-PadG18)")) + (pad G17 smd circle (at -5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 493 "Net-(U13-PadG17)")) + (pad G16 smd circle (at -4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 494 "Net-(U13-PadG16)")) + (pad G15 smd circle (at -3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 495 "Net-(U13-PadG15)")) + (pad G14 smd circle (at -2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad G13 smd circle (at -1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 496 "Net-(U13-PadG13)")) + (pad G12 smd circle (at -0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad G11 smd circle (at 0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 244 "/Config interface/FPGA_DONE_INT")) + (pad G10 smd circle (at 1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad G9 smd circle (at 2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad G8 smd circle (at 3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad G7 smd circle (at 4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad G6 smd circle (at 5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad G5 smd circle (at 6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad G4 smd circle (at 7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 497 "Net-(U13-PadG4)")) + (pad G3 smd circle (at 8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 498 "Net-(U13-PadG3)")) + (pad G2 smd circle (at 9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 499 "Net-(U13-PadG2)")) + (pad G1 smd circle (at 10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 500 "Net-(U13-PadG1)")) + (pad F22 smd circle (at -10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad F21 smd circle (at -9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 501 "Net-(U13-PadF21)")) + (pad F20 smd circle (at -8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 502 "Net-(U13-PadF20)")) + (pad F19 smd circle (at -7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 503 "Net-(U13-PadF19)")) + (pad F18 smd circle (at -6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 592 ICE40_GPIO_FPGA_3)) + (pad F17 smd circle (at -5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad F16 smd circle (at -4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 121 FPGA_IRQ_N_1)) + (pad F15 smd circle (at -3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 504 "Net-(U13-PadF15)")) + (pad F14 smd circle (at -2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 120 FPGA_IRQ_N_0)) + (pad F13 smd circle (at -1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 505 "Net-(U13-PadF13)")) + (pad F12 smd circle (at -0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad F11 smd circle (at 0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad F10 smd circle (at 1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 506 "Net-(U13-PadF10)")) + (pad F9 smd circle (at 2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 507 "Net-(U13-PadF9)")) + (pad F8 smd circle (at 3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 508 "Net-(U13-PadF8)")) + (pad F7 smd circle (at 4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 509 "Net-(U13-PadF7)")) + (pad F6 smd circle (at 5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 510 "Net-(U13-PadF6)")) + (pad F5 smd circle (at 6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad F4 smd circle (at 7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 511 "Net-(U13-PadF4)")) + (pad F3 smd circle (at 8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 512 "Net-(U13-PadF3)")) + (pad F2 smd circle (at 9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad F1 smd circle (at 10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 513 "Net-(U13-PadF1)")) + (pad E22 smd circle (at -10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 514 "Net-(U13-PadE22)")) + (pad E21 smd circle (at -9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 515 "Net-(U13-PadE21)")) + (pad E20 smd circle (at -8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad E19 smd circle (at -7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 590 ICE40_GPIO_FPGA_0)) + (pad E18 smd circle (at -6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 593 ICE40_GPIO_FPGA_2)) + (pad E17 smd circle (at -5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 122 FPGA_IRQ_N_2)) + (pad E16 smd circle (at -4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 516 "Net-(U13-PadE16)")) + (pad E15 smd circle (at -3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad E14 smd circle (at -2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 99 FPGA_GPIO_A_0)) + (pad E13 smd circle (at -1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 100 FPGA_GPIO_A_1)) + (pad E12 smd circle (at -0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad E11 smd circle (at 0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad E10 smd circle (at 1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 517 "Net-(U13-PadE10)")) + (pad E9 smd circle (at 2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad E8 smd circle (at 3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 518 "Net-(U13-PadE8)")) + (pad E7 smd circle (at 4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad E6 smd circle (at 5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 519 "Net-(U13-PadE6)")) + (pad E5 smd circle (at 6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad E4 smd circle (at 7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad E3 smd circle (at 8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 520 "Net-(U13-PadE3)")) + (pad E2 smd circle (at 9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 521 "Net-(U13-PadE2)")) + (pad E1 smd circle (at 10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 522 "Net-(U13-PadE1)")) + (pad D22 smd circle (at -10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 523 "Net-(U13-PadD22)")) + (pad D21 smd circle (at -9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 524 "Net-(U13-PadD21)")) + (pad D20 smd circle (at -8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 525 "Net-(U13-PadD20)")) + (pad D19 smd circle (at -7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 526 "Net-(U13-PadD19)")) + (pad D18 smd circle (at -6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad D17 smd circle (at -5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 98 FPGA_GCLK)) + (pad D16 smd circle (at -4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 527 "Net-(U13-PadD16)")) + (pad D15 smd circle (at -3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 528 "Net-(U13-PadD15)")) + (pad D14 smd circle (at -2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 110 FPGA_GPIO_B_3)) + (pad D13 smd circle (at -1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad D12 smd circle (at -0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad D11 smd circle (at 0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 529 "Net-(U13-PadD11)")) + (pad D10 smd circle (at 1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 530 "Net-(U13-PadD10)")) + (pad D9 smd circle (at 2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 531 "Net-(U13-PadD9)")) + (pad D8 smd circle (at 3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad D7 smd circle (at 4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 532 "Net-(U13-PadD7)")) + (pad D6 smd circle (at 5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 533 "Net-(U13-PadD6)")) + (pad D5 smd circle (at 6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 534 "Net-(U13-PadD5)")) + (pad D4 smd circle (at 7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad D3 smd circle (at 8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad D2 smd circle (at 9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 535 "Net-(U13-PadD2)")) + (pad D1 smd circle (at 10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 536 "Net-(U13-PadD1)")) + (pad C22 smd circle (at -10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 114 FPGA_GPIO_B_7)) + (pad C21 smd circle (at -9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad C20 smd circle (at -8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 113 FPGA_GPIO_B_6)) + (pad C19 smd circle (at -7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 537 "Net-(U13-PadC19)")) + (pad C18 smd circle (at -6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 111 FPGA_GPIO_B_4)) + (pad C17 smd circle (at -5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 591 ICE40_GPIO_FPGA_1)) + (pad C16 smd circle (at -4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad C15 smd circle (at -3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 108 FPGA_GPIO_B_1)) + (pad C14 smd circle (at -2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 123 FPGA_IRQ_N_3)) + (pad C13 smd circle (at -1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 103 FPGA_GPIO_A_4)) + (pad C12 smd circle (at -0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad C11 smd circle (at 0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 538 "Net-(U13-PadC11)")) + (pad C10 smd circle (at 1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad C9 smd circle (at 2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 539 "Net-(U13-PadC9)")) + (pad C8 smd circle (at 3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 540 "Net-(U13-PadC8)")) + (pad C7 smd circle (at 4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 541 "Net-(U13-PadC7)")) + (pad C6 smd circle (at 5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad C5 smd circle (at 6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 542 "Net-(U13-PadC5)")) + (pad C4 smd circle (at 7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 543 "Net-(U13-PadC4)")) + (pad C3 smd circle (at 8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad C2 smd circle (at 9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 544 "Net-(U13-PadC2)")) + (pad C1 smd circle (at 10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad B22 smd circle (at -10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 545 "Net-(U13-PadB22)")) + (pad B21 smd circle (at -9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 546 "Net-(U13-PadB21)")) + (pad B20 smd circle (at -8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 612 "Net-(U13-PadB20)")) + (pad B19 smd circle (at -7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad B18 smd circle (at -6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 97 FPGA_ENTROPY_DISABLE)) + (pad B17 smd circle (at -5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 616 ICE40_GPIO_FPGA_4)) + (pad B16 smd circle (at -4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 109 FPGA_GPIO_B_2)) + (pad B15 smd circle (at -3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 106 FPGA_GPIO_A_7)) + (pad B14 smd circle (at -2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad B13 smd circle (at -1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 104 FPGA_GPIO_A_5)) + (pad B12 smd circle (at -0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad B11 smd circle (at 0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 547 "Net-(U13-PadB11)")) + (pad B10 smd circle (at 1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 548 "Net-(U13-PadB10)")) + (pad B9 smd circle (at 2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 549 "Net-(U13-PadB9)")) + (pad B8 smd circle (at 3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 550 "Net-(U13-PadB8)")) + (pad B7 smd circle (at 4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 551 "Net-(U13-PadB7)")) + (pad B6 smd circle (at 5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 552 "Net-(U13-PadB6)")) + (pad B5 smd circle (at 6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 553 "Net-(U13-PadB5)")) + (pad B4 smd circle (at 7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 554 "Net-(U13-PadB4)")) + (pad B3 smd circle (at 8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad B2 smd circle (at 9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 555 "Net-(U13-PadB2)")) + (pad B1 smd circle (at 10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 556 "Net-(U13-PadB1)")) + (pad A22 smd circle (at -10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad A21 smd circle (at -9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 112 FPGA_GPIO_B_5)) + (pad A20 smd circle (at -8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 613 ICE40_GPIO_FPGA_7)) + (pad A19 smd circle (at -7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 614 ICE40_GPIO_FPGA_5)) + (pad A18 smd circle (at -6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 615 ICE40_GPIO_FPGA_6)) + (pad A17 smd circle (at -5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad A16 smd circle (at -4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 107 FPGA_GPIO_B_0)) + (pad A15 smd circle (at -3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 105 FPGA_GPIO_A_6)) + (pad A14 smd circle (at -2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 102 FPGA_GPIO_A_3)) + (pad A13 smd circle (at -1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 101 FPGA_GPIO_A_2)) + (pad A12 smd circle (at -0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad A11 smd circle (at 0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad A10 smd circle (at 1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 557 "Net-(U13-PadA10)")) + (pad A9 smd circle (at 2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad A8 smd circle (at 3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 558 "Net-(U13-PadA8)")) + (pad A7 smd circle (at 4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad A6 smd circle (at 5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 559 "Net-(U13-PadA6)")) + (pad A5 smd circle (at 6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad A4 smd circle (at 7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 560 "Net-(U13-PadA4)")) + (pad A3 smd circle (at 8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad A2 smd circle (at 9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 3 GND)) + (pad A1 smd circle (at 10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 561 "Net-(U13-PadA1)")) + (model wrlshp/041B98A5-F02D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 0)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 57.4548 -70.4088 90) - (path /57D855DE/58023E8A) + (module Cryptech_Alpha_Footprints:ASF (layer B.Cu) (tedit 60BDCC8E) (tstamp 539EEDBF) + (at 67.9704 -84.709) + (path /57D85260/58023F3D) (attr smd) - (fp_text reference C134 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference Q5 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value ASFL1-50.000MHZ-EK-T (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_poly (pts (xy 2.032 -2.286) (xy 0.508 -2.286) (xy 0.508 -0.508) (xy 2.032 -0.508)) (layer B.Fab) (width 0.1)) + (fp_line (start -2.032 -2.286) (end -2.032 2.286) (layer B.Fab) (width 0.12)) + (fp_line (start 2.032 -2.286) (end -2.032 -2.286) (layer B.Fab) (width 0.12)) + (fp_line (start 2.032 2.286) (end 2.032 -2.286) (layer B.Fab) (width 0.12)) + (fp_line (start -2.032 2.286) (end 2.032 2.286) (layer B.Fab) (width 0.12)) + (fp_text user %R (at 0 0.762) (layer B.Fab) + (effects (font (size 1.2 1.2) (thickness 0.15)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 4 smd rect (at -1.0922 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 3 smd rect (at -1.0922 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 187 "Net-(Q5-Pad3)")) + (pad 1 smd rect (at 1.1302 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 186 "Net-(Q5-Pad1)")) + (pad 2 smd rect (at 1.1302 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.96 -67.8942) - (path /57D855DE/58023EB0) - (attr smd) - (fp_text reference C135 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) + (module Cryptech_Alpha_Footprints:SOT95P280X100-5N (layer F.Cu) (tedit 60BD3E3A) (tstamp 5F036F55) + (at 71.1 -27.7) + (path /57D8509E/5F0932AD) + (fp_text reference U12 (at 1.755545 -3.587435) (layer F.SilkS) + (effects (font (size 1.642764 1.642764) (thickness 0.015))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text value ADP121-AUJZ25R7 (at 13.23165 3.409705) (layer F.Fab) hide + (effects (font (size 1.642937 1.642937) (thickness 0.015))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (fp_line (start -1.905 1.524) (end -1.905 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 1.905 1.524) (end -1.905 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 1.905 -1.524) (end 1.905 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -1.905 -1.524) (end 1.905 -1.524) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0.02 0.268) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (fp_text user Name (at 0.71248 -3.587855) (layer Dwgs.User) hide + (effects (font (size 1.642953 1.642953) (thickness 0.015))) ) + (fp_arc (start 0 -1.446774) (end -0.1778 -1.2192) (angle -76) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -1.4478) (end -0.3048 -1.4478) (angle -180) (layer F.Fab) (width 0.1)) + (fp_arc (start 0 -1.4478) (end -0.3048 -1.4478) (angle -180) (layer F.SilkS) (width 0.1524)) + (pad 5 smd rect (at 1.2192 -0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 572 "/Master Key Memory/MKM_VPP")) + (pad 4 smd rect (at 1.2192 0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 575 "Net-(U12-Pad4)")) + (pad 3 smd rect (at -1.2192 0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) + (pad 2 smd rect (at -1.2192 0) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 1 smd rect (at -1.2192 -0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 61.9506 -66.8782) - (path /57D855DE/58023EAF) - (attr smd) - (fp_text reference C138 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) + (module Cryptech_Alpha_Footprints:SOT95P280X100-5N (layer F.Cu) (tedit 60BD3E3A) (tstamp 5F036E6C) + (at 71.1 -30.9) + (path /57D8509E/5F031C66) + (fp_text reference U10 (at 1.755545 -3.587435) (layer F.SilkS) + (effects (font (size 1.642764 1.642764) (thickness 0.015))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_text value ADP121-AUJZ12R7 (at 13.23165 3.409705) (layer F.Fab) hide + (effects (font (size 1.642937 1.642937) (thickness 0.015))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (fp_line (start -1.905 1.524) (end -1.905 -1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 1.905 1.524) (end -1.905 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start 1.905 -1.524) (end 1.905 1.524) (layer F.Fab) (width 0.1)) + (fp_line (start -1.905 -1.524) (end 1.905 -1.524) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0.166) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (fp_text user Name (at 0.71248 -3.587855) (layer Dwgs.User) hide + (effects (font (size 1.642953 1.642953) (thickness 0.015))) ) + (fp_arc (start 0 -1.446774) (end -0.1778 -1.2192) (angle -76) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -1.4478) (end -0.3048 -1.4478) (angle -180) (layer F.Fab) (width 0.1)) + (fp_arc (start 0 -1.4478) (end -0.3048 -1.4478) (angle -180) (layer F.SilkS) (width 0.1524)) + (pad 5 smd rect (at 1.2192 -0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 571 "/Master Key Memory/MKM_VCC")) + (pad 4 smd rect (at 1.2192 0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 574 "Net-(U10-Pad4)")) + (pad 3 smd rect (at -1.2192 0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) + (pad 2 smd rect (at -1.2192 0) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 3 GND)) + (pad 1 smd rect (at -1.2192 -0.9398) (size 1.2192 0.508) (layers F.Cu F.Paste F.Mask) + (net 1 3V3_BATT)) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.9346 -65.8876) - (path /57D855DE/58023EAE) + (module Cryptech_Alpha_Footprints:694106301002 (layer F.Cu) (tedit 60BDC87E) (tstamp 539EEDBF) + (at 20 18.4) + (path /57D84708/580240B4) (attr smd) - (fp_text reference C142 (at 0 0) (layer F.SilkS) hide + (fp_text reference JP1 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 694106301002 (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -4.8 0) (end -4.8 -13.6) (layer F.Fab) (width 0.12)) + (fp_line (start 4.8 0) (end -4.8 0) (layer F.Fab) (width 0.12)) + (fp_line (start 4.8 -13.6) (end 4.8 0) (layer F.Fab) (width 0.12)) + (fp_line (start -4.8 -13.6) (end 4.8 -13.6) (layer F.Fab) (width 0.12)) + (fp_text user %R (at 0 -6.7 90) (layer F.Fab) + (effects (font (size 5 5) (thickness 0.5))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 3 thru_hole oval (at 4.8 -10.6 90) (size 4.5 2) (drill oval 3 0.8) (layers *.Cu *.Paste *.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (pad 2 thru_hole oval (at 0 -7.8 90) (size 2 4.5) (drill oval 0.8 3) (layers *.Cu *.Paste *.Mask) + (net 3 GND)) + (pad 1 thru_hole oval (at 0 -13.6 90) (size 2 4.5) (drill oval 0.8 3) (layers *.Cu *.Paste *.Mask) + (net 202 PWR_18V)) + (model wrlshp/PJ-002A.wrl + (offset (xyz 0.0551179991722107 -0.01193799982070923 6.499999602379799)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) + (rotate (xyz 90 180 270)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/51D2E761-0F4D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) + (rotate (xyz 0 0 180)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 55.4736 -71.3994 90) - (path /57D855DE/58023EA7) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 5F035EDF) + (at 86.2 -27.5 270) + (path /57D8509E/5F05B071) (attr smd) - (fp_text reference C143 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) + (fp_text reference C107 (at 1.846 -1.43 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.1))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 10uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 573 "/Master Key Memory/MKM_VCC_PLL")) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 58.9788 -65.8876) - (path /57D855DE/58023EAD) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 72.5 -86.5 180) + (path /57D84708/580240BA) (attr smd) - (fp_text reference C146 (at 0 0) (layer F.SilkS) hide + (fp_text reference C7 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 202 PWR_18V)) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 55.4736 -73.406 90) - (path /57D855DE/58023EA5) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 76.25 -87.75 270) + (path /57D84708/580240B9) (attr smd) - (fp_text reference C147 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C13 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 2 15V_STABLE)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 58.9534 -64.8462 180) - (path /57D855DE/58023EAC) + (module Cryptech_Alpha_Footprints:C_0805 (layer B.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 29.718 -26.5684 270) + (path /57D849FD/5802406E) (attr smd) - (fp_text reference C150 (at 0 0) (layer F.SilkS) hide + (fp_text reference C26 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 10uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 0.762) (end 1.651 0.762) (layer B.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end 1.651 -0.762) (layer B.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end -1.651 -0.762) (layer B.Fab) (width 0.1)) + (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 58.9534 -70.8914) - (path /57D855DE/58023EA4) + (module Cryptech_Alpha_Footprints:C_0805 (layer B.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 45.6946 -51.3334 180) + (path /57D849FD/58024063) (attr smd) - (fp_text reference C151 (at 0 0) (layer F.SilkS) hide + (fp_text reference C27 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 10uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 0.762) (end 1.651 0.762) (layer B.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end 1.651 -0.762) (layer B.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end -1.651 -0.762) (layer B.Fab) (width 0.1)) + (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.9346 -64.8462 180) - (path /57D855DE/58023EAB) + (module Cryptech_Alpha_Footprints:C_0805 (layer B.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 19.77586 -5.96143) + (path /57D84CB3/58023FE6) (attr smd) - (fp_text reference C154 (at 0 0) (layer F.SilkS) hide + (fp_text reference C72 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 0.762) (end 1.651 0.762) (layer B.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end 1.651 -0.762) (layer B.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end -1.651 -0.762) (layer B.Fab) (width 0.1)) + (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask) + (net 144 FT_VREGIN)) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 57.4548 -65.3796 90) - (path /57D855DE/58023EA3) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 25.8074 -9.89 270) + (path /57D84CB3/58023FFC) (attr smd) - (fp_text reference C155 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C77 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 10uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 142 FT_VPHY)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 57.9374 -63.881 180) - (path /57D855DE/58023EAA) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 24.2072 -15.8844 90) + (path /57D84CB3/58023FFA) (attr smd) - (fp_text reference C158 (at 0 0) (layer F.SilkS) hide + (fp_text reference C80 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 10uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 143 FT_VPLL)) + (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 55.4228 -65.3796 270) - (path /57D855DE/58023EA2) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 7.7734 -15.0716 90) + (path /57D84CB3/58023FFF) (attr smd) - (fp_text reference C159 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C82 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 125 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 141 FT_VCC3V3)) + (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.9346 -71.9074 180) - (path /57D855DE/58023EA9) + (module Cryptech_Alpha_Footprints:C_0805 (layer B.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 78.40381 -17.07095 90) + (path /57D84E30/58023FB0) (attr smd) - (fp_text reference C162 (at 0 0) (layer F.SilkS) hide + (fp_text reference C87 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 0.762) (end 1.651 0.762) (layer B.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end 1.651 -0.762) (layer B.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end -1.651 -0.762) (layer B.Fab) (width 0.1)) + (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer B.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer B.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask) + (net 137 FT_MGMT_VREGIN)) + (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 59.436 -72.39 90) - (path /57D855DE/58023EA8) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 86.419 -7.0668 270) + (path /57D84E30/58023FC6) (attr smd) - (fp_text reference C163 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C92 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 10uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 135 FT_MGMT_VPHY)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.96 -72.898) - (path /57D855DE/58023EA1) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 91.186 -7.207 270) + (path /57D84E30/58023FC4) (attr smd) - (fp_text reference C164 (at 0 0) (layer F.SilkS) hide + (fp_text reference C95 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 10uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 126 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 136 FT_MGMT_VPLL)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 48.4378 -62.3824 270) - (path /57D8583B/58023E5E) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 90 -25 180) + (path /57D84E30/58023FC9) (attr smd) - (fp_text reference C181 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C97 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 134 FT_MGMT_VCC3V3)) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 47.9552 -59.8678) - (path /57D8583B/58023E3B) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 52.07 -83.0072) + (path /57D855DE/58023E94) (attr smd) - (fp_text reference C182 (at 0 0) (layer F.SilkS) hide + (fp_text reference C132 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 53.467 -79.4258 90) - (path /57D8583B/58023E37) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 43.9928 -71.6788 270) + (path /57D855DE/58023E93) (attr smd) - (fp_text reference C183 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C136 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 61.9506 -61.9244 180) - (path /57D8583B/58023E5A) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 52.07 -85.725) + (path /57D855DE/58023E92) (attr smd) - (fp_text reference C184 (at 0 0) (layer F.SilkS) hide + (fp_text reference C139 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_VCCAUX_1V8)) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 49.9364 -69.8754 180) - (path /57D8583B/58023E56) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 61.849 -81.5594) + (path /57D855DE/58023EB1) (attr smd) - (fp_text reference C185 (at 0 0) (layer F.SilkS) hide + (fp_text reference C140 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 55.4736 -75.4126 90) - (path /57D8583B/58023E51) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 60.1218 -55.118 270) + (path /57D855DE/58023E9A) (attr smd) - (fp_text reference C186 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C141 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 44.6786 -63.3984 270) - (path /57D8583B/58023E53) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 71.6788 -71.0184 90) + (path /57D855DE/58023EA0) (attr smd) - (fp_text reference C187 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C144 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 53.0098 -56.9976 180) - (path /57D8583B/58023E3A) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 43.9166 -67.1068 270) + (path /57D855DE/58023E99) (attr smd) - (fp_text reference C188 (at 0 0) (layer F.SilkS) hide + (fp_text reference C145 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 52.451 -75.3872 270) - (path /57D8583B/58023E5D) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 41.4274 -67.1068 270) + (path /57D855DE/58023E9F) (attr smd) - (fp_text reference C189 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C148 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 67.818 -64.7446) - (path /57D8583B/58023E59) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 69.2658 -70.9676 90) + (path /57D855DE/58023E98) (attr smd) - (fp_text reference C190 (at 0 0) (layer F.SilkS) hide + (fp_text reference C149 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 52.959 -67.9196 180) - (path /57D8583B/58023E55) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 57.3024 -84.0232 180) + (path /57D855DE/58023E9E) (attr smd) - (fp_text reference C191 (at 0 0) (layer F.SilkS) hide + (fp_text reference C152 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) - ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 46.4312 -78.4098 90) - (path /57D8583B/58023E50) - (attr smd) - (fp_text reference C192 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 49.4538 -66.3956 90) - (path /57D8583B/58023E48) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 70.485 -66.6496 270) + (path /57D855DE/58023E97) (attr smd) - (fp_text reference C193 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C153 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 49.9364 -58.9026 180) - (path /57D8583B/58023E39) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 56.7436 -53.7972 180) + (path /57D855DE/58023E9D) (attr smd) - (fp_text reference C194 (at 0 0) (layer F.SilkS) hide + (fp_text reference C156 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 48.9458 -76.9112 180) - (path /57D8583B/58023E5C) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 57.3024 -81.5594 180) + (path /57D855DE/58023E96) (attr smd) - (fp_text reference C195 (at 0 0) (layer F.SilkS) hide + (fp_text reference C157 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 60.452 -62.4078 270) - (path /57D8583B/58023E58) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 41.402 -71.6788 90) + (path /57D855DE/58023E9C) (attr smd) - (fp_text reference C196 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C160 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 47.9552 -67.8942) - (path /57D8583B/58023E54) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 56.769 -56.1848 180) + (path /57D855DE/58023E95) (attr smd) - (fp_text reference C197 (at 0 0) (layer F.SilkS) hide + (fp_text reference C161 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 126 FPGA_VCCINT_1V0)) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 50.927 -80.7974) - (path /57D8583B/58023E4F) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 63.246 -54.74298 270) + (path /57D8583B/58023E4D) (attr smd) - (fp_text reference C198 (at 0 0) (layer F.SilkS) hide + (fp_text reference C169 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 63.9318 -67.8942 180) - (path /57D8583B/58023E3D) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 42.7736 -82.0674 180) + (path /57D8583B/58023E4A) (attr smd) - (fp_text reference C199 (at 0 0) (layer F.SilkS) hide + (fp_text reference C170 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 50.9524 -61.8998 180) - (path /57D8583B/58023E38) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 42.8244 -79.2734 180) + (path /57D8583B/58023E49) (attr smd) - (fp_text reference C200 (at 0 0) (layer F.SilkS) hide + (fp_text reference C171 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 51.4604 -72.39 270) - (path /57D8583B/58023E5B) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 40.1574 -63.0428 270) + (path /57D8583B/58023E45) (attr smd) - (fp_text reference C201 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C172 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 67.4624 -67.3862 90) - (path /57D8583B/58023E57) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 42.5958 -63.0428 270) + (path /57D8583B/58023E44) (attr smd) - (fp_text reference C202 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C173 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 45.9486 -66.8782 180) - (path /57D8583B/58023E52) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 52.2986 -54.9148 180) + (path /57D8583B/58023E41) (attr smd) - (fp_text reference C203 (at 0 0) (layer F.SilkS) hide + (fp_text reference C174 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 44.59546 -75.27194 90) - (path /57D8583B/58023E4E) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 69.2658 -78.9432 90) + (path /57D8583B/58023E4C) (attr smd) - (fp_text reference C204 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C175 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.47uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 210 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 24.4856 -62.8904 180) - (path /57D85A75/58023E28) - (attr smd) - (fp_text reference C207 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 0.047uF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 165 "Net-(C207-Pad1)")) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) - (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) - (rotate (xyz 270 360 0)) - ) - (model wrlshp/ECAF1ED8-FCC0.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 360)) - ) - ) - - (module Cryptech_Alpha_Footprints:C_0402 (layer B.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 26.924 -62.8904 180) - (path /57D85A75/58023E23) - (attr smd) - (fp_text reference C208 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text value 27pF (at 0 0) (layer Cmts.User) - (effects (font (size 1.524 1.524) (thickness 0.05))) - ) - (fp_text user %R (at 0 0) (layer B.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025)) (justify mirror)) - ) - (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end -0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end 0.762 -0.381) (layer B.Fab) (width 0.1)) - (fp_line (start -0.762 0.381) (end 0.762 0.381) (layer B.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 166 "Net-(C208-Pad1)")) - (pad 2 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) - (net 167 "Net-(C208-Pad2)")) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 24.003 -63.0936 90) - (path /57D85B19/58023E13) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 65.4558 -55.118 270) + (path /57D8583B/58023E4B) (attr smd) - (fp_text reference C211 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C176 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 204 PWR_ENA_VCCINT)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 14.8336 -47.2694 90) - (path /57D85B19/58023E12) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 66.1162 -81.5594) + (path /57D8583B/58023E47) (attr smd) - (fp_text reference C212 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C177 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 205 PWR_ENA_VCCO)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 30.9118 -76.327 90) - (path /57D85B19/58023E11) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 42.6212 -75.9206 90) + (path /57D8583B/58023E46) (attr smd) - (fp_text reference C213 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C178 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 203 PWR_ENA_VCCAUX)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 1 0 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 36 -14.5 90) - (path /57D84CB3/58023FEE) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 69.2658 -74.8284 270) + (path /57D8583B/58023E43) (attr smd) - (fp_text reference C214 (at 0 0 90) (layer F.SilkS) hide + (fp_text reference C179 (at 0 0 90) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0 90) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0 90) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0 90) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 144 FT_VREGIN)) - (pad 2 smd rect (at 0.5 0 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 1 0 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) ) ) - (module Cryptech_Alpha_Footprints:C_0402 (layer F.Cu) (tedit 60BD3CB0) (tstamp 539EEDBF) - (at 72.9 -16.7) - (path /57D84E30/58023FB8) + (module Cryptech_Alpha_Footprints:C_0805 (layer F.Cu) (tedit 60BDC58A) (tstamp 539EEDBF) + (at 47.4472 -56.0832) + (path /57D8583B/58023E42) (attr smd) - (fp_text reference C215 (at 0 0) (layer F.SilkS) hide + (fp_text reference C180 (at 0 0) (layer F.SilkS) hide (effects (font (size 1.524 1.524) (thickness 0.05))) ) - (fp_text value 0.1uF (at 0 0) (layer Cmts.User) + (fp_text value 4.7uF (at 0 0) (layer Cmts.User) (effects (font (size 1.524 1.524) (thickness 0.05))) ) + (fp_line (start -1.651 -0.762) (end 1.651 -0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start 1.651 0.762) (end -1.651 0.762) (layer F.Fab) (width 0.1)) + (fp_line (start -1.651 0.762) (end -1.651 -0.762) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.3 0.3) (thickness 0.025))) + (effects (font (size 0.8 0.8) (thickness 0.1))) ) - (fp_line (start -0.762 0.381) (end -0.762 -0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 0.381) (end -0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.Fab) (width 0.1)) - (fp_line (start -0.762 -0.381) (end 0.762 -0.381) (layer F.Fab) (width 0.1)) - (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) - (net 137 FT_MGMT_VREGIN)) - (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 210 VCCO_3V3)) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 GND)) - (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" - (at (xyz 0 -0 0)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) (rotate (xyz 270 360 0)) ) - (model wrlshp/ECAF1ED8-FCC0.wrl + (model wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 360)) @@ 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2.5) (end -2.5 3.5) (layer B.Fab) (width 0.1)) - (fp_line (start -4.12 4.12) (end -4.12 -4.12) (layer B.CrtYd) (width 0.05)) - (fp_line (start -4.12 -4.12) (end 4.12 -4.12) (layer B.CrtYd) (width 0.05)) - (fp_line (start 4.12 -4.12) (end 4.12 4.12) (layer B.CrtYd) (width 0.05)) (fp_line (start 4.12 4.12) (end -4.12 4.12) (layer B.CrtYd) (width 0.05)) + (fp_line (start 4.12 -4.12) (end 4.12 4.12) (layer B.CrtYd) (width 0.05)) + (fp_line (start -4.12 -4.12) (end 4.12 -4.12) (layer B.CrtYd) (width 0.05)) + (fp_line (start -4.12 4.12) (end -4.12 -4.12) (layer B.CrtYd) (width 0.05)) + (fp_line (start -3.5 2.5) (end -2.5 3.5) (layer B.Fab) (width 0.1)) + (fp_line (start -3.5 -3.5) (end -3.5 2.5) (layer B.Fab) (width 0.1)) + (fp_line (start 3.5 -3.5) (end -3.5 -3.5) (layer B.Fab) (width 0.1)) + (fp_line (start 3.5 3.5) (end 3.5 -3.5) (layer B.Fab) (width 0.1)) + (fp_line (start -2.5 3.5) (end 3.5 3.5) (layer B.Fab) (width 0.1)) + (fp_line (start -3.135 3.61) (end -3.61 3.61) (layer B.SilkS) (width 0.12)) + (fp_line (start 3.61 -3.61) (end 3.61 -3.135) (layer B.SilkS) (width 0.12)) + (fp_line (start 3.135 -3.61) (end 3.61 -3.61) (layer B.SilkS) (width 0.12)) + (fp_line (start -3.61 -3.61) (end -3.61 -3.135) (layer B.SilkS) (width 0.12)) + (fp_line (start -3.135 -3.61) (end -3.61 -3.61) (layer B.SilkS) (width 0.12)) + (fp_line (start 3.61 3.61) (end 3.61 3.135) (layer B.SilkS) (width 0.12)) + (fp_line (start 3.135 3.61) (end 3.61 3.61) (layer B.SilkS) (width 0.12)) (fp_text user %R (at 0 0) (layer B.Fab) (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) @@ -16787,21 +16787,21 @@ (fp_text value PLS-8 (at 0 20.11) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.8 19.55) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.8 19.55) (end 1.8 19.55) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.8 -1.8) (end -1.8 19.55) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.33 1.27) (end 1.33 19.11) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end -1.33 19.11) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 19.11) (end 1.33 19.11) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 19.05) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 19.05) (end -1.27 19.05) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 -1.27) (end 1.27 19.05) (layer F.Fab) (width 0.1)) (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end 1.27 19.05) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 19.05) (end -1.27 19.05) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 19.05) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 19.11) (end 1.33 19.11) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 19.11) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end 1.33 19.11) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.8 -1.8) (end -1.8 19.55) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 19.55) (end 1.8 19.55) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 19.55) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) (fp_text user %R (at 0 8.89 90) (layer F.Fab) (effects (font (size 1 1) (thickness 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(layer F.CrtYd) (width 0.05)) + (fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer F.SilkS) (width 0.12)) + (fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1)) + (fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1)) + (fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1)) + (fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) (effects (font (size 0.5 0.5) (thickness 0.08))) ) @@ -16876,16 +16876,16 @@ (fp_text value 100 (at 0 1.65) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1)) - (fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1)) - (fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1)) - (fp_line (start 1 0.6) (end -1 0.6) (layer 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(layer F.Fab) (width 0.1)) + (fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1)) + (fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1)) (fp_text user %R (at 0 0) (layer F.Fab) (effects (font (size 0.5 0.5) (thickness 0.08))) ) @@ -16912,16 +16912,16 @@ (fp_text value 100 (at 0 1.65) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1)) - (fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1)) - (fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1)) - (fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1)) - (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer F.SilkS) (width 0.12)) - (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.68 -0.95) (end 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F.Fab) (width 0.15)) + (gr_line (start 21.0576 -8.7724) (end 21.59 -8.128) (layer F.Fab) (width 0.15)) + (gr_line (start 32.258 -45.212) (end 32.258 -43.434) (layer F.Fab) (width 0.15)) + (gr_line (start 32.004 -45.212) (end 32.258 -45.212) (layer F.Fab) (width 0.15)) + (gr_line (start 30.226 -45.212) (end 32.004 -45.212) (layer F.Fab) (width 0.15)) (gr_line (start 92.456 -37.592) (end 74.168 -37.592) (layer F.SilkS) (width 0.15) (tstamp 5F5F7446)) (gr_line (start 94.67 -35.33) (end 92.456 -37.592) (layer F.SilkS) (width 0.15)) (gr_line (start 61.468 -46.736) (end 61.468 -45.212) (layer F.SilkS) (width 0.15) (tstamp 5F5F73C1)) @@ -31572,7 +31625,7 @@ (segment (start 81.534 -81.28) (end 83.312 -79.502) (width 0.15) (layer In5.Cu) (net 616)) (segment (start 83.312 -79.502) (end 83.312 -76.962) (width 0.15) (layer In5.Cu) (net 616)) - (zone (net 161) (net_name "Net-(C117-Pad1)") (layer B.Cu) (tstamp 60BE95A9) (hatch edge 0.508) + (zone (net 161) (net_name "Net-(C117-Pad1)") (layer B.Cu) (tstamp 60BEE935) (hatch edge 0.508) (priority 47) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31601,7 +31654,7 @@ ) ) ) - (zone (net 202) (net_name PWR_18V) (layer B.Cu) (tstamp 60BE95A6) (hatch edge 0.508) + (zone (net 202) (net_name PWR_18V) (layer B.Cu) (tstamp 60BEE932) (hatch edge 0.508) (priority 65) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31624,7 +31677,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BE95A3) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BEE92F) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31647,7 +31700,7 @@ ) ) ) - (zone (net 166) (net_name "Net-(C208-Pad1)") (layer B.Cu) (tstamp 60BE95A0) (hatch edge 0.508) + (zone (net 166) (net_name "Net-(C208-Pad1)") (layer B.Cu) (tstamp 60BEE92C) (hatch edge 0.508) (priority 59) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31677,7 +31730,7 @@ ) ) ) - (zone (net 125) (net_name FPGA_VCCAUX_1V8) (layer B.Cu) (tstamp 60BE959D) (hatch edge 0.508) + (zone (net 125) (net_name FPGA_VCCAUX_1V8) (layer B.Cu) (tstamp 60BEE929) (hatch edge 0.508) (priority 58) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31696,7 +31749,7 @@ ) ) ) - (zone (net 126) (net_name FPGA_VCCINT_1V0) (layer B.Cu) (tstamp 60BE959A) (hatch edge 0.508) + (zone (net 126) (net_name FPGA_VCCINT_1V0) (layer B.Cu) (tstamp 60BEE926) (hatch edge 0.508) (priority 56) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31716,7 +31769,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BE9597) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BEE923) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31747,7 +31800,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BE9594) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BEE920) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31770,7 +31823,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BE9591) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BEE91D) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31796,7 +31849,7 @@ ) ) ) - (zone (net 163) (net_name "Net-(C118-Pad1)") (layer B.Cu) (tstamp 60BE958E) (hatch edge 0.508) + (zone (net 163) (net_name "Net-(C118-Pad1)") (layer B.Cu) (tstamp 60BEE91A) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31822,7 +31875,7 @@ ) ) ) - (zone (net 209) (net_name VCC_5V0) (layer B.Cu) (tstamp 60BE958B) (hatch edge 0.508) + (zone (net 209) (net_name VCC_5V0) (layer B.Cu) (tstamp 60BEE917) (hatch edge 0.508) (priority 60) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31890,7 +31943,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BE9588) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BEE914) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -31912,7 +31965,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BE9585) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BEE911) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -32158,7 +32211,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BE9582) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60BEE90E) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -32209,7 +32262,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer F.Cu) (tstamp 60BE957F) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer F.Cu) (tstamp 60BEE90B) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -32230,7 +32283,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer F.Cu) (tstamp 60BE957C) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer F.Cu) (tstamp 60BEE908) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -32291,7 +32344,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer F.Cu) (tstamp 60BE9579) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer F.Cu) (tstamp 60BEE905) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -32307,7 +32360,7 @@ ) ) ) - (zone (net 125) (net_name FPGA_VCCAUX_1V8) (layer F.Cu) (tstamp 60BE9576) (hatch edge 0.508) + (zone (net 125) (net_name FPGA_VCCAUX_1V8) (layer F.Cu) (tstamp 60BEE902) (hatch edge 0.508) (priority 53) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -32323,7 +32376,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer F.Cu) (tstamp 60BE9573) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer F.Cu) (tstamp 60BEE8FF) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -32542,7 +32595,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer In2.Cu) (tstamp 60BE9570) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer In2.Cu) (tstamp 60BEE8FC) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -38637,7 +38690,7 @@ ) ) ) - (zone (net 202) (net_name PWR_18V) (layer In2.Cu) (tstamp 60BE956D) (hatch edge 0.508) + (zone (net 202) (net_name PWR_18V) (layer In2.Cu) (tstamp 60BEE8F9) (hatch edge 0.508) (priority 46) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -38698,7 +38751,7 @@ ) ) ) - (zone (net 202) (net_name PWR_18V) (layer In5.Cu) (tstamp 60BE956A) (hatch edge 0.508) + (zone (net 202) (net_name PWR_18V) (layer In5.Cu) (tstamp 60BEE8F6) (hatch edge 0.508) (priority 45) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -38759,7 +38812,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer In1.Cu) (tstamp 60BE9567) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer In1.Cu) (tstamp 60BEE8F3) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -45945,7 +45998,7 @@ ) ) ) - (zone (net 126) (net_name FPGA_VCCINT_1V0) (layer In4.Cu) (tstamp 60BE9564) (hatch edge 0.508) + (zone (net 126) (net_name FPGA_VCCINT_1V0) (layer In4.Cu) (tstamp 60BEE8F0) (hatch edge 0.508) (priority 100) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -49003,7 +49056,7 @@ ) ) ) - (zone (net 125) (net_name FPGA_VCCAUX_1V8) (layer In4.Cu) (tstamp 60BE9561) (hatch edge 0.508) + (zone (net 125) (net_name FPGA_VCCAUX_1V8) (layer In4.Cu) (tstamp 60BEE8ED) (hatch edge 0.508) (priority 100) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -49495,7 +49548,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer In4.Cu) (tstamp 60BE955E) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer In4.Cu) (tstamp 60BEE8EA) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -51645,7 +51698,7 @@ ) ) ) - (zone (net 202) (net_name PWR_18V) (layer In4.Cu) (tstamp 60BE955B) (hatch edge 0.508) + (zone (net 202) (net_name PWR_18V) (layer In4.Cu) (tstamp 60BEE8E7) (hatch edge 0.508) (priority 100) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -51766,7 +51819,7 @@ ) ) ) - (zone (net 141) (net_name FT_VCC3V3) (layer In4.Cu) (tstamp 60BE9558) (hatch edge 0.508) + (zone (net 141) (net_name FT_VCC3V3) (layer In4.Cu) (tstamp 60BEE8E4) (hatch edge 0.508) (priority 100) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -52137,7 +52190,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer In6.Cu) (tstamp 60BE9555) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer In6.Cu) (tstamp 60BEE8E1) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -59323,7 +59376,7 @@ ) ) ) - (zone (net 0) (net_name "") (layer B.Paste) (tstamp 60BE9552) (hatch edge 0.508) + (zone (net 0) (net_name "") (layer B.Paste) (tstamp 60BEE8DE) (hatch edge 0.508) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) (fill yes (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.512)) @@ -59338,7 +59391,7 @@ ) ) ) - (zone (net 0) (net_name "") (layer B.Paste) (tstamp 60BE954F) (hatch edge 0.508) + (zone (net 0) (net_name "") (layer B.Paste) (tstamp 60BEE8DB) (hatch edge 0.508) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) (fill yes (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.512)) @@ -59353,7 +59406,7 @@ ) ) ) - (zone (net 0) (net_name "") (layer B.Paste) (tstamp 60BE954C) (hatch edge 0.508) + (zone (net 0) (net_name "") (layer B.Paste) (tstamp 60BEE8D8) (hatch edge 0.508) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) (fill yes (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.512)) @@ -59368,7 +59421,7 @@ ) ) ) - (zone (net 210) (net_name VCCO_3V3) (layer In3.Cu) (tstamp 60BE9549) (hatch edge 0.508) + (zone (net 210) (net_name VCCO_3V3) (layer In3.Cu) (tstamp 60BEE8D5) (hatch edge 0.508) (priority 100) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -68942,7 +68995,7 @@ ) ) ) - (zone (net 3) (net_name GND) (layer In5.Cu) (tstamp 60BE9546) (hatch edge 0.508) + (zone (net 3) (net_name GND) (layer In5.Cu) (tstamp 60BEE8D2) (hatch edge 0.508) (priority 40) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -74541,7 +74594,7 @@ ) ) ) - (zone (net 1) (net_name 3V3_BATT) (layer In4.Cu) (tstamp 60BE9543) (hatch edge 0.508) + (zone (net 1) (net_name 3V3_BATT) (layer In4.Cu) (tstamp 60BEE8CF) (hatch edge 0.508) (priority 100) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -76498,7 +76551,7 @@ ) ) ) - (zone (net 134) (net_name FT_MGMT_VCC3V3) (layer In4.Cu) (tstamp 60BE9540) (hatch edge 0.508) + (zone (net 134) (net_name FT_MGMT_VCC3V3) (layer In4.Cu) (tstamp 60BEE8CC) (hatch edge 0.508) (priority 100) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) @@ -76820,7 +76873,7 @@ ) ) ) - (zone (net 571) (net_name "/Master Key Memory/MKM_VCC") (layer In5.Cu) (tstamp 60BE953D) (hatch edge 0.508) + (zone (net 571) (net_name "/Master Key Memory/MKM_VCC") (layer In5.Cu) (tstamp 60BEE8C9) (hatch edge 0.508) (priority 50) (connect_pads thru_hole_only (clearance 0.127)) (min_thickness 0.127) diff --git a/KiCAD/fp-info-cache b/KiCAD/fp-info-cache index 3029d35..bb85bd1 100644 --- a/KiCAD/fp-info-cache +++ b/KiCAD/fp-info-cache @@ -1,4 +1,4 @@ -18561129476945446 +18561839811122257 Battery BatteryHolder_Bulgin_BX0036_1xC Bulgin Battery Holder, BX0036, Battery Type C (https://www.bulgin.com/products/pub/media/bulgin/data/Battery_holders.pdf) |