summaryrefslogtreecommitdiff
path: root/KiCAD/rev04_24.sch-bak
diff options
context:
space:
mode:
Diffstat (limited to 'KiCAD/rev04_24.sch-bak')
-rw-r--r--KiCAD/rev04_24.sch-bak506
1 files changed, 506 insertions, 0 deletions
diff --git a/KiCAD/rev04_24.sch-bak b/KiCAD/rev04_24.sch-bak
new file mode 100644
index 0000000..29d7929
--- /dev/null
+++ b/KiCAD/rev04_24.sch-bak
@@ -0,0 +1,506 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr B 17000 11000
+encoding utf-8
+Sheet 26 27
+Title "rev04_24"
+Date "15 10 2016"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Text Notes 4800 2800 0 60 ~ 12
+*) FPGA Power Subsystem -- CORE
+Text Notes 7650 4010 0 60 ~ 12
+*) VCCINT = 0.6V x (1 + 150 / 226) = 0.998V\n*) OCP_ADJ is not used (default over-current threshold)\n*) MARx are not used (output at nominal 100%)\n*) S_IN/S_OUT are not used (single regulator mode)\n*) S_DELAY is not used (single regulator mode)\n*) M/S is not used (parallel operation not needed)\n*) EA_OUT is not used (default control loop)\n*) Minimal load current is 0A, but we still place\nload of 100 Ohms just in case (gives 10 mA)
+Text Notes 6770 1400 0 54 ~ 11
+FPGA CORE voltage regulators
+Text Notes 3370 5380 0 60 ~ 12
+R66
+Text Notes 2360 5290 0 60 ~ 12
+C205
+Text Notes 2360 5490 0 60 ~ 12
+22~uF
+Text Notes 2760 5290 0 60 ~ 12
+C206
+Text Notes 2760 5490 0 60 ~ 12
+22~uF
+Text Notes 6160 5330 0 60 ~ 12
+R68
+Text Notes 6150 5960 0 60 ~ 12
+R69
+Text Notes 6830 5290 0 60 ~ 12
+C208
+Text Notes 6830 5380 0 60 ~ 12
+27pF
+Text Notes 8190 5790 0 60 ~ 12
+R70
+Text Notes 5760 5980 0 60 ~ 12
+R67
+Text Notes 7160 5790 0 60 ~ 12
+C209
+Text Notes 7160 5990 0 60 ~ 12
+47uF
+Text Notes 7660 5790 0 60 ~ 12
+C210
+Text Notes 7660 5990 0 60 ~ 12
+47uF
+$Comp
+L power:GND #GND_0216
+U 1 1 58023E36
+P 4700 8200
+F 0 "#GND_0216" H 4700 8200 20 0000 C CNN
+F 1 "+GND" H 4700 8130 30 0000 C CNN
+F 2 "" H 4700 8200 70 0000 C CNN
+F 3 "" H 4700 8200 70 0000 C CNN
+ 1 4700 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #GND_0217
+U 1 1 58023E35
+P 5200 8200
+F 0 "#GND_0217" H 5200 8200 20 0000 C CNN
+F 1 "+GND" H 5200 8130 30 0000 C CNN
+F 2 "" H 5200 8200 70 0000 C CNN
+F 3 "" H 5200 8200 70 0000 C CNN
+ 1 5200 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #GND_0218
+U 1 1 58023E34
+P 3900 8200
+F 0 "#GND_0218" H 3900 8200 20 0000 C CNN
+F 1 "+GND" H 3900 8130 30 0000 C CNN
+F 2 "" H 3900 8200 70 0000 C CNN
+F 3 "" H 3900 8200 70 0000 C CNN
+ 1 3900 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #GND_0219
+U 1 1 58023E33
+P 2300 5700
+F 0 "#GND_0219" H 2300 5700 20 0000 C CNN
+F 1 "+GND" H 2300 5630 30 0000 C CNN
+F 2 "" H 2300 5700 70 0000 C CNN
+F 3 "" H 2300 5700 70 0000 C CNN
+ 1 2300 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #GND_0220
+U 1 1 58023E32
+P 2700 5700
+F 0 "#GND_0220" H 2700 5700 20 0000 C CNN
+F 1 "+GND" H 2700 5630 30 0000 C CNN
+F 2 "" H 2700 5700 70 0000 C CNN
+F 3 "" H 2700 5700 70 0000 C CNN
+ 1 2700 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #GND_0221
+U 1 1 58023E31
+P 6400 6300
+F 0 "#GND_0221" H 6400 6300 20 0000 C CNN
+F 1 "+GND" H 6400 6230 30 0000 C CNN
+F 2 "" H 6400 6300 70 0000 C CNN
+F 3 "" H 6400 6300 70 0000 C CNN
+ 1 6400 6300
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #GND_0222
+U 1 1 58023E30
+P 7100 6300
+F 0 "#GND_0222" H 7100 6300 20 0000 C CNN
+F 1 "+GND" H 7100 6230 30 0000 C CNN
+F 2 "" H 7100 6300 70 0000 C CNN
+F 3 "" H 7100 6300 70 0000 C CNN
+ 1 7100 6300
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #GND_0223
+U 1 1 58023E2F
+P 7600 6300
+F 0 "#GND_0223" H 7600 6300 20 0000 C CNN
+F 1 "+GND" H 7600 6230 30 0000 C CNN
+F 2 "" H 7600 6300 70 0000 C CNN
+F 3 "" H 7600 6300 70 0000 C CNN
+ 1 7600 6300
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #GND_0224
+U 1 1 58023E2E
+P 8100 6300
+F 0 "#GND_0224" H 8100 6300 20 0000 C CNN
+F 1 "+GND" H 8100 6230 30 0000 C CNN
+F 2 "" H 8100 6300 70 0000 C CNN
+F 3 "" H 8100 6300 70 0000 C CNN
+ 1 8100 6300
+ 1 0 0 -1
+$EndComp
+$Comp
+L Cryptech_Alpha:VCC_5V0 #VCC_5V0_03
+U 1 1 58023E2D
+P 2100 4900
+F 0 "#VCC_5V0_03" H 2100 4900 20 0000 C CNN
+F 1 "+VCC_5V0" H 2100 4830 30 0000 C CNN
+F 2 "" H 2100 4900 70 0000 C CNN
+F 3 "" H 2100 4900 70 0000 C CNN
+ 1 2100 4900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3900 8100 3900 8200
+Wire Wire Line
+ 2300 5500 2300 5700
+Wire Wire Line
+ 2700 5500 2700 5700
+Wire Wire Line
+ 6400 6200 6400 6300
+Wire Wire Line
+ 7100 6000 7100 6300
+Wire Wire Line
+ 7600 6000 7600 6300
+Wire Wire Line
+ 8100 6100 8100 6300
+Wire Wire Line
+ 8800 5100 8650 5100
+Text Label 8800 5100 0 48 ~ 0
+FPGA_VCCINT_1V0
+Wire Wire Line
+ 2100 4900 2100 5100
+Wire Wire Line
+ 3900 5100 3900 5300
+Wire Wire Line
+ 4100 5100 3900 5100
+Wire Wire Line
+ 4100 5300 3900 5300
+Wire Wire Line
+ 3900 5100 3300 5100
+Wire Wire Line
+ 3300 5100 2700 5100
+Wire Wire Line
+ 2700 5100 2300 5100
+Wire Wire Line
+ 2300 5100 2300 5200
+Wire Wire Line
+ 2700 5100 2700 5200
+Wire Wire Line
+ 3300 5100 3300 5200
+Wire Wire Line
+ 2300 5100 2100 5100
+Connection ~ 3900 5100
+Connection ~ 2700 5100
+Connection ~ 3300 5100
+Connection ~ 2300 5100
+Wire Wire Line
+ 6100 7800 5800 7800
+Text GLabel 6100 7800 2 48 Output ~ 0
+POK_VCCINT
+Wire Wire Line
+ 4100 7800 3900 7800
+Wire Wire Line
+ 4100 5700 3300 5700
+Wire Wire Line
+ 3300 5600 3300 5700
+Wire Wire Line
+ 4100 5500 3700 5500
+Wire Wire Line
+ 3700 4600 3700 5500
+Wire Wire Line
+ 3700 4600 3200 4600
+Text GLabel 3200 4600 0 48 Input ~ 0
+PWR_ENA_VCCINT
+Wire Wire Line
+ 6000 6300 5800 6300
+Wire Wire Line
+ 6000 6200 6000 6300
+Wire Wire Line
+ 6000 5100 6000 5800
+Wire Wire Line
+ 6000 5100 5800 5100
+Wire Wire Line
+ 6400 5100 6000 5100
+Wire Wire Line
+ 6400 5100 6400 5200
+Wire Wire Line
+ 6700 5100 6400 5100
+Wire Wire Line
+ 6700 5100 6700 5200
+Wire Wire Line
+ 7100 5100 7100 5700
+Wire Wire Line
+ 7100 5100 6700 5100
+Wire Wire Line
+ 7600 5100 7600 5700
+Wire Wire Line
+ 7600 5100 7100 5100
+Wire Wire Line
+ 8100 5100 8100 5700
+Wire Wire Line
+ 8100 5100 7600 5100
+Wire Wire Line
+ 8200 5100 8100 5100
+Connection ~ 6000 5100
+Connection ~ 6400 5100
+Connection ~ 6700 5100
+Connection ~ 7100 5100
+Connection ~ 7600 5100
+Connection ~ 8100 5100
+Wire Wire Line
+ 6400 5700 5800 5700
+Wire Wire Line
+ 6400 5600 6400 5700
+Wire Wire Line
+ 6400 5700 6400 5800
+Wire Wire Line
+ 6700 5700 6400 5700
+Wire Wire Line
+ 6700 5500 6700 5700
+Connection ~ 6400 5700
+Text Notes 4400 4100 0 72 ~ 14
+U16
+Wire Wire Line
+ 4100 4300 4100 4200
+Wire Wire Line
+ 4100 4400 4100 4300
+Wire Wire Line
+ 4100 4500 4100 4400
+Wire Wire Line
+ 4100 4600 4100 4500
+Wire Wire Line
+ 4100 4700 4100 4600
+Wire Wire Line
+ 4100 4800 4100 4700
+Wire Wire Line
+ 4100 4900 4100 4800
+Wire Wire Line
+ 4100 5000 4100 4900
+Wire Wire Line
+ 4100 5100 4100 5000
+Wire Wire Line
+ 5800 4400 5800 4300
+Wire Wire Line
+ 5800 4500 5800 4400
+Wire Wire Line
+ 5800 4600 5800 4500
+Wire Wire Line
+ 5800 4700 5800 4600
+Wire Wire Line
+ 5800 4800 5800 4700
+Wire Wire Line
+ 5800 4900 5800 4800
+Wire Wire Line
+ 5800 5000 5800 4900
+Wire Wire Line
+ 5800 5100 5800 5000
+Text Notes 3610 7870 0 60 ~ 12
+C116
+Text Notes 3300 8070 0 60 ~ 12
+0.047~uF
+Connection ~ 4100 5100
+Connection ~ 4100 5000
+Connection ~ 4100 4900
+Connection ~ 4100 4800
+Connection ~ 4100 4700
+Connection ~ 4100 4600
+Connection ~ 4100 4500
+Connection ~ 4100 4400
+Connection ~ 4100 4300
+Connection ~ 5800 5100
+Connection ~ 5800 5000
+Connection ~ 5800 4900
+Connection ~ 5800 4800
+Connection ~ 5800 4700
+Connection ~ 5800 4600
+Connection ~ 5800 4500
+Connection ~ 5800 4400
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R66
+U 1 1 58023E2C
+P 3300 5400
+F 0 "R66" V 3210 5355 60 0000 R TNN
+F 1 "4.7k" V 3230 5330 60 0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 3230 5330 60 0001 C CNN
+F 3 "" H 3230 5330 60 0000 C CNN
+ 1 3300 5400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L Cryptech_Alpha:C-EUC1210 C209
+U 1 1 58023E2B
+P 7100 5800
+F 0 "C209" H 7180 5610 60 0000 L BNN
+F 1 "~" H 7100 5800 50 0001 C CNN
+F 2 "Cryptech_Alpha_Footprints:C_1210" H 7180 5610 60 0001 C CNN
+F 3 "" H 7100 5800 50 0001 C CNN
+ 1 7100 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L Cryptech_Alpha:C-EUC1210 C210
+U 1 1 58023E2A
+P 7600 5800
+F 0 "C210" H 7680 5610 60 0000 L BNN
+F 1 "~" H 7600 5800 50 0001 C CNN
+F 2 "Cryptech_Alpha_Footprints:C_1210" H 7680 5610 60 0001 C CNN
+F 3 "" H 7600 5800 50 0001 C CNN
+ 1 7600 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L Cryptech_Alpha:EN5364QI U16
+U 1 1 58023E29
+P 4900 6400
+F 0 "U16" H 4450 8720 60 0000 L BNN
+F 1 "EN5364QI" H 5010 8730 60 0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:QFN68" H 5010 8730 60 0001 C CNN
+F 3 "" H 5010 8730 60 0000 C CNN
+ 1 4900 6400
+ 1 0 0 -1
+$EndComp
+$Comp
+L Cryptech_Alpha:C-EUC0402 C207
+U 1 1 58023E28
+P 3900 7900
+F 0 "C207" H 3300 7850 60 0000 L BNN
+F 1 "~" H 3900 7900 50 0001 C CNN
+F 2 "Cryptech_Alpha_Footprints:C_0402" H 3300 7850 60 0001 C CNN
+F 3 "" H 3900 7900 50 0001 C CNN
+ 1 3900 7900
+ 1 0 0 -1
+$EndComp
+$Comp
+L Cryptech_Alpha:C-EUC1210 C205
+U 1 1 58023E27
+P 2300 5300
+F 0 "C205" H 2380 5110 60 0000 L BNN
+F 1 "~" H 2300 5300 50 0001 C CNN
+F 2 "Cryptech_Alpha_Footprints:C_1210" H 2380 5110 60 0001 C CNN
+F 3 "" H 2300 5300 50 0001 C CNN
+ 1 2300 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L Cryptech_Alpha:C-EUC1210 C206
+U 1 1 58023E26
+P 2700 5300
+F 0 "C206" H 2780 5110 60 0000 L BNN
+F 1 "~" H 2700 5300 50 0001 C CNN
+F 2 "Cryptech_Alpha_Footprints:C_1210" H 2780 5110 60 0001 C CNN
+F 3 "" H 2700 5300 50 0001 C CNN
+ 1 2700 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R68
+U 1 1 58023E25
+P 6400 5400
+F 0 "R68" V 6310 5355 60 0000 R TNN
+F 1 "150k" V 6370 5650 60 0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 6370 5650 60 0001 C CNN
+F 3 "" H 6370 5650 60 0000 C CNN
+ 1 6400 5400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R69
+U 1 1 58023E24
+P 6400 6000
+F 0 "R69" V 6310 5955 60 0000 R TNN
+F 1 "226k" V 6350 6250 60 0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 6350 6250 60 0001 C CNN
+F 3 "" H 6350 6250 60 0000 C CNN
+ 1 6400 6000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L Cryptech_Alpha:C-EUC0402 C208
+U 1 1 58023E23
+P 6700 5300
+F 0 "C208" H 6780 5110 60 0000 L BNN
+F 1 "~" H 6700 5300 50 0001 C CNN
+F 2 "Cryptech_Alpha_Footprints:C_0402" H 6780 5110 60 0001 C CNN
+F 3 "" H 6700 5300 50 0001 C CNN
+ 1 6700 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L Cryptech_Alpha:BLM31PG330SN1_1206 FB7
+U 1 1 58023E22
+P 8400 5200
+F 0 "FB7" H 8250 5400 60 0000 L BNN
+F 1 "BLM31PG330SN1" H 8250 5100 60 0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:L_1206" H 8250 5100 60 0001 C CNN
+F 3 "" H 8250 5100 60 0000 C CNN
+ 1 8400 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R70
+U 1 1 58023E21
+P 8100 5900
+F 0 "R70" V 8010 5855 60 0000 R TNN
+F 1 "100" V 8110 5800 60 0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 8110 5800 60 0001 C CNN
+F 3 "" H 8110 5800 60 0000 C CNN
+ 1 8100 5900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R67
+U 1 1 58023E20
+P 6000 6000
+F 0 "R67" V 5910 5955 60 0000 R TNN
+F 1 "0" V 5940 6240 60 0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 5940 6240 60 0001 C CNN
+F 3 "" H 5940 6240 60 0000 C CNN
+ 1 6000 6000
+ 0 -1 -1 0
+$EndComp
+NoConn ~ 5800 6800
+NoConn ~ 5800 7000
+NoConn ~ 4100 6100
+NoConn ~ 4100 6300
+NoConn ~ 4100 6500
+NoConn ~ 4100 6700
+NoConn ~ 4100 6900
+NoConn ~ 4100 7400
+Wire Wire Line
+ 8800 5100 8800 4900
+$Comp
+L Cryptech_Alpha:FPGA_VCCINT_1V0 #PWR0112
+U 1 1 5AF3F25C
+P 8800 4900
+F 0 "#PWR0112" H 8800 4750 50 0001 C CNN
+F 1 "FPGA_VCCINT_1V0" H 8815 5073 50 0000 C CNN
+F 2 "" H 8800 4900 60 0000 C CNN
+F 3 "" H 8800 4900 60 0000 C CNN
+ 1 8800 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:PWR_FLAG #FLG0111
+U 1 1 5AFA77EC
+P 8650 5100
+F 0 "#FLG0111" H 8650 5175 50 0001 C CNN
+F 1 "PWR_FLAG" H 8650 5274 50 0000 C CNN
+F 2 "" H 8650 5100 50 0001 C CNN
+F 3 "~" H 8650 5100 50 0001 C CNN
+ 1 8650 5100
+ 1 0 0 -1
+$EndComp
+Connection ~ 8650 5100
+Wire Wire Line
+ 8650 5100 8600 5100
+$EndSCHEMATC