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Diffstat (limited to 'KiCAD/rev04_15.sch-bak')
| -rw-r--r-- | KiCAD/rev04_15.sch-bak | 601 |
1 files changed, 601 insertions, 0 deletions
diff --git a/KiCAD/rev04_15.sch-bak b/KiCAD/rev04_15.sch-bak new file mode 100644 index 0000000..2301053 --- /dev/null +++ b/KiCAD/rev04_15.sch-bak @@ -0,0 +1,601 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 16 27 +Title "rev04_15" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 9150 2900 0 60 ~ 12 +*) HOLD feature not used\n*) PROM is write-protected by default, to disable\nwrite protection (such as during firmware update),\njumper must be inserted +Text Notes 6850 6600 0 84 ~ 17 +FPGA clock +Text Notes 9150 2200 0 84 ~ 17 +FPGA config memory, 128 Mbit +Text Notes 3310 1930 0 84 ~ 17 +SPI mux to let ARM override access to\nFPGA config memory (to reprogram FPGA) +Text Notes 2470 4220 0 42 ~ 8 +Install this jumper to allow\nARM to configure the FPGA +Text Notes 5540 2850 0 42 ~ 8 +ARM access default\ndisabled through pull-up +Text Notes 5240 5830 0 42 ~ 8 +FPGA access default\nenabled through pull-down +Text Notes 2480 4540 0 42 ~ 8 +Install this jumper to allow\nARM to configure the FPGA +Text Notes 10570 8210 0 60 ~ 12 +FPGA supporting components +Text Notes 9950 4180 0 60 ~ 12 +IC3 +Text Notes 10510 4180 0 60 ~ 12 +N25Q128A13ES +Text Notes 9750 3900 0 60 ~ 12 +R51 +Text Notes 8850 4900 0 60 ~ 12 +R50 +Text Notes 6510 7590 0 60 ~ 12 +C111 +Text Notes 6510 7790 0 60 ~ 12 +0.01uF +Text Notes 7700 6770 2 60 ~ 12 +R49 +Text Notes 5520 2640 0 60 ~ 12 +R46 +Text Notes 5260 5520 2 60 ~ 12 +R47 +Text Notes 8500 7560 2 60 ~ 12 +R4 +Text Notes 5910 3510 0 60 ~ 12 +IC2 +Text Notes 5910 4330 0 60 ~ 12 +74*244DW +$Comp +L power:GND #GND_0102 +U 1 1 58023F4D +P 9650 5300 +F 0 "#GND_0102" H 9650 5300 20 0000 C CNN +F 1 "+GND" H 9650 5230 30 0000 C CNN +F 2 "" H 9650 5300 70 0000 C CNN +F 3 "" H 9650 5300 70 0000 C CNN + 1 9650 5300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #GND_0103 +U 1 1 58023F4C +P 8750 5300 +F 0 "#GND_0103" H 8750 5300 20 0000 C CNN +F 1 "+GND" H 8750 5230 30 0000 C CNN +F 2 "" H 8750 5300 70 0000 C CNN +F 3 "" H 8750 5300 70 0000 C CNN + 1 8750 5300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #GND_0104 +U 1 1 58023F4B +P 12050 5300 +F 0 "#GND_0104" H 12050 5300 20 0000 C CNN +F 1 "+GND" H 12050 5230 30 0000 C CNN +F 2 "" H 12050 5300 70 0000 C CNN +F 3 "" H 12050 5300 70 0000 C CNN + 1 12050 5300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #GND_0105 +U 1 1 58023F4A +P 7050 8000 +F 0 "#GND_0105" H 7050 8000 20 0000 C CNN +F 1 "+GND" H 7050 7930 30 0000 C CNN +F 2 "" H 7050 8000 70 0000 C CNN +F 3 "" H 7050 8000 70 0000 C CNN + 1 7050 8000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #GND_0106 +U 1 1 58023F49 +P 6450 8000 +F 0 "#GND_0106" H 6450 8000 20 0000 C CNN +F 1 "+GND" H 6450 7930 30 0000 C CNN +F 2 "" H 6450 8000 70 0000 C CNN +F 3 "" H 6450 8000 70 0000 C CNN + 1 6450 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_027 +U 1 1 58023F48 +P 8750 3200 +F 0 "#VCCO_3V3_027" H 8750 3200 20 0000 C CNN +F 1 "+VCCO_3V3" H 8750 3130 30 0000 C CNN +F 2 "" H 8750 3200 70 0000 C CNN +F 3 "" H 8750 3200 70 0000 C CNN + 1 8750 3200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_028 +U 1 1 58023F47 +P 6450 6900 +F 0 "#VCCO_3V3_028" H 6450 6900 20 0000 C CNN +F 1 "+VCCO_3V3" H 6450 6830 30 0000 C CNN +F 2 "" H 6450 6900 70 0000 C CNN +F 3 "" H 6450 6900 70 0000 C CNN + 1 6450 6900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_029 +U 1 1 58023F46 +P 3710 2630 +F 0 "#VCCO_3V3_029" H 3710 2630 20 0000 C CNN +F 1 "+VCCO_3V3" H 3710 2560 30 0000 C CNN +F 2 "" H 3710 2630 70 0000 C CNN +F 3 "" H 3710 2630 70 0000 C CNN + 1 3710 2630 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #GND_0107 +U 1 1 58023F45 +P 3710 3630 +F 0 "#GND_0107" H 3710 3630 20 0000 C CNN +F 1 "+GND" H 3710 3560 30 0000 C CNN +F 2 "" H 3710 3630 70 0000 C CNN +F 3 "" H 3710 3630 70 0000 C CNN + 1 3710 3630 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_030 +U 1 1 58023F44 +P 5410 2300 +F 0 "#VCCO_3V3_030" H 5410 2300 20 0000 C CNN +F 1 "+VCCO_3V3" H 5410 2230 30 0000 C CNN +F 2 "" H 5410 2300 70 0000 C CNN +F 3 "" H 5410 2300 70 0000 C CNN + 1 5410 2300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #GND_0108 +U 1 1 58023F43 +P 5010 5930 +F 0 "#GND_0108" H 5010 5930 20 0000 C CNN +F 1 "+GND" H 5010 5860 30 0000 C CNN +F 2 "" H 5010 5930 70 0000 C CNN +F 3 "" H 5010 5930 70 0000 C CNN + 1 5010 5930 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9650 4600 9650 5300 +Wire Wire Line + 9750 4600 9650 4600 +Wire Wire Line + 8750 5100 8750 5300 +Wire Wire Line + 12050 5000 12050 5300 +Wire Wire Line + 7050 7700 7050 8000 +Wire Wire Line + 7150 7700 7050 7700 +Wire Wire Line + 6450 7800 6450 8000 +Wire Wire Line + 3710 3530 3710 3630 +Wire Wire Line + 3710 3430 3710 3530 +Wire Wire Line + 3310 3330 3310 3530 +Wire Wire Line + 3710 3530 3310 3530 +Wire Wire Line + 5010 5830 5010 5930 +Wire Wire Line + 9650 3500 9650 3700 +Wire Wire Line + 9650 3500 8750 3500 +Wire Wire Line + 8750 3200 8750 3500 +Wire Wire Line + 11450 4300 11200 4300 +Wire Wire Line + 11450 3500 11450 4300 +Wire Wire Line + 11450 3500 9650 3500 +Wire Wire Line + 11450 4400 11200 4400 +Wire Wire Line + 11450 4300 11450 4400 +Wire Wire Line + 12050 4400 12050 4700 +Wire Wire Line + 12050 4400 11450 4400 +Wire Wire Line + 6450 7300 6450 7500 +Wire Wire Line + 7050 7300 6450 7300 +Wire Wire Line + 7150 7300 7050 7300 +Wire Wire Line + 6450 6900 6450 7300 +Wire Wire Line + 7450 6900 7050 6900 +Wire Wire Line + 7050 6900 7050 7300 +Wire Wire Line + 3710 2730 3710 2830 +Wire Wire Line + 3710 2630 3710 2730 +Wire Wire Line + 3310 2730 3310 3030 +Wire Wire Line + 3710 2730 3310 2730 +Wire Wire Line + 5410 2420 5410 2500 +Wire Wire Line + 5410 2300 5410 2420 +Wire Wire Line + 11820 4500 11200 4500 +Text Label 11200 4500 0 48 ~ 0 +FPGA_PROM_SCLK +Wire Wire Line + 6910 3730 6710 3730 +Wire Wire Line + 6910 3730 6910 4830 +Wire Wire Line + 6910 4830 6710 4830 +Wire Wire Line + 7210 3730 6910 3730 +Text Label 7210 3730 0 48 ~ 0 +FPGA_PROM_SCLK +Wire Wire Line + 11820 4600 11200 4600 +Text Label 11200 4600 0 48 ~ 0 +FPGA_PROM_MOSI +Wire Wire Line + 7010 4930 6710 4930 +Wire Wire Line + 7010 3830 7010 4930 +Wire Wire Line + 7010 3830 6710 3830 +Wire Wire Line + 7210 3830 7010 3830 +Text Label 7210 3830 0 48 ~ 0 +FPGA_PROM_MOSI +Wire Wire Line + 9750 4300 9650 4300 +Wire Wire Line + 9650 4100 9650 4300 +Wire Wire Line + 9650 4300 8950 4300 +Text Label 8950 4300 0 48 ~ 0 +FPGA_PROM_CS_N +Wire Wire Line + 6810 4730 6710 4730 +Wire Wire Line + 6810 3630 6810 4730 +Wire Wire Line + 6810 3630 6710 3630 +Wire Wire Line + 7210 3630 6810 3630 +Text Label 7210 3630 0 48 ~ 0 +FPGA_PROM_CS_N +Wire Wire Line + 9750 4400 8950 4400 +Text Label 8950 4400 0 48 ~ 0 +FPGA_PROM_MISO +Wire Wire Line + 5710 3930 5610 3930 +Wire Wire Line + 5610 3930 5030 3930 +Wire Wire Line + 5710 5030 5610 5030 +Wire Wire Line + 5610 3930 5610 5030 +Text Label 5030 3930 0 48 ~ 0 +FPGA_PROM_MISO +Wire Wire Line + 9750 4500 8750 4500 +Wire Wire Line + 8750 4500 8750 4700 +Text Label 8950 4500 0 48 ~ 0 +FPGA_PROM_W_N +Wire Wire Line + 9050 7500 8750 7500 +Text GLabel 8750 7500 0 48 Input ~ 0 +FPGA_GCLK +Wire Wire Line + 8250 7300 8150 7300 +Wire Wire Line + 8250 6900 8250 7300 +Wire Wire Line + 8250 6900 7850 6900 +Wire Wire Line + 5710 4830 5140 4830 +Text GLabel 5140 4830 0 48 Input ~ 0 +FPGA_CFG_SCLK +Wire Wire Line + 5710 4930 5140 4930 +Text GLabel 5140 4930 0 48 Input ~ 0 +FPGA_CFG_MOSI +Wire Wire Line + 5710 4730 5140 4730 +Text GLabel 5140 4730 0 48 Input ~ 0 +FPGA_CFG_CS_N +Wire Wire Line + 7210 5030 6710 5030 +Text GLabel 7210 5030 2 48 Output ~ 0 +FPGA_CFG_MISO +Wire Wire Line + 5710 3630 5030 3630 +Text GLabel 5030 3630 0 48 Input ~ 0 +ARM_FPGA_CFG_CS_N +Wire Wire Line + 5710 3830 5030 3830 +Text GLabel 5030 3830 0 48 Input ~ 0 +ARM_FPGA_CFG_MOSI +Wire Wire Line + 7210 3930 6710 3930 +Text GLabel 7210 3930 2 48 Output ~ 0 +ARM_FPGA_CFG_MISO +Wire Wire Line + 5710 3730 5030 3730 +Text GLabel 5030 3730 0 48 Input ~ 0 +ARM_FPGA_CFG_SCLK +Text Label 5410 3510 1 48 ~ 0 +SPI_A_TRISTATE +Text Label 5110 5230 0 48 ~ 0 +SPI_B_TRISTATE +Text GLabel 2480 4430 0 48 Input ~ 0 +FPGA_CFG_CTRL_FPGA_DIS +Wire Wire Line + 8350 7500 8150 7500 +Text Notes 7370 7730 0 54 ~ 11 +GND +Text Notes 7370 7330 0 54 ~ 11 +VCC +Text Notes 7810 7660 0 54 ~ 11 +FO +Text Notes 7800 7300 0 54 ~ 11 +OE +Text Notes 3940 4120 0 60 ~ 12 +1 +Text Notes 4240 4120 0 60 ~ 12 +2 +Text Notes 3940 4220 0 60 ~ 12 +3 +Text Notes 4240 4220 0 60 ~ 12 +4 +Text Notes 3940 4320 0 60 ~ 12 +5 +Text Notes 4240 4320 0 60 ~ 12 +6 +Wire Wire Line + 5410 2900 5410 4130 +Wire Wire Line + 5010 5230 5010 5430 +Wire Wire Line + 5710 5230 5010 5230 +Wire Wire Line + 5010 4230 5010 5230 +Wire Wire Line + 4410 4230 5010 4230 +Wire Wire Line + 3610 4430 2480 4430 +Wire Wire Line + 3610 4230 3610 4430 +Wire Wire Line + 3810 4230 3610 4230 +Wire Wire Line + 3690 4830 2470 4830 +Wire Wire Line + 3690 4330 3690 4830 +Wire Wire Line + 3810 4330 3690 4330 +Wire Wire Line + 4760 4330 4410 4330 +Wire Wire Line + 4760 2420 4760 4330 +Wire Wire Line + 5410 2420 4760 2420 +Text Label 2470 4830 0 48 ~ 0 +FPGA_PROM_W_N +Wire Wire Line + 5410 4130 4410 4130 +Wire Wire Line + 5710 4130 5410 4130 +Wire Wire Line + 2480 4130 3810 4130 +Text GLabel 2480 4130 0 48 Input ~ 0 +FPGA_CFG_CTRL_ARM_ENA +Connection ~ 5410 2420 +$Comp +L Cryptech_Alpha:N25Q128A13ES IC3 +U 1 1 58023F42 +P 10450 4550 +F 0 "IC3" H 9940 4290 60 0000 L BNN +F 1 "N25Q128A13ESE*" H 10150 4920 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO08" H 10150 4920 60 0001 C CNN +F 3 "" H 10150 4920 60 0000 C CNN + 1 10450 4550 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R4 +U 1 1 58023F41 +P 8550 7500 +F 0 "R4" H 8660 7645 60 0000 R TNN +F 1 "0" H 8510 7660 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8510 7660 60 0001 C CNN +F 3 "" H 8510 7660 60 0000 C CNN + 1 8550 7500 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:74*244DW_NEW IC2 +U 1 1 58023F40 +P 6210 3830 +F 0 "IC2" H 5880 3300 60 0000 L BNN +F 1 "MC74AC244DW*" H 5900 3300 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 5900 3300 60 0001 C CNN +F 3 "" H 5900 3300 60 0000 C CNN + 1 6210 3830 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:74*244DW_NEW IC2 +U 2 1 58023F3F +P 6210 4930 +F 0 "IC2" H 5880 4400 60 0000 L BNN +F 1 "MC74AC244DW*" H 5910 4390 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 5910 4390 60 0001 C CNN +F 3 "" H 5910 4390 60 0000 C CNN + 2 6210 4930 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:74*244DW_NEW IC2 +U 3 1 58023F3E +P 3710 3130 +F 0 "IC2" H 3740 2980 60 0000 L BNN +F 1 "MC74AC244DW*" H 3910 3110 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 3910 3110 60 0001 C CNN +F 3 "" H 3910 3110 60 0000 C CNN + 3 3710 3130 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:ASF* Q5 +U 1 1 58023F3D +P 7650 7500 +F 0 "Q5" H 7320 7070 60 0000 L BNN +F 1 "ASFL1-50.000MHZ-EK-T" H 7130 7830 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:ASF" H 7130 7830 60 0001 C CNN +F 3 "" H 7130 7830 60 0000 C CNN + 1 7650 7500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:M03X2NO_SILK JP7 +U 1 1 58023F3C +P 4110 4230 +F 0 "JP7" H 3900 3920 60 0000 L BNN +F 1 "~" H 4110 4230 50 0001 C CNN +F 2 "Cryptech_Alpha_Footprints:PLD-6" H 3900 3920 60 0001 C CNN +F 3 "" H 4110 4230 50 0001 C CNN + 1 4110 4230 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R51 +U 1 1 58023F3B +P 9650 3900 +F 0 "R51" V 9560 3855 60 0000 R TNN +F 1 "4.7k" V 9560 3810 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 9560 3810 60 0001 C CNN +F 3 "" H 9560 3810 60 0000 C CNN + 1 9650 3900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R50 +U 1 1 58023F3A +P 8750 4900 +F 0 "R50" V 8660 4855 60 0000 R TNN +F 1 "4.7k" V 8670 4800 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8670 4800 60 0001 C CNN +F 3 "" H 8670 4800 60 0000 C CNN + 1 8750 4900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C111 +U 1 1 58023F39 +P 6450 7600 +F 0 "C111" H 6530 7410 60 0000 L BNN +F 1 "~" H 6450 7600 50 0001 C CNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6530 7410 60 0001 C CNN +F 3 "" H 6450 7600 50 0001 C CNN + 1 6450 7600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R49 +U 1 1 58023F38 +P 7650 6900 +F 0 "R49" H 7760 7045 60 0000 R TNN +F 1 "0" H 7760 7060 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 7760 7060 60 0001 C CNN +F 3 "" H 7760 7060 60 0000 C CNN + 1 7650 6900 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C112 +U 1 1 58023F37 +P 12050 4800 +F 0 "C112" H 11710 4615 60 0000 L BNN +F 1 "0.1uF" H 11710 4530 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11710 4530 60 0001 C CNN +F 3 "" H 11710 4530 60 0000 C CNN + 1 12050 4800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C110 +U 1 1 58023F36 +P 3310 3130 +F 0 "C110" H 3370 3145 60 0000 L BNN +F 1 "0.1uF" H 3370 2920 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3370 2920 60 0001 C CNN +F 3 "" H 3370 2920 60 0000 C CNN + 1 3310 3130 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R46 +U 1 1 58023F35 +P 5410 2700 +F 0 "R46" V 5320 2655 60 0000 R TNN +F 1 "4.7k" V 5390 2590 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5390 2590 60 0001 C CNN +F 3 "" H 5390 2590 60 0000 C CNN + 1 5410 2700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R47 +U 1 1 58023F34 +P 5010 5630 +F 0 "R47" V 5100 5675 60 0000 L BNN +F 1 "4.7k" V 5090 5710 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5090 5710 60 0001 C CNN +F 3 "" H 5090 5710 60 0000 C CNN + 1 5010 5630 + 0 1 1 0 +$EndComp +Connection ~ 3710 2730 +Connection ~ 3710 3530 +Connection ~ 5010 5230 +Connection ~ 5410 4130 +Connection ~ 5610 3930 +Connection ~ 6450 7300 +Connection ~ 6810 3630 +Connection ~ 6910 3730 +Connection ~ 7010 3830 +Connection ~ 7050 7300 +Connection ~ 9650 3500 +Connection ~ 9650 4300 +Connection ~ 11450 4300 +Connection ~ 11450 4400 +$EndSCHEMATC |