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-EESchema Schematic File Version 4
-EELAYER 30 0
-EELAYER END
-$Descr B 17000 11000
-encoding utf-8
-Sheet 22 27
-Title "rev04_20"
-Date "15 10 2016"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Text Notes 2600 2900 0 60 ~ 12
-*) Lower Right Bank
-Text Notes 4820 6210 0 60 ~ 12
-DIGITIZED_NOISE signal should go into\neither W19 or Y18 (i.e. into one of the two\npositive (master) sides of the two available\nMRCC differential pairs)
-Text Notes 7500 2900 0 60 ~ 12
-*) Signals, that are allowed to be swapped, can be be swapped\nwith each other and/or moved to different pins within their bank.
-Text Notes 5800 5300 0 60 ~ 12
-<-- FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped
-Text Notes 5980 3610 0 60 ~ 12
-<-- Disable pull-ups on all pins during configuration
-Text Notes 6900 1420 0 84 ~ 17
-FPGA MKM interface
-Text Notes 5280 3690 0 60 ~ 12
-R65
-$Comp
-L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_038
-U 1 1 58023EEC
-P 5200 3100
-F 0 "#VCCO_3V3_038" H 5200 3100 20 0000 C CNN
-F 1 "+VCCO_3V3" H 5200 3030 30 0000 C CNN
-F 2 "" H 5200 3100 70 0000 C CNN
-F 3 "" H 5200 3100 70 0000 C CNN
- 1 5200 3100
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4600 6200 3400 6200
-Text GLabel 4600 6200 2 48 Input ~ 0
-DIGITIZED_NOISE
-Wire Wire Line
- 4600 5300 3400 5300
-Text GLabel 4600 5300 2 48 Output ~ 0
-FPGA_GPIO_LED_2
-Wire Wire Line
- 4600 5400 3400 5400
-Text GLabel 4600 5400 2 48 Output ~ 0
-FPGA_GPIO_LED_3
-Wire Wire Line
- 4600 5200 3400 5200
-Wire Wire Line
- 3600 3300 3400 3300
-Wire Wire Line
- 3600 3300 3600 3400
-Wire Wire Line
- 3600 3400 3600 3500
-Wire Wire Line
- 3600 3500 3600 3600
-Wire Wire Line
- 3600 3600 3600 3700
-Wire Wire Line
- 3600 3700 3400 3700
-Wire Wire Line
- 3600 3600 3400 3600
-Wire Wire Line
- 3600 3500 3400 3500
-Wire Wire Line
- 3600 3400 3400 3400
-Wire Wire Line
- 5200 3100 5200 3300
-Wire Wire Line
- 3600 3700 3600 3800
-Wire Wire Line
- 3600 3800 3400 3800
-Wire Wire Line
- 4600 4000 4500 4000
-Text GLabel 4600 4000 2 48 UnSpc ~ 0
-FPGA_CFG_MOSI
-Wire Wire Line
- 4600 4100 4500 4100
-Text GLabel 4600 4100 2 48 Input ~ 0
-FPGA_CFG_MISO
-Wire Wire Line
- 4600 5000 4500 5000
-Text GLabel 4600 5000 2 48 Output ~ 0
-FPGA_CFG_CS_N
-Wire Wire Line
- 4100 4100 3400 4100
-Text Label 3460 4100 2 48 ~ 0
-FPGA_CFG_MISO1
-Wire Wire Line
- 4100 4000 3400 4000
-Text Label 3460 4000 2 48 ~ 0
-FPGA_CFG_MOSI1
-Wire Wire Line
- 4100 5000 3400 5000
-Text Label 3460 5000 2 48 ~ 0
-FPGA_CFG_CS_N1
-Text GLabel 4600 5800 2 48 Input ~ 0
-FMC_A19
-Text GLabel 4600 5900 2 48 Input ~ 0
-FMC_A20
-Wire Wire Line
- 4600 5800 3400 5800
-Wire Wire Line
- 4600 5900 3400 5900
-Text GLabel 4610 6900 2 48 Input ~ 0
-FMC_A21
-Wire Wire Line
- 4610 6900 3400 6900
-Text GLabel 4600 5600 2 48 Input ~ 0
-FMC_A22
-Text GLabel 4600 5700 2 48 Input ~ 0
-FMC_A23
-Wire Wire Line
- 4600 5700 3400 5700
-Wire Wire Line
- 4600 5600 3400 5600
-Text GLabel 4600 7300 2 48 Input ~ 0
-FMC_A24
-Wire Wire Line
- 4600 7300 3400 7300
-Text GLabel 4600 6800 2 48 Input ~ 0
-FMC_A25
-Wire Wire Line
- 4600 6800 3400 6800
-Text GLabel 4600 6400 2 48 BiDi ~ 0
-FMC_D8
-Wire Wire Line
- 4600 6400 3400 6400
-Text GLabel 4600 5500 2 48 BiDi ~ 0
-FMC_D9
-Wire Wire Line
- 4600 5500 3400 5500
-Text GLabel 4600 6300 2 48 BiDi ~ 0
-FMC_D10
-Wire Wire Line
- 4600 6300 3400 6300
-Text GLabel 4600 6000 2 48 BiDi ~ 0
-FMC_D12
-Wire Wire Line
- 4600 6000 3400 6000
-Text GLabel 4600 6100 2 48 BiDi ~ 0
-FMC_D28
-Wire Wire Line
- 4600 6100 3400 6100
-Text GLabel 4600 6600 2 48 BiDi ~ 0
-FMC_D29
-Wire Wire Line
- 4600 6600 3400 6600
-Text GLabel 4100 4300 2 48 BiDi ~ 0
-FMC_D30
-Wire Wire Line
- 4100 4300 3400 4300
-Text GLabel 4100 4200 2 48 BiDi ~ 0
-FMC_D31
-Wire Wire Line
- 4100 4200 3400 4200
-Text GLabel 4600 7100 2 48 UnSpc ~ 0
-FMC_NL
-Wire Wire Line
- 4600 7100 3400 7100
-Text GLabel 4600 8800 2 48 BiDi ~ 0
-FMC_D11
-Wire Wire Line
- 4600 8800 3400 8800
-Wire Wire Line
- 5200 3800 5200 4400
-Wire Wire Line
- 5200 3400 5200 3300
-$Comp
-L Cryptech_Alpha:R-EU_R0402 R65
-U 1 1 58023EEB
-P 5200 3600
-F 0 "R65" V 5110 3555 60 0000 R TNN
-F 1 "1k" V 5030 3530 60 0000 R TNN
-F 2 "Cryptech_Alpha_Footprints:R_0402" H 5030 3530 60 0001 C CNN
-F 3 "" H 5030 3530 60 0000 C CNN
- 1 5200 3600
- 0 -1 -1 0
-$EndComp
-$Comp
-L Cryptech_Alpha:R-EU_R0603 R83
-U 1 1 58023EEA
-P 4300 4000
-F 0 "R83" H 4410 3920 60 0000 R TNN
-F 1 "0" H 4220 3920 60 0000 R TNN
-F 2 "Cryptech_Alpha_Footprints:R_0402" H 4220 3920 60 0001 C CNN
-F 3 "" H 4220 3920 60 0000 C CNN
- 1 4300 4000
- -1 0 0 1
-$EndComp
-$Comp
-L Cryptech_Alpha:R-EU_R0603 R84
-U 1 1 58023EE9
-P 4300 4100
-F 0 "R84" H 4400 4280 60 0000 R TNN
-F 1 "0" H 4210 4270 60 0000 R TNN
-F 2 "Cryptech_Alpha_Footprints:R_0402" H 4210 4270 60 0001 C CNN
-F 3 "" H 4210 4270 60 0000 C CNN
- 1 4300 4100
- -1 0 0 1
-$EndComp
-$Comp
-L Cryptech_Alpha:R-EU_R0603 R85
-U 1 1 58023EE8
-P 4300 5000
-F 0 "R85" H 4180 5000 60 0000 R TNN
-F 1 "0" H 4170 5100 60 0000 R TNN
-F 2 "Cryptech_Alpha_Footprints:R_0402" H 4170 5100 60 0001 C CNN
-F 3 "" H 4170 5100 60 0000 C CNN
- 1 4300 5000
- -1 0 0 1
-$EndComp
-$Comp
-L Cryptech_Alpha:XC7A200TFBG484_NEW U13
-U 3 1 58023EE7
-P 3200 6000
-F 0 "U13" H 2790 2990 60 0000 L BNN
-F 1 "~" H 3200 6000 50 0001 C CNN
-F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 2790 2990 60 0001 C CNN
-F 3 "" H 3200 6000 50 0001 C CNN
- 3 3200 6000
- 1 0 0 -1
-$EndComp
-NoConn ~ 3400 4500
-NoConn ~ 3400 4700
-NoConn ~ 3400 4600
-NoConn ~ 3400 4800
-NoConn ~ 3400 4900
-NoConn ~ 3400 5100
-NoConn ~ 3400 6500
-NoConn ~ 3400 6700
-NoConn ~ 3400 7000
-NoConn ~ 3400 7200
-NoConn ~ 3400 7400
-NoConn ~ 3400 7500
-NoConn ~ 3400 7600
-NoConn ~ 3400 7700
-NoConn ~ 3400 7800
-NoConn ~ 3400 7900
-NoConn ~ 3400 8000
-NoConn ~ 3400 8100
-NoConn ~ 3400 8200
-NoConn ~ 3400 8300
-NoConn ~ 3400 8400
-NoConn ~ 3400 8500
-NoConn ~ 3400 8600
-NoConn ~ 3400 8700
-NoConn ~ 3400 3900
-NoConn ~ 4600 5200
-Wire Wire Line
- 3400 4400 5200 4400
-Wire Wire Line
- 3600 3300 5200 3300
-Connection ~ 3600 3300
-Connection ~ 3600 3400
-Connection ~ 3600 3500
-Connection ~ 3600 3600
-Connection ~ 3600 3700
-Connection ~ 5200 3300
-$EndSCHEMATC