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-rw-r--r--KiCAD/rev02_19.sch-bak14
1 files changed, 7 insertions, 7 deletions
diff --git a/KiCAD/rev02_19.sch-bak b/KiCAD/rev02_19.sch-bak
index ed11dfd..d1feb42 100644
--- a/KiCAD/rev02_19.sch-bak
+++ b/KiCAD/rev02_19.sch-bak
@@ -15,13 +15,13 @@ Comment4 ""
$EndDescr
Text Notes 1000 4000 0 60 ~ 12
*) Upper Right Bank
-Text Notes 3290 7510 0 60 ~ 12
+Text Notes 4000 6350 0 60 ~ 12
*) FPGA_GCLK signal _MUST_ go into either D17 or C18\n(i.e. into one of the two positive (master) sides\nof the two available MRCC differential pairs)
-Text Notes 3260 7850 0 60 ~ 12
+Text Notes 4000 6650 0 60 ~ 12
*) FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped
Text Notes 6930 3910 0 60 ~ 12
*) Signals, that are allowed to be swapped, can be be swapped\nwith each other and/or moved to different pins within their bank.
-Text Notes 3300 6500 0 60 ~ 12
+Text Notes 4000 5750 0 60 ~ 12
NOTE: One of the FPGA_GPIO_* pins\nshould be connected to one of the\nMRCC pins.\nThe non-MRCC GPIO signals should be\nlength matched to within 500 ps of\nthe MRCC signal.
Text Notes 8840 10230 0 84 ~ 17
FPGA GPIO
@@ -278,11 +278,11 @@ Wire Wire Line
Wire Wire Line
3100 8100 1900 8100
Text GLabel 3100 8100 2 48 UnSpc ~ 0
-AVR_GPIO_FPGA_0
+ICE40_GPIO_FPGA_0
Wire Wire Line
3100 8200 1900 8200
Text GLabel 3100 8200 2 48 UnSpc ~ 0
-AVR_GPIO_FPGA_1
+ICE40_GPIO_FPGA_1
Wire Wire Line
3100 5200 1900 5200
Text GLabel 3100 5200 2 48 UnSpc ~ 0
@@ -454,11 +454,11 @@ FPGA_ENTROPY_DISABLE
Wire Wire Line
3100 8300 1900 8300
Text GLabel 3100 8300 2 48 UnSpc ~ 0
-AVR_GPIO_FPGA_2
+ICE40_GPIO_FPGA_2
Wire Wire Line
3100 8400 1900 8400
Text GLabel 3100 8400 2 48 UnSpc ~ 0
-AVR_GPIO_FPGA_3
+ICE40_GPIO_FPGA_3
Wire Wire Line
3100 7500 1900 7500
Wire Wire Line