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-rw-r--r--KiCAD/rev02_06.sch22
1 files changed, 10 insertions, 12 deletions
diff --git a/KiCAD/rev02_06.sch b/KiCAD/rev02_06.sch
index a972e71..f3a4216 100644
--- a/KiCAD/rev02_06.sch
+++ b/KiCAD/rev02_06.sch
@@ -3,8 +3,8 @@ EELAYER 30 0
EELAYER END
$Descr B 17000 11000
encoding utf-8
-Sheet 8 27
-Title "rev02_06"
+Sheet 7 27
+Title "rev04_06"
Date "15 10 2016"
Rev ""
Comp ""
@@ -15,8 +15,6 @@ Comment4 ""
$EndDescr
Text Notes 5500 1300 0 126 ~ 25
2x512 Mbit SDRAM memory for the ARM
-Text Notes 13910 10230 0 84 ~ 17
-SDRAM
Text Notes 6000 1700 0 60 ~ 12
These packages are TSSOP, but if new packages are to be created\nfor layout, BGA package is preferred.
Text Notes 3180 2240 0 60 ~ 12
@@ -1145,25 +1143,17 @@ Text GLabel 9700 6100 0 48 Input ~ 0
FMC_SDNE1
Wire Bus Line
2700 2400 2150 2400
-Wire Bus Line
- 2700 2400 2700 4200
Text Label 2150 2400 0 60 ~ 0
FMC_A[0..25]
Wire Bus Line
9700 2500 9150 2500
-Wire Bus Line
- 9700 2500 9700 4300
Text Label 9150 2500 0 60 ~ 0
FMC_A[0..25]
Wire Bus Line
- 6300 2400 6300 5700
-Wire Bus Line
6900 2400 6300 2400
Text Label 6300 2400 0 60 ~ 0
FMC_D[0..31]
Wire Bus Line
- 13300 2500 13300 5800
-Wire Bus Line
13900 2500 13300 2500
Text Label 13300 2500 0 60 ~ 0
FMC_D[0..31]
@@ -1431,4 +1421,12 @@ F 3 "" H 3120 7920 60 0000 C CNN
1 3500 8000
1 0 0 -1
$EndComp
+Wire Bus Line
+ 2700 2400 2700 4200
+Wire Bus Line
+ 9700 2500 9700 4300
+Wire Bus Line
+ 6300 2400 6300 5700
+Wire Bus Line
+ 13300 2500 13300 5800
$EndSCHEMATC