diff options
Diffstat (limited to 'KiCAD/Cryptech Alpha.pro')
| -rw-r--r-- | KiCAD/Cryptech Alpha.pro | 288 |
1 files changed, 268 insertions, 20 deletions
diff --git a/KiCAD/Cryptech Alpha.pro b/KiCAD/Cryptech Alpha.pro index 3c93a1f..0068a54 100644 --- a/KiCAD/Cryptech Alpha.pro +++ b/KiCAD/Cryptech Alpha.pro @@ -1,25 +1,6 @@ -update=ons 9 maj 2018 10:36:52 +update=21.06.2020 23:43:45 version=1 last_client=kicad -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 [cvpcb] version=1 NetIExt=net @@ -28,3 +9,270 @@ version=1 [eeschema] version=1 LibDir= +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Pcbnew +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead=Cryptech Alpha.net +CopperLayerCount=8 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.15 +MinViaDiameter=0.5 +MinViaDrill=0.25 +MinMicroViaDiameter=0.508 +MinMicroViaDrill=0.127 +MinHoleToHole=0.25 +TrackWidth1=0.254 +ViaDiameter1=0.889 +ViaDrill1=0.25 +dPairWidth1=0.2 +dPairGap1=0.25 +dPairViaGap1=0.25 +SilkLineWidth=0.15 +SilkTextSizeV=1 +SilkTextSizeH=1 +SilkTextSizeThickness=0.15 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.2 +CopperTextSizeV=1.5 +CopperTextSizeH=1.5 +CopperTextThickness=0.3 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.09999999999999999 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0 +SolderMaskMinWidth=0 +SolderPasteClearance=0 +SolderPasteRatio=0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=1 +Enabled=1 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=2 +Enabled=1 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=1 +Enabled=1 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=1 +Enabled=1 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=2 +Enabled=1 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=1 +Enabled=1 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=1 +[pcbnew/Layer.F.Fab] +Enabled=1 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.125 +TrackWidth=0.254 +ViaDiameter=0.889 +ViaDrill=0.25 +uViaDiameter=0.508 +uViaDrill=0.127 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 +[pcbnew/Netclasses/1] +Name=FMC +Clearance=0.125 +TrackWidth=0.254 +ViaDiameter=0.889 +ViaDrill=0.25 +uViaDiameter=0.508 +uViaDrill=0.127 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 +[pcbnew/Netclasses/2] +Name=FPGA_GPIO +Clearance=0.125 +TrackWidth=0.254 +ViaDiameter=0.889 +ViaDrill=0.25 +uViaDiameter=0.508 +uViaDrill=0.127 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 +[pcbnew/Netclasses/3] +Name=USB +Clearance=0.125 +TrackWidth=0.254 +ViaDiameter=0.889 +ViaDrill=0.25 +uViaDiameter=0.508 +uViaDrill=0.127 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 |