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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:11:11 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:11:11 +0300 |
| commit | 1dee9e20eccc1cf3a6396d88c765b44faebacdd2 (patch) | |
| tree | 1189394c7bbb3bfd232397208b7c8bf5ac8bf108 /KiCAD/wrlshp/537E0B02-A9B3.wrl | |
| parent | a70ee229e036c7ae9ef61af5a73cc32ea6b773ca (diff) | |
Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGA
along with it's power subsystem and programming circuitry.
Diffstat (limited to 'KiCAD/wrlshp/537E0B02-A9B3.wrl')
0 files changed, 0 insertions, 0 deletions