diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 16:00:05 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 16:00:05 +0300 |
| commit | 4d9304dbd2f49e99e900039caeab133687c6e5cb (patch) | |
| tree | 15c240a2b952eb05a970c48fb966348bcfa313b6 /KiCAD/rev04_12.sch | |
| parent | f66f8e0815ed28ab80065a381fcecb27bc4f8c66 (diff) | |
Finished BOM overhaul. All the discrete components should have proper tolerance
and other parameters. All the other components should have partnumbers and
manufacturers associated.
Did some polishing to the PCB after feedback from the assembly house. KiCAD was
for some reason breaking the "neck" between two copper islands in a couple of
places. This was happening in two places on Layer 3 and three places on Layer
6, easily fixed by hand.
Diffstat (limited to 'KiCAD/rev04_12.sch')
| -rw-r--r-- | KiCAD/rev04_12.sch | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/KiCAD/rev04_12.sch b/KiCAD/rev04_12.sch index ecfab81..116acc1 100644 --- a/KiCAD/rev04_12.sch +++ b/KiCAD/rev04_12.sch @@ -55,9 +55,10 @@ L FPGA_Lattice:ICE40UP5K-SG48ITR U11 U 2 1 5EF0D127 P 4700 2550 F 0 "U11" H 4700 1475 50 0000 C CNN -F 1 "ICE40UP5K-SG48ITR" H 4700 1384 50 0000 C CNN +F 1 "ICE40UP5K-SG48I" H 4700 1384 50 0000 C CNN F 2 "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm" H 4700 1200 50 0001 C CNN F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra" H 4300 3550 50 0001 C CNN +F 4 "Lattice" H 4700 2550 50 0001 C CNN "Manufacturer" 2 4700 2550 1 0 0 -1 $EndComp @@ -66,9 +67,10 @@ L FPGA_Lattice:ICE40UP5K-SG48ITR U11 U 3 1 5F21B0EE P 9400 8900 F 0 "U11" H 9750 8800 50 0000 L CNN -F 1 "ICE40UP5K-SG48ITR" H 9750 8700 50 0000 L CNN +F 1 "ICE40UP5K-SG48I" H 9750 8700 50 0000 L CNN F 2 "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm" H 9400 7550 50 0001 C CNN F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra" H 9000 9900 50 0001 C CNN +F 4 "Lattice" H 9400 8900 50 0001 C CNN "Manufacturer" 3 9400 8900 1 0 0 -1 $EndComp @@ -77,9 +79,10 @@ L FPGA_Lattice:ICE40UP5K-SG48ITR U11 U 4 1 5F21BC58 P 15500 1600 F 0 "U11" H 15730 1646 50 0000 L CNN -F 1 "ICE40UP5K-SG48ITR" H 15730 1555 50 0000 L CNN +F 1 "ICE40UP5K-SG48I" H 15730 1555 50 0000 L CNN F 2 "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm" H 15500 250 50 0001 C CNN F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra" H 15100 2600 50 0001 C CNN +F 4 "Lattice" H 15500 1600 50 0001 C CNN "Manufacturer" 4 15500 1600 0 -1 -1 0 $EndComp @@ -88,9 +91,10 @@ L FPGA_Lattice:ICE40UP5K-SG48ITR U11 U 1 1 5EEFEF07 P 4600 8300 F 0 "U11" H 4930 8353 50 0000 L CNN -F 1 "ICE40UP5K-SG48ITR" H 4930 8262 50 0000 L CNN +F 1 "ICE40UP5K-SG48I" H 4930 8262 50 0000 L CNN F 2 "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm" H 4600 6950 50 0001 C CNN F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra" H 4200 9300 50 0001 C CNN +F 4 "Lattice" H 4600 8300 50 0001 C CNN "Manufacturer" 1 4600 8300 1 0 0 -1 $EndComp @@ -119,6 +123,7 @@ F 4 "Analog Devices" H 10500 1650 50 0001 L BNN "Field4" F 5 "TSOT-5" H 10500 1650 50 0001 L BNN "Field5" F 6 "10R7024" H 10500 1650 50 0001 L BNN "Field6" F 7 "ADP121-AUJZ12R7" H 10500 1650 50 0001 L BNN "Field7" +F 8 "AD" H 10500 1650 50 0001 C CNN "Manufacturer" 1 10500 1650 1 0 0 -1 $EndComp @@ -445,6 +450,7 @@ F 4 "Analog Devices" H 10500 3400 50 0001 L BNN "Field4" F 5 "TSOT-5" H 10500 3400 50 0001 L BNN "Field5" F 6 "10R7024" H 10500 3400 50 0001 L BNN "Field6" F 7 "ADP121-AUJZ25R7" H 10500 3400 50 0001 L BNN "Field7" +F 8 "AD" H 10500 3400 50 0001 C CNN "Manufacturer" 1 10500 3400 1 0 0 -1 $EndComp @@ -713,9 +719,11 @@ L Connector_Generic:Conn_01x08 J5 U 1 1 5F109687 P 14200 5050 F 0 "J5" H 14280 5042 50 0000 L CNN -F 1 "Conn_01x08" H 14280 4951 50 0000 L CNN +F 1 "PLS-8" H 14280 4951 50 0000 L CNN F 2 "Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical" H 14200 5050 50 0001 C CNN -F 3 "~" H 14200 5050 50 0001 C CNN +F 3 "" H 14200 5050 50 0001 C CNN +F 4 "-" H 14200 5050 50 0001 C CNN "Manufacturer" +F 5 "0.1\" (2.54mm) 1x8 Pin Header" H 14200 5050 50 0001 C CNN "Comment" 1 14200 5050 1 0 0 -1 $EndComp @@ -969,6 +977,8 @@ F 0 "LED5" H 15155 7860 60 0000 R BNN F 1 "LTST-C191KGKT" H 15155 7760 60 0000 R BNN F 2 "Cryptech_Alpha_Footprints:VD_0603" H 15155 7760 60 0001 C CNN F 3 "" H 15155 7760 60 0000 C CNN +F 4 "Lite-On" H 15300 7950 50 0001 C CNN "Manufacturer" +F 5 "Green" H 15300 7950 50 0001 C CNN "Comment" 1 15300 7950 -1 0 0 -1 $EndComp @@ -1266,7 +1276,7 @@ Wire Wire Line 9000 9400 8300 9400 NoConn ~ 4200 2750 NoConn ~ 4200 2150 -NoConn ~ 4200 8100 NoConn ~ 9000 9200 NoConn ~ 9000 9300 +NoConn ~ 4200 8100 $EndSCHEMATC |