diff options
author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 14:53:52 +0300 |
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committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 14:53:52 +0300 |
commit | 9686a399784d63654bc32d4c04d678e181cece97 (patch) | |
tree | ed72db1d2b9219f1bb44a9086f5fd97fa2c3ba77 /KiCAD/rev02_21.sch-bak | |
parent | 90e0724d8e70b64612d23751e81dd207907aa0db (diff) |
Initial project cleanup
Diffstat (limited to 'KiCAD/rev02_21.sch-bak')
-rw-r--r-- | KiCAD/rev02_21.sch-bak | 549 |
1 files changed, 549 insertions, 0 deletions
diff --git a/KiCAD/rev02_21.sch-bak b/KiCAD/rev02_21.sch-bak new file mode 100644 index 0000000..8bb433b --- /dev/null +++ b/KiCAD/rev02_21.sch-bak @@ -0,0 +1,549 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 23 27 +Title "rev02_21" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 8100 4600 0 60 ~ 12 +*) Power - AUX +Text Notes 5000 4600 0 60 ~ 12 +*) Power - CORE & BRAM +Text Notes 2000 4500 0 60 ~ 12 +*) Ground Pins +Text Notes 8460 10210 0 66 ~ 12 +FPGA power and ground +$Comp +L power:GND GND_132 +U 1 1 58023EE6 +P 2000 9700 +F 0 "GND_132" H 2000 9700 20 0000 C CNN +F 1 "+GND" H 2000 9630 30 0000 C CNN +F 2 "" H 2000 9700 70 0000 C CNN +F 3 "" H 2000 9700 70 0000 C CNN + 1 2000 9700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_133 +U 1 1 58023EE5 +P 3800 9600 +F 0 "GND_133" H 3800 9600 20 0000 C CNN +F 1 "+GND" H 3800 9530 30 0000 C CNN +F 2 "" H 3800 9600 70 0000 C CNN +F 3 "" H 3800 9600 70 0000 C CNN + 1 3800 9600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FPGA_VCCINT_1V0 FPGA_VCCINT_1V0 +U 1 1 58023EE4 +P 6000 4900 +F 0 "FPGA_VCCINT_1V0" H 6000 4900 20 0000 C CNN +F 1 "+FPGA_VCCINT_1V0" H 6000 4830 30 0000 C CNN +F 2 "" H 6000 4900 70 0000 C CNN +F 3 "" H 6000 4900 70 0000 C CNN + 1 6000 4900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FPGA_VCCAUX_1V8 FPGA_VCCAUX_1V8_2 +U 1 1 58023EE3 +P 9000 4900 +F 0 "FPGA_VCCAUX_1V8_2" H 9000 4900 20 0000 C CNN +F 1 "+FPGA_VCCAUX_1V8" H 9000 4830 30 0000 C CNN +F 2 "" H 9000 4900 70 0000 C CNN +F 3 "" H 9000 4900 70 0000 C CNN + 1 9000 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2000 9500 1800 9500 +Wire Wire Line + 2000 9500 2000 9700 +Wire Wire Line + 2000 9400 1800 9400 +Wire Wire Line + 2000 9400 2000 9500 +Wire Wire Line + 2000 9000 1800 9000 +Wire Wire Line + 2000 9000 2000 9100 +Wire Wire Line + 2000 9100 2000 9200 +Wire Wire Line + 2000 9200 2000 9300 +Wire Wire Line + 2000 9300 2000 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U13_13 +U 1 1 58023EE2 +P 1600 7300 +F 0 "U13_13" H 1190 4890 60 0000 L BNN + 1 1600 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1190 4890 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_10 U13_14 +U 1 1 58023EE1 +P 3400 7300 +F 0 "U13_14" H 2990 4990 60 0000 L BNN + 1 3400 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 2990 4990 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_14 U13_15 +U 1 1 58023EE0 +P 8600 5300 +F 0 "U13_15" H 8190 4890 60 0000 L BNN + 1 8600 5300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 8190 4890 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_15 U13_16 +U 1 1 58023EDF +P 5600 5200 +F 0 "U13_16" H 5190 4890 60 0000 L BNN + 1 5600 5200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 5190 4890 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_16 U13_17 +U 1 1 58023EDE +P 5600 6600 +F 0 "U13_17" H 5190 7410 60 0000 L TNN + 1 5600 6600 + 1 0 0 1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 5190 7410 60 0001 C CNN +$EndComp +$EndSCHEMATC
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