Initial project cleanup

1 files changed, 583 insertions, 0 deletions

diff --git a/KiCAD/rev02_15.sch-bak b/KiCAD/rev02_15.sch-bak
new file mode 100644
index 0000000..15ab3eb
--- /dev/null
+++ b/KiCAD/rev02_15.sch-bak
@@ -0,0 +1,583 @@
+EESchema Schematic File Version 4
+EELAYER 26 0
+EELAYER END
+$Descr B 17000 11000
+encoding utf-8
+Sheet 17 27
+Title "rev02_15"
+Date "15 10 2016"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Text Notes 7100 4900 0    60   ~ 12
+*) HOLD feature not used\n*) PROM is write-protected by default, to disable\nwrite protection (such as during firmware update),\njumper must be inserted
+Text Notes 4800 8600 0    84   ~ 12
+FPGA clock
+Text Notes 7100 4200 0    84   ~ 12
+FPGA config memory, 128 Mbit
+Text Notes 1260 3930 0    84   ~ 12
+SPI mux to let ARM override access to\nFPGA config memory (to reprogram FPGA)
+Text Notes 420 6220 0    42   ~ 12
+Install this jumper to allow\nARM to configure the FPGA
+Text Notes 3490 4850 0    42   ~ 12
+ARM access default\ndisabled through pull-up
+Text Notes 3190 7830 0    42   ~ 12
+FPGA access default\nenabled through pull-down
+Text Notes 430 6540 0    42   ~ 12
+Install this jumper to allow\nARM to configure the FPGA
+Text Notes 8520 10210 0    60   ~ 12
+FPGA supporting components
+Text Notes 7900 6180 0    60   ~ 12
+IC3
+Text Notes 8460 6180 0    60   ~ 12
+N25Q128A13ES
+Text Notes 7700 5900 0    60   ~ 12
+R51
+Text Notes 6800 6900 0    60   ~ 12
+R50
+Text Notes 4460 9590 0    60   ~ 12
+C111
+Text Notes 4460 9790 0    60   ~ 12
+0.01uF
+Text Notes 5650 8770 2    60   ~ 12
+R49
+Text Notes 3470 4640 0    60   ~ 12
+R46
+Text Notes 3210 7520 2    60   ~ 12
+R47
+Text Notes 6450 9560 2    60   ~ 12
+R4
+Text Notes 3860 5510 0    60   ~ 12
+IC2
+Text Notes 3860 6330 0    60   ~ 12
+74*244DW
+$Comp
+L power:GND GND_102
+U 1 1 58023F4D
+P 7600 7300
+F 0 "GND_102" H 7600 7300 20  0000 C CNN
+F 1 "+GND" H 7600 7230 30  0000 C CNN
+F 2 "" H 7600 7300 70  0000 C CNN
+F 3 "" H 7600 7300 70  0000 C CNN
+	1    7600 7300
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND GND_103
+U 1 1 58023F4C
+P 6700 7300
+F 0 "GND_103" H 6700 7300 20  0000 C CNN
+F 1 "+GND" H 6700 7230 30  0000 C CNN
+F 2 "" H 6700 7300 70  0000 C CNN
+F 3 "" H 6700 7300 70  0000 C CNN
+	1    6700 7300
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND GND_104
+U 1 1 58023F4B
+P 10000 7300
+F 0 "GND_104" H 10000 7300 20  0000 C CNN
+F 1 "+GND" H 10000 7230 30  0000 C CNN
+F 2 "" H 10000 7300 70  0000 C CNN
+F 3 "" H 10000 7300 70  0000 C CNN
+	1    10000 7300
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND GND_105
+U 1 1 58023F4A
+P 5000 10000
+F 0 "GND_105" H 5000 10000 20  0000 C CNN
+F 1 "+GND" H 5000 9930 30  0000 C CNN
+F 2 "" H 5000 10000 70  0000 C CNN
+F 3 "" H 5000 10000 70  0000 C CNN
+	1    5000 10000
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND GND_106
+U 1 1 58023F49
+P 4400 10000
+F 0 "GND_106" H 4400 10000 20  0000 C CNN
+F 1 "+GND" H 4400 9930 30  0000 C CNN
+F 2 "" H 4400 10000 70  0000 C CNN
+F 3 "" H 4400 10000 70  0000 C CNN
+	1    4400 10000
+	1    0    0    -1  
+$EndComp
+$Comp
+L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_27
+U 1 1 58023F48
+P 6700 5200
+F 0 "VCCO_3V3_27" H 6700 5200 20  0000 C CNN
+F 1 "+VCCO_3V3" H 6700 5130 30  0000 C CNN
+F 2 "" H 6700 5200 70  0000 C CNN
+F 3 "" H 6700 5200 70  0000 C CNN
+	1    6700 5200
+	1    0    0    -1  
+$EndComp
+$Comp
+L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_28
+U 1 1 58023F47
+P 4400 8900
+F 0 "VCCO_3V3_28" H 4400 8900 20  0000 C CNN
+F 1 "+VCCO_3V3" H 4400 8830 30  0000 C CNN
+F 2 "" H 4400 8900 70  0000 C CNN
+F 3 "" H 4400 8900 70  0000 C CNN
+	1    4400 8900
+	1    0    0    -1  
+$EndComp
+$Comp
+L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_29
+U 1 1 58023F46
+P 1660 4630
+F 0 "VCCO_3V3_29" H 1660 4630 20  0000 C CNN
+F 1 "+VCCO_3V3" H 1660 4560 30  0000 C CNN
+F 2 "" H 1660 4630 70  0000 C CNN
+F 3 "" H 1660 4630 70  0000 C CNN
+	1    1660 4630
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND GND_107
+U 1 1 58023F45
+P 1660 5630
+F 0 "GND_107" H 1660 5630 20  0000 C CNN
+F 1 "+GND" H 1660 5560 30  0000 C CNN
+F 2 "" H 1660 5630 70  0000 C CNN
+F 3 "" H 1660 5630 70  0000 C CNN
+	1    1660 5630
+	1    0    0    -1  
+$EndComp
+$Comp
+L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_30
+U 1 1 58023F44
+P 3360 4300
+F 0 "VCCO_3V3_30" H 3360 4300 20  0000 C CNN
+F 1 "+VCCO_3V3" H 3360 4230 30  0000 C CNN
+F 2 "" H 3360 4300 70  0000 C CNN
+F 3 "" H 3360 4300 70  0000 C CNN
+	1    3360 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND GND_108
+U 1 1 58023F43
+P 2960 7930
+F 0 "GND_108" H 2960 7930 20  0000 C CNN
+F 1 "+GND" H 2960 7860 30  0000 C CNN
+F 2 "" H 2960 7930 70  0000 C CNN
+F 3 "" H 2960 7930 70  0000 C CNN
+	1    2960 7930
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7600 6600 7600 7300
+Wire Wire Line
+	7700 6600 7600 6600
+Wire Wire Line
+	6700 7100 6700 7300
+Wire Wire Line
+	10000 7000 10000 7300
+Wire Wire Line
+	5000 9700 5000 10000
+Wire Wire Line
+	5100 9700 5000 9700
+Wire Wire Line
+	4400 9800 4400 10000
+Wire Wire Line
+	1660 5530 1660 5630
+Wire Wire Line
+	1660 5430 1660 5530
+Wire Wire Line
+	1260 5330 1260 5530
+Wire Wire Line
+	1660 5530 1260 5530
+Wire Wire Line
+	2960 7830 2960 7930
+Wire Wire Line
+	7600 5500 7600 5700
+Wire Wire Line
+	7600 5500 6700 5500
+Wire Wire Line
+	6700 5200 6700 5500
+Wire Wire Line
+	9400 6300 9150 6300
+Wire Wire Line
+	9400 5500 9400 6300
+Wire Wire Line
+	9400 5500 7600 5500
+Wire Wire Line
+	9400 6400 9150 6400
+Wire Wire Line
+	9400 6300 9400 6400
+Wire Wire Line
+	10000 6400 10000 6700
+Wire Wire Line
+	10000 6400 9400 6400
+Wire Wire Line
+	4400 9300 4400 9500
+Wire Wire Line
+	5000 9300 4400 9300
+Wire Wire Line
+	5100 9300 5000 9300
+Wire Wire Line
+	4400 8900 4400 9300
+Wire Wire Line
+	5400 8900 5000 8900
+Wire Wire Line
+	5000 8900 5000 9300
+Wire Wire Line
+	1660 4730 1660 4830
+Wire Wire Line
+	1660 4630 1660 4730
+Wire Wire Line
+	1260 4730 1260 5030
+Wire Wire Line
+	1660 4730 1260 4730
+Wire Wire Line
+	3360 4420 3360 4500
+Wire Wire Line
+	3360 4300 3360 4420
+Wire Wire Line
+	9770 6500 9150 6500
+Text Label 9150 6500 0 48 ~
+FPGA_PROM_SCLK
+Wire Wire Line
+	4860 5730 4660 5730
+Wire Wire Line
+	4860 5730 4860 6830
+Wire Wire Line
+	4860 6830 4660 6830
+Wire Wire Line
+	5160 5730 4860 5730
+Text Label 5160 5730 0 48 ~
+FPGA_PROM_SCLK
+Wire Wire Line
+	9770 6600 9150 6600
+Text Label 9150 6600 0 48 ~
+FPGA_PROM_MOSI
+Wire Wire Line
+	4960 6930 4660 6930
+Wire Wire Line
+	4960 5830 4960 6930
+Wire Wire Line
+	4960 5830 4660 5830
+Wire Wire Line
+	5160 5830 4960 5830
+Text Label 5160 5830 0 48 ~
+FPGA_PROM_MOSI
+Wire Wire Line
+	7700 6300 7600 6300
+Wire Wire Line
+	7600 6100 7600 6300
+Wire Wire Line
+	7600 6300 6900 6300
+Text Label 6900 6300 0 48 ~
+FPGA_PROM_CS_N
+Wire Wire Line
+	4760 6730 4660 6730
+Wire Wire Line
+	4760 5630 4760 6730
+Wire Wire Line
+	4760 5630 4660 5630
+Wire Wire Line
+	5160 5630 4760 5630
+Text Label 5160 5630 0 48 ~
+FPGA_PROM_CS_N
+Wire Wire Line
+	7700 6400 6900 6400
+Text Label 6900 6400 0 48 ~
+FPGA_PROM_MISO
+Wire Wire Line
+	3660 5930 3560 5930
+Wire Wire Line
+	3560 5930 2980 5930
+Wire Wire Line
+	3660 7030 3560 7030
+Wire Wire Line
+	3560 5930 3560 7030
+Text Label 2980 5930 0 48 ~
+FPGA_PROM_MISO
+Wire Wire Line
+	7700 6500 6700 6500
+Wire Wire Line
+	6700 6500 6700 6700
+Text Label 6900 6500 0 48 ~
+FPGA_PROM_W_N
+Wire Wire Line
+	7000 9500 6700 9500
+Text GLabel 6700 9500 0 48 Input ~ 0
+FPGA_GCLK
+Wire Wire Line
+	6200 9300 6100 9300
+Wire Wire Line
+	6200 8900 6200 9300
+Wire Wire Line
+	6200 8900 5800 8900
+Wire Wire Line
+	3660 6830 3090 6830
+Text GLabel 3090 6830 0 48 Input ~ 0
+FPGA_CFG_SCLK
+Wire Wire Line
+	3660 6930 3090 6930
+Text GLabel 3090 6930 0 48 Input ~ 0
+FPGA_CFG_MOSI
+Wire Wire Line
+	3660 6730 3090 6730
+Text GLabel 3090 6730 0 48 Input ~ 0
+FPGA_CFG_CS_N
+Wire Wire Line
+	5160 7030 4660 7030
+Text GLabel 5160 7030 2 48 Output ~ 0
+FPGA_CFG_MISO
+Wire Wire Line
+	3660 5630 2980 5630
+Text GLabel 2980 5630 0 48 Input ~ 0
+ARM_FPGA_CFG_CS_N
+Wire Wire Line
+	3660 5830 2980 5830
+Text GLabel 2980 5830 0 48 Input ~ 0
+ARM_FPGA_CFG_MOSI
+Wire Wire Line
+	5160 5930 4660 5930
+Text GLabel 5160 5930 2 48 Output ~ 0
+ARM_FPGA_CFG_MISO
+Wire Wire Line
+	3660 5730 2980 5730
+Text GLabel 2980 5730 0 48 Input ~ 0
+ARM_FPGA_CFG_SCLK
+Text Label 3360 5510 1 48 ~
+SPI_A_TRISTATE
+Text Label 3060 7230 0 48 ~
+SPI_B_TRISTATE
+Text GLabel 430 6430 0 48 Input ~ 0
+FPGA_CFG_CTRL_FPGA_DIS
+Wire Wire Line
+	6300 9500 6100 9500
+Text Notes 5320 9730 0    54   ~ 12
+GND
+Text Notes 5320 9330 0    54   ~ 12
+VCC
+Text Notes 5760 9660 0    54   ~ 12
+FO
+Text Notes 5750 9300 0    54   ~ 12
+OE
+Text Notes 1890 6120 0    60   ~ 12
+1
+Text Notes 2190 6120 0    60   ~ 12
+2
+Text Notes 1890 6220 0    60   ~ 12
+3
+Text Notes 2190 6220 0    60   ~ 12
+4
+Text Notes 1890 6320 0    60   ~ 12
+5
+Text Notes 2190 6320 0    60   ~ 12
+6
+Wire Wire Line
+	3360 4900 3360 6130
+Wire Wire Line
+	2960 7230 2960 7430
+Wire Wire Line
+	3660 7230 2960 7230
+Wire Wire Line
+	2960 6230 2960 7230
+Wire Wire Line
+	2360 6230 2960 6230
+Wire Wire Line
+	1560 6430 430 6430
+Wire Wire Line
+	1560 6230 1560 6430
+Wire Wire Line
+	1760 6230 1560 6230
+Wire Wire Line
+	1640 6830 420 6830
+Wire Wire Line
+	1640 6330 1640 6830
+Wire Wire Line
+	1760 6330 1640 6330
+Wire Wire Line
+	2710 6330 2360 6330
+Wire Wire Line
+	2710 4420 2710 6330
+Wire Wire Line
+	3360 4420 2710 4420
+Text Label 420 6830 0 48 ~
+FPGA_PROM_W_N
+Wire Wire Line
+	3360 6130 2360 6130
+Wire Wire Line
+	3660 6130 3360 6130
+Wire Wire Line
+	430 6130 1760 6130
+Text GLabel 430 6130 0 48 Input ~ 0
+FPGA_CFG_CTRL_ARM_ENA
+Connection ~ 3360 4420
+$Comp
+L Cryptech_Alpha:N25Q128A13ES IC3
+U 1 1 58023F42
+P 8400 6550
+F 0 "IC3" H 7890 6290 60  0000 L BNN
+F 1 "N25Q128A13ESE*" H 8100 6920 60  0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:SO08" H 8100 6920 60  0001 C CNN
+F 3 "" H 8100 6920 60  0000 C CNN
+	1    8400 6550
+	1    0    0    -1
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R4
+U 1 1 58023F41
+P 6500 9500
+F 0 "R4" H 6610 9645 60  0000 R TNN
+F 1 "0" H 6460 9660 60  0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 6460 9660 60  0001 C CNN
+F 3 "" H 6460 9660 60  0000 C CNN
+	1    6500 9500
+	-1   0    0    1
+$EndComp
+$Comp
+L Cryptech_Alpha:74*244DW_1 IC2
+U 1 1 58023F40
+P 4160 5830
+F 0 "IC2" H 3830 5300 60  0000 L BNN
+F 1 "MC74AC244DW*" H 3850 5300 60  0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:SO20W" H 3850 5300 60  0001 C CNN
+F 3 "" H 3850 5300 60  0000 C CNN
+	1    4160 5830
+	1    0    0    -1
+$EndComp
+$Comp
+L Cryptech_Alpha:74*244DW_2 IC2_2
+U 1 1 58023F3F
+P 4160 6930
+F 0 "IC2_2" H 3830 6400 60  0000 L BNN
+F 1 "MC74AC244DW*" H 3860 6390 60  0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:SO20W" H 3860 6390 60  0001 C CNN
+F 3 "" H 3860 6390 60  0000 C CNN
+	1    4160 6930
+	1    0    0    -1
+$EndComp
+$Comp
+L Cryptech_Alpha:74*244DW_3 IC2_3
+U 1 1 58023F3E
+P 1660 5130
+F 0 "IC2_3" H 1690 4980 60  0000 L BNN
+F 1 "MC74AC244DW*" H 1860 5110 60  0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:SO20W" H 1860 5110 60  0001 C CNN
+F 3 "" H 1860 5110 60  0000 C CNN
+	1    1660 5130
+	1    0    0    -1
+$EndComp
+$Comp
+L Cryptech_Alpha:ASF* Q5
+U 1 1 58023F3D
+P 5600 9500
+F 0 "Q5" H 5270 9070 60  0000 L BNN
+F 1 "ASFL1-50.000MHZ-EK-T" H 5080 9830 60  0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:ASF" H 5080 9830 60  0001 C CNN
+F 3 "" H 5080 9830 60  0000 C CNN
+	1    5600 9500
+	1    0    0    -1
+$EndComp
+$Comp
+L Cryptech_Alpha:M03X2NO_SILK JP7
+U 1 1 58023F3C
+P 2060 6230
+F 0 "JP7" H 1850 5920 60  0000 L BNN
+	1    2060 6230
+	1    0    0    -1
+F 2 "Cryptech_Alpha_Footprints:PLD-6" H 1850 5920 60  0001 C CNN
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R51
+U 1 1 58023F3B
+P 7600 5900
+F 0 "R51" V 7510 5855 60  0000 R TNN
+F 1 "4.7k" V 7510 5810 60  0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 7510 5810 60  0001 C CNN
+F 3 "" H 7510 5810 60  0000 C CNN
+	1    7600 5900
+	0    -1   -1   0
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R50
+U 1 1 58023F3A
+P 6700 6900
+F 0 "R50" V 6610 6855 60  0000 R TNN
+F 1 "4.7k" V 6620 6800 60  0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 6620 6800 60  0001 C CNN
+F 3 "" H 6620 6800 60  0000 C CNN
+	1    6700 6900
+	0    -1   -1   0
+$EndComp
+$Comp
+L Cryptech_Alpha:C-EUC0402 C111
+U 1 1 58023F39
+P 4400 9600
+F 0 "C111" H 4480 9410 60  0000 L BNN
+	1    4400 9600
+	1    0    0    -1
+F 2 "Cryptech_Alpha_Footprints:C_0402" H 4480 9410 60  0001 C CNN
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R49
+U 1 1 58023F38
+P 5600 8900
+F 0 "R49" H 5710 9045 60  0000 R TNN
+F 1 "0" H 5710 9060 60  0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 5710 9060 60  0001 C CNN
+F 3 "" H 5710 9060 60  0000 C CNN
+	1    5600 8900
+	-1   0    0    1
+$EndComp
+$Comp
+L Cryptech_Alpha:C-EUC0402 C112
+U 1 1 58023F37
+P 10000 6800
+F 0 "C112" H 9660 6615 60  0000 L BNN
+F 1 "0.1uF" H 9660 6530 60  0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:C_0402" H 9660 6530 60  0001 C CNN
+F 3 "" H 9660 6530 60  0000 C CNN
+	1    10000 6800
+	1    0    0    -1
+$EndComp
+$Comp
+L Cryptech_Alpha:C-EUC0402 C110
+U 1 1 58023F36
+P 1260 5130
+F 0 "C110" H 1320 5145 60  0000 L BNN
+F 1 "0.1uF" H 1320 4920 60  0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:C_0402" H 1320 4920 60  0001 C CNN
+F 3 "" H 1320 4920 60  0000 C CNN
+	1    1260 5130
+	1    0    0    -1
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R46
+U 1 1 58023F35
+P 3360 4700
+F 0 "R46" V 3270 4655 60  0000 R TNN
+F 1 "4.7k" V 3340 4590 60  0000 R TNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 3340 4590 60  0001 C CNN
+F 3 "" H 3340 4590 60  0000 C CNN
+	1    3360 4700
+	0    -1   -1   0
+$EndComp
+$Comp
+L Cryptech_Alpha:R-EU_R0402 R47
+U 1 1 58023F34
+P 2960 7630
+F 0 "R47" V 3050 7675 60  0000 L BNN
+F 1 "4.7k" V 3040 7710 60  0000 L BNN
+F 2 "Cryptech_Alpha_Footprints:R_0402" H 3040 7710 60  0001 C CNN
+F 3 "" H 3040 7710 60  0000 C CNN
+	1    2960 7630
+	0    1    1    0
+$EndComp
+$EndSCHEMATC
\ No newline at end of file