diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:14:24 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:14:24 +0300 |
| commit | 59237fb52930aa5495fe25526d5269f05239282e (patch) | |
| tree | 713b82ce1515375b7ab5f7284a4b28e324f3a524 /KiCAD/rev02_12.sch | |
| parent | df87322e903025945ccc4607cabdca46d98318e0 (diff) | |
Entirely routed the design. Not useable right now, so far just reports zero
unrouted nets. Will cleanup next.
Diffstat (limited to 'KiCAD/rev02_12.sch')
| -rw-r--r-- | KiCAD/rev02_12.sch | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/KiCAD/rev02_12.sch b/KiCAD/rev02_12.sch index 7b5ef89..a7d8f58 100644 --- a/KiCAD/rev02_12.sch +++ b/KiCAD/rev02_12.sch @@ -1104,4 +1104,104 @@ Text GLabel 8200 9000 0 50 Input ~ 0 ICE40_LED2 Text GLabel 8200 9100 0 50 Input ~ 0 ICE40_LED1 +Wire Wire Line + 3400 8800 4200 8800 +Text GLabel 3400 8800 0 50 BiDi ~ 0 +ICE40_GPIO_0 +Wire Wire Line + 4200 9000 3400 9000 +Wire Wire Line + 4200 9300 3400 9300 +Wire Wire Line + 4200 9200 3400 9200 +Wire Wire Line + 4200 9100 3400 9100 +Wire Wire Line + 4200 8900 3400 8900 +Wire Wire Line + 4200 8500 3400 8500 +Wire Wire Line + 4200 8700 3400 8700 +Text GLabel 3400 9000 0 50 BiDi ~ 0 +ICE40_GPIO_1 +Text GLabel 3400 9300 0 50 BiDi ~ 0 +ICE40_GPIO_2 +Text GLabel 3400 9200 0 50 BiDi ~ 0 +ICE40_GPIO_7 +Text GLabel 3400 9100 0 50 BiDi ~ 0 +ICE40_GPIO_6 +Text GLabel 3400 8900 0 50 BiDi ~ 0 +ICE40_GPIO_5 +Text GLabel 3400 8500 0 50 BiDi ~ 0 +ICE40_GPIO_4 +Text GLabel 3400 8700 0 50 BiDi ~ 0 +ICE40_GPIO_3 +Wire Wire Line + 4200 7700 3400 7700 +Wire Wire Line + 4200 7800 3400 7800 +Wire Wire Line + 4200 7900 3400 7900 +Wire Wire Line + 4200 8000 3400 8000 +Text GLabel 3400 7700 0 50 Input ~ 0 +ICE40_FPGA_CS_N +Text GLabel 3400 7800 0 50 Input ~ 0 +ICE40_FPGA_SCK +Text GLabel 3400 7900 0 50 Input ~ 0 +ICE40_FPGA_MOSI +Text GLabel 3400 8000 0 50 Output ~ 0 +ICE40_FPGA_MISO +Wire Wire Line + 4200 3050 3400 3050 +Wire Wire Line + 4200 2950 3400 2950 +Wire Wire Line + 4200 2850 3400 2850 +Wire Wire Line + 4200 2650 3400 2650 +Text GLabel 3400 2650 0 50 BiDi ~ 0 +ICE40_GPIO_FPGA_0 +Text GLabel 3400 2850 0 50 BiDi ~ 0 +ICE40_GPIO_FPGA_1 +Text GLabel 3400 2950 0 50 BiDi ~ 0 +ICE40_GPIO_FPGA_2 +Text GLabel 3400 3050 0 50 BiDi ~ 0 +ICE40_GPIO_FPGA_3 +Wire Wire Line + 4200 2550 3400 2550 +Wire Wire Line + 4200 2450 3400 2450 +Wire Wire Line + 4200 2350 3400 2350 +Wire Wire Line + 4200 2250 3400 2250 +Text GLabel 3400 2250 0 50 BiDi ~ 0 +ICE40_GPIO_ARM_3 +Text GLabel 3400 2350 0 50 BiDi ~ 0 +ICE40_GPIO_ARM_0 +Text GLabel 3400 2450 0 50 BiDi ~ 0 +ICE40_GPIO_ARM_2 +Text GLabel 3400 2550 0 50 BiDi ~ 0 +ICE40_GPIO_ARM_1 +Wire Wire Line + 9000 9200 8300 9200 +Text GLabel 8300 9200 0 50 Input ~ 0 +ICE40_JUMPER +Wire Wire Line + 4200 8200 3400 8200 +Wire Wire Line + 4200 8300 3400 8300 +Wire Wire Line + 4200 8400 3400 8400 +Wire Wire Line + 4200 8600 3400 8600 +Text GLabel 3400 8200 0 50 BiDi ~ 0 +ICE40_GPIO_FPGA_4 +Text GLabel 3400 8300 0 50 BiDi ~ 0 +ICE40_GPIO_FPGA_5 +Text GLabel 3400 8400 0 50 BiDi ~ 0 +ICE40_GPIO_FPGA_6 +Text GLabel 3400 8600 0 50 BiDi ~ 0 +ICE40_GPIO_FPGA_7 $EndSCHEMATC |