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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr B 17000 11000
encoding utf-8
Sheet 13 27
Title "rev02_12"
Date "15 10 2016"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 11400 3800 0 84 ~ 17
Master Key Memory
Text Notes 3400 2700 0 84 ~ 17
SPI mux controlling access to the MKM.\nNormally, the FPGA has R/W access to the MKM but on a\ntamper event the tamper detect MCU (AVR) will grab access\nto the MKM and erase the contents.
Text Notes 7800 6100 0 42 ~ 8
Make AVR unable to read the\nMKM by installing this jumper
Text Notes 13630 10230 0 84 ~ 17
Master Key Memory
Text Notes 7500 6200 1 60 ~ 12
JP6
Text Notes 7770 6200 1 60 ~ 12
JP1Q
$Comp
L power:GND #GND_087
U 1 1 58023F8C
P 11300 6500
F 0 "#GND_087" H 11300 6500 20 0000 C CNN
F 1 "+GND" H 11300 6430 30 0000 C CNN
F 2 "" H 11300 6500 70 0000 C CNN
F 3 "" H 11300 6500 70 0000 C CNN
1 11300 6500
1 0 0 -1
$EndComp
$Comp
L Cryptech_Alpha:3V3_BATT #3V3_BATT_08
U 1 1 58023F8B
P 11300 4200
F 0 "#3V3_BATT_08" H 11300 4200 20 0000 C CNN
F 1 "+3V3_BATT" H 11300 4130 30 0000 C CNN
F 2 "" H 11300 4200 70 0000 C CNN
F 3 "" H 11300 4200 70 0000 C CNN
1 11300 4200
1 0 0 -1
$EndComp
$Comp
L Cryptech_Alpha:3V3_BATT #3V3_BATT_09
U 1 1 58023F8A
P 3300 4100
F 0 "#3V3_BATT_09" H 3300 4100 20 0000 C CNN
F 1 "+3V3_BATT" H 3300 4030 30 0000 C CNN
F 2 "" H 3300 4100 70 0000 C CNN
F 3 "" H 3300 4100 70 0000 C CNN
1 3300 4100
1 0 0 -1
$EndComp
$Comp
L Cryptech_Alpha:3V3_BATT #3V3_BATT_010
U 1 1 58023F89
P 10800 4200
F 0 "#3V3_BATT_010" H 10800 4200 20 0000 C CNN
F 1 "+3V3_BATT" H 10800 4130 30 0000 C CNN
F 2 "" H 10800 4200 70 0000 C CNN
F 3 "" H 10800 4200 70 0000 C CNN
1 10800 4200
1 0 0 -1
$EndComp
$Comp
L power:GND #GND_088
U 1 1 58023F88
P 11500 4700
F 0 "#GND_088" H 11500 4700 20 0000 C CNN
F 1 "+GND" H 11500 4630 30 0000 C CNN
F 2 "" H 11500 4700 70 0000 C CNN
F 3 "" H 11500 4700 70 0000 C CNN
1 11500 4700
1 0 0 -1
$EndComp
$Comp
L power:GND #GND_089
U 1 1 58023F87
P 7600 6400
F 0 "#GND_089" H 7600 6400 20 0000 C CNN
F 1 "+GND" H 7600 6330 30 0000 C CNN
F 2 "" H 7600 6400 70 0000 C CNN
F 3 "" H 7600 6400 70 0000 C CNN
1 7600 6400
1 0 0 -1
$EndComp
$Comp
L power:GND #GND_090
U 1 1 58023F86
P 3300 5200
F 0 "#GND_090" H 3300 5200 20 0000 C CNN
F 1 "+GND" H 3300 5130 30 0000 C CNN
F 2 "" H 3300 5200 70 0000 C CNN
F 3 "" H 3300 5200 70 0000 C CNN
1 3300 5200
1 0 0 -1
$EndComp
$Comp
L power:GND #GND_091
U 1 1 58023F85
P 5000 7500
F 0 "#GND_091" H 5000 7500 20 0000 C CNN
F 1 "+GND" H 5000 7430 30 0000 C CNN
F 2 "" H 5000 7500 70 0000 C CNN
F 3 "" H 5000 7500 70 0000 C CNN
1 5000 7500
1 0 0 -1
$EndComp
$Comp
L Cryptech_Alpha:3V3_BATT #3V3_BATT_011
U 1 1 58023F84
P 5000 4100
F 0 "#3V3_BATT_011" H 5000 4100 20 0000 C CNN
F 1 "+3V3_BATT" H 5000 4030 30 0000 C CNN
F 2 "" H 5000 4100 70 0000 C CNN
F 3 "" H 5000 4100 70 0000 C CNN
1 5000 4100
1 0 0 -1
$EndComp
$Comp
L Cryptech_Alpha:3V3_BATT #3V3_BATT_012
U 1 1 58023F83
P 10100 4220
F 0 "#3V3_BATT_012" H 10100 4220 20 0000 C CNN
F 1 "+3V3_BATT" H 10100 4150 30 0000 C CNN
F 2 "" H 10100 4220 70 0000 C CNN
F 3 "" H 10100 4220 70 0000 C CNN
1 10100 4220
1 0 0 -1
$EndComp
Wire Wire Line
11500 4600 11500 4700
Wire Wire Line
7600 6300 7600 6400
Wire Wire Line
3300 5100 3300 5200
Wire Wire Line
2900 4900 2900 5100
Wire Wire Line
3300 5100 2900 5100
Wire Wire Line
5000 7400 5000 7500
Wire Wire Line
11300 4300 11300 5200
Wire Wire Line
11300 4200 11300 4300
Wire Wire Line
3300 4100 3300 4300
Wire Wire Line
3300 4300 2900 4300
Wire Wire Line
2900 4300 2900 4600
Wire Wire Line
3300 4300 3300 4400
Wire Wire Line
10800 4200 10800 4600
Wire Wire Line
5000 4100 5000 4600
$Comp
L Cryptech_Alpha:JP1Q JP6
U 1 1 58023F7B
P 7600 6000
F 0 "JP6" H 7705 6030 60 0000 L BNN
F 1 "~" H 7600 6000 50 0001 C CNN
F 2 "Cryptech_Alpha_Footprints:PLS-2" H 7705 6030 60 0001 C CNN
F 3 "" H 7600 6000 50 0001 C CNN
1 7600 6000
1 0 0 -1
$EndComp
$Comp
L FPGA_Lattice:ICE40UP5K-SG48ITR U11
U 1 1 5EEFEF07
P 14650 2250
F 0 "U11" H 14980 2303 50 0000 L CNN
F 1 "ICE40UP5K-SG48ITR" H 14980 2212 50 0000 L CNN
F 2 "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm" H 14650 900 50 0001 C CNN
F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra" H 14250 3250 50 0001 C CNN
1 14650 2250
1 0 0 -1
$EndComp
$Comp
L FPGA_Lattice:ICE40UP5K-SG48ITR U11
U 2 1 5EF0D127
P 15400 4900
F 0 "U11" H 15400 3825 50 0000 C CNN
F 1 "ICE40UP5K-SG48ITR" H 15400 3734 50 0000 C CNN
F 2 "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm" H 15400 3550 50 0001 C CNN
F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra" H 15000 5900 50 0001 C CNN
2 15400 4900
1 0 0 -1
$EndComp
$EndSCHEMATC
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