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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 27
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 7100 6650 500 300
U 57D8469B
F0 "Introduction" 60
F1 "rev02_00.sch" 60
$EndSheet
$Sheet
S 9900 850 750 400
U 57D84708
F0 "Power" 60
F1 "rev02_01.sch" 60
$EndSheet
$Sheet
S 750 5200 750 400
U 57D8488D
F0 "Entropy source" 60
F1 "rev02_02.sch" 60
$EndSheet
$Sheet
S 6950 3100 750 400
U 57D84936
F0 "STM32 configuration" 60
F1 "rev02_03.sch" 60
$EndSheet
$Sheet
S 6950 2400 750 400
U 57D849FD
F0 "STM32 power" 60
F1 "rev02_04.sch" 60
$EndSheet
$Sheet
S 8700 2400 750 400
U 57D84B22
F0 "SDRAM" 60
F1 "rev02_06.sch" 60
$EndSheet
$Sheet
S 8700 3100 750 400
U 57D84C13
F0 "Keystore memory" 60
F1 "rev02_07.sch" 60
$EndSheet
$Sheet
S 8700 3800 750 400
U 57D84C55
F0 "Real Time Clock" 60
F1 "rev02_08.sch" 60
$EndSheet
$Sheet
S 7550 1200 750 400
U 57D84CB3
F0 "User USB UART" 60
F1 "rev02_09.sch" 60
$EndSheet
$Sheet
S 6350 1200 750 400
U 57D84E30
F0 "MGMT USB UART" 60
F1 "rev02_10.sch" 60
$EndSheet
$Sheet
S 5350 5250 750 450
U 57D84FAD
F0 "Tamper Circuitry" 60
F1 "rev02_11.sch" 60
$EndSheet
$Sheet
S 5350 6100 750 400
U 57D8509E
F0 "Master Key Memory" 60
F1 "rev02_12.sch" 60
$EndSheet
$Sheet
S 2100 2100 750 400
U 57D85134
F0 "Config interface" 60
F1 "rev02_13.sch" 60
$EndSheet
$Sheet
S 2100 2700 750 400
U 57D85217
F0 "Unused" 60
F1 "rev02_14.sch" 60
$EndSheet
$Sheet
S 650 1300 750 400
U 57D85260
F0 "Config memory" 60
F1 "rev02_15.sch" 60
$EndSheet
$Sheet
S 2100 3350 750 400
U 57D85319
F0 "Unused banks" 60
F1 "rev02_16.sch" 60
$EndSheet
$Sheet
S 4900 3350 750 400
U 57D85338
F0 "FMC interface" 60
F1 "rev02_17.sch" 60
$EndSheet
$Sheet
S 6950 3800 750 400
U 57D85391
F0 "STM32 IO" 60
F1 "rev02_05.sch" 60
$EndSheet
$Sheet
S 9900 2100 750 400
U 57D853B0
F0 "Power: 1V8 3V3" 60
F1 "rev02_18.sch" 60
$EndSheet
$Sheet
S 2100 4050 750 400
U 57D854CB
F0 "GPIO" 60
F1 "rev02_19.sch" 60
$EndSheet
$Sheet
S 4900 4050 750 400
U 57D8556F
F0 "MKM interface" 60
F1 "rev02_20.sch" 60
$EndSheet
$Sheet
S 3500 4050 750 400
U 57D8559C
F0 "PWR and GND" 60
F1 "rev02_21.sch" 60
$EndSheet
$Sheet
S 3500 2700 750 400
U 57D855DE
F0 "Core and AUX bypass" 60
F1 "rev02_22.sch" 60
$EndSheet
$Sheet
S 3500 3350 750 400
U 57D8583B
F0 "VCCO bypass" 60
F1 "rev02_23.sch" 60
$EndSheet
$Sheet
S 9900 1500 750 400
U 57D85A75
F0 "Power: 1V0" 60
F1 "rev02_24.sch" 60
$EndSheet
$Sheet
S 3500 2100 750 400
U 57D85B19
F0 "Power sequencing" 60
F1 "rev02_25.sch" 60
$EndSheet
Wire Notes Line
6400 2200 6400 4400
Wire Notes Line
6400 4400 8300 4400
Wire Notes Line
8300 4400 8300 2200
Wire Notes Line
8300 2200 6400 2200
Text Notes 6450 2350 0 98 ~ 20
STM32
Wire Wire Line
8700 3300 8300 3300
Wire Wire Line
8700 4000 8300 4000
Wire Wire Line
7950 1700 7950 2200
Wire Wire Line
6750 1700 6750 2200
Wire Bus Line
8200 2600 8700 2600
Text Label 8350 2600 0 60 ~ 0
FMC
Wire Notes Line
1950 1800 1950 4700
Wire Notes Line
1950 4700 6000 4700
Wire Notes Line
6000 4700 6000 1800
Wire Notes Line
6000 1800 1950 1800
Text Notes 2050 1950 0 98 ~ 20
FPGA
Wire Wire Line
1400 1500 1650 1500
Wire Wire Line
1650 1500 1650 2300
Wire Wire Line
1650 2300 2100 2300
Wire Wire Line
1500 5400 3150 5400
Wire Wire Line
3150 5400 3150 4700
Wire Wire Line
5200 4550 5200 5450
Wire Wire Line
5200 5450 5350 5450
Wire Wire Line
5700 5800 5700 6000
Wire Bus Line
8200 2600 8200 4000
Wire Bus Line
8200 4000 7700 4000
Wire Bus Line
5650 3550 6500 3550
Wire Bus Line
6500 3550 6500 4000
Wire Bus Line
6500 4000 6950 4000
Text Label 6100 3550 0 60 ~ 0
FMC
$EndSCHEMATC
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