//======================================================================
//
// Copyright (c) 2016, NORDUnet A/S All rights reserved.
//
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// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
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//
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// without specific prior written permission.
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`timescale 1ns / 1ps
module modexpa7_modinv32
(
input wire clk,
input wire ena,
output wire rdy,
input wire [31: 0] n0,
output wire [31: 0] n0_modinv
);
//
// Trigger
//
reg ena_dly = 1'b0;
wire ena_trig = ena && !ena_dly;
always @(posedge clk) ena_dly <= ena;
//
// Ready Register
//
reg rdy_reg = 1'b0;
assign rdy = rdy_reg;
//
// Counter
//
reg [7: 0] cnt = 8'd0;
wire [7: 0] cnt_zero = 8'd0;
wire [7: 0] cnt_last = 8'd132;
wire [7: 0] cnt_next = cnt + 1'b1;
wire [1: 0] cnt_phase = cnt[1:0];
wire [5: 0] cnt_cycle = cnt[7:2];
always @(posedge clk)
//
if (cnt == cnt_zero) cnt <= (!rdy_reg && ena_trig) ? cnt_next : cnt_zero;
else cnt <= (cnt == cnt_last) ? cnt_zero : cnt_next;
//
// Enable / Ready Logic
//
always @(posedge clk)
//
if (cnt == cnt_last) rdy_reg <= 1'b1;
else if ((cnt == cnt_zero) && (rdy_reg && !ena)) rdy_reg <= 1'b0;
//
// Output Register
//
reg [31: 0] n0_modinv_reg;
assign n0_modinv = n0_modinv_reg;
//
// Multiplier
//
(* KEEP="TRUE" *)
wire [63: 0] multiplier_out;
wire [31: 0] multiplier_out_masked = multiplier_out[31: 0] & {mask_reg, 1'b1};
dsp_multiplier_a7 dsp_multiplier
(
.clk (clk),
.a (n0),
.b (n0_modinv_reg),
.p (multiplier_out)
);
//
// Mask and Power
//
reg [30: 0] mask_reg;
reg [31: 0] power_reg;
always @(posedge clk)
//
if (cnt_phase == 2'd1) begin
//
if (cnt_cycle == 6'd0) begin
//
mask_reg <= 31'd0;
power_reg <= 32'd1;
//
n0_modinv_reg <= 32'd0;
//
end else begin
//
mask_reg <= { mask_reg[29:0], 1'b1};
power_reg <= {power_reg[30:0], 1'b0};
//
if (multiplier_out_masked != 32'd1)
//
n0_modinv_reg <= n0_modinv_reg + power_reg;
//
end
//
end
endmodule
