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diff --git a/README.md b/README.md new file mode 100644 index 0000000..b2c0d35 --- /dev/null +++ b/README.md @@ -0,0 +1,14 @@ +toggle +====== +## Introduction ## + +This repo contains a simple deign that toggles an ouput pin. The toggle +is in sync with the given sys_clk, but the toggle circuit divides down +the clock. The divisor is build time defined. + +The design is used in the Cryptech FPGA design to observe internal +clock frequencies. + + +## Status ## +Has been simulated with Icarus Verilog. |