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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-10-16 11:22:13 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-10-16 11:22:13 +0200
commitd504b392554f0ea17fa947e67cfd772a79d05cc5 (patch)
treecb3977f73b532d57690f99d094105ec7604cb62f
parent77fb7c4d456d71c08eeb09f62d0d544c7693ab6b (diff)
(1) Added register missing from reset code. (2) Cleaned up reset constants. (3) Added missing wire declaration in testbench.HEADmaster
-rw-r--r--src/rtl/mkmif.v1
-rw-r--r--src/rtl/mkmif_core.v4
-rw-r--r--src/tb/tb_mkmif_core.v1
3 files changed, 4 insertions, 2 deletions
diff --git a/src/rtl/mkmif.v b/src/rtl/mkmif.v
index 4f44878..55d9678 100644
--- a/src/rtl/mkmif.v
+++ b/src/rtl/mkmif.v
@@ -154,6 +154,7 @@ module mkmif(
begin
read_op_reg <= 1'h0;
write_op_reg <= 1'h0;
+ init_op_reg <= 1'h0;
addr_reg <= 16'h0;
sclk_div_reg <= DEFAULT_SCLK_DIV;
write_data_reg <= 32'h0;
diff --git a/src/rtl/mkmif_core.v b/src/rtl/mkmif_core.v
index 0f90bf0..9bd5317 100644
--- a/src/rtl/mkmif_core.v
+++ b/src/rtl/mkmif_core.v
@@ -152,8 +152,8 @@ module mkmif_core(
begin
if (!reset_n)
begin
- ready_reg <= 0;
- valid_reg <= 0;
+ ready_reg <= 1'h0;
+ valid_reg <= 1'h0;
read_data_reg <= 32'h0;
mkmif_ctrl_reg <= CTRL_IDLE;
end
diff --git a/src/tb/tb_mkmif_core.v b/src/tb/tb_mkmif_core.v
index 766bc12..9452bbf 100644
--- a/src/tb/tb_mkmif_core.v
+++ b/src/tb/tb_mkmif_core.v
@@ -57,6 +57,7 @@ module tb_mkmif_core();
reg tb_clk;
reg tb_reset_n;
wire tb_spi_sclk;
+ wire tb_cs_n;
wire tb_spi_do;
wire tb_spi_di;
reg tb_read_op;