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status register.
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after the Cryptech audit.
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automatically. It seems to work, but needs a bit more testing.
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after timeout. Status bits looks fishy though.
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support for SW to trigger zeroisation of a loaded key.
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key loaded into the aes core.
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ports in the core to support key status and timeout. Updated core testbench to match the new interface.
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more banks.
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capacity. Does not yet work, but at least the linter is fairly happy.
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blockRAM. Added test case that checks access to the API regs.
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ModelSim.
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debug outputs.
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Fixed boundaries for the block counter. Now we don't read mem out of bounds.
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possible to optimize.
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both wrap and unwrap cases.
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define to something more comprehensible.
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model.
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and implement unwrap.
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correctly. Now we just need to stop processing whe we should.
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correctly. A state is wrong and memory is read too far.
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interface. A bit more kludgy, esp since we need to use bank switching to be able to provide enough address space. But this removes a possible problem of the streaming address counter running wild.
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things go bad and where the isssues are.
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number of operations. Bad news: All values are wrong.
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are starting to work. As in AES is actually initialized and used.
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correctly.
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