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-rw-r--r--src/rtl/keywrap_mem.v99
1 files changed, 97 insertions, 2 deletions
diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v
index 21d3a2b..2076a57 100644
--- a/src/rtl/keywrap_mem.v
+++ b/src/rtl/keywrap_mem.v
@@ -40,10 +40,105 @@
module keywrap_mem
(
- input wire sys_clk,
- input wire reset_n
+ input wire clk,
+ input wire reset_n,
+
+ input wire api_we,
+ input wire [8 : 0] api_addr,
+ input wire [31 : 0] api_wr_data,
+ output wire [31 : 0] api_rd_data,
+
+ input wire core_we,
+ input wire [7 : 0] core_addr,
+ input wire [63 : 0] core_wr_data,
+ output wire [63 : 0] core_rd_data
);
+
+ reg [31 : 0] tmp_api_rd_data;
+ reg [63 : 0] tmp_core_rd_data;
+
+ reg [31 : 0] mem0 [0 : 255];
+ reg [31 : 0] mem0_data;
+ reg [7 : 0] mem0_addr;
+ reg mem0_we;
+
+ reg [31 : 0] mem1 [0 : 255];
+ reg [31 : 0] mem1_data;
+ reg [7 : 0] mem1_addr;
+ reg mem1_we;
+
+
+ //----------------------------------------------------------------
+ // Assignments for ports.
+ //----------------------------------------------------------------
+ assign api_rd_data = tmp_api_rd_data;
+ assign core_rd_data = tmp_core_rd_data;
+
+
+ //----------------------------------------------------------------
+ // mem_access
+ //
+ // Clocked read and write to the memory banks.
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ begin : mem_access
+ tmp_core_rd_data <= {mem1[core_addr], mem0[core_addr]};
+
+ if (api_addr[0])
+ tmp_api_rd_data <= mem1[api_addr[8 : 1]];
+ else
+ tmp_api_rd_data <= mem0[api_addr[8 : 1]];
+
+
+ if (mem0_we)
+ mem0[mem0_addr] <= mem0_data;
+
+ if (mem1_we)
+ mem1[mem1_addr] <= mem1_data;
+ end
+
+
+ //----------------------------------------------------------------
+ // write_mux
+ // Mux that handles priority of writes and selection
+ // of memory bank to write api data to.
+ //----------------------------------------------------------------
+ always @*
+ begin : write_mux
+ mem0_data = 32'h0;
+ mem0_addr = 8'h0;
+ mem0_we = 1'h0;
+ mem1_data = 32'h0;
+ mem1_addr = 8'h0;
+ mem1_we = 1'h0;
+
+ if (core_we)
+ begin
+ mem0_data = core_wr_data[31 : 0];
+ mem0_addr = core_addr;
+ mem0_we = 1'h1;
+ mem1_data = core_wr_data[63 : 32];
+ mem1_addr = core_addr;
+ mem1_we = 1'h1;
+ end
+
+ else if (api_we)
+ begin
+ if (api_addr[0])
+ begin
+ mem1_data = api_wr_data;
+ mem1_addr = api_addr[7 : 0];
+ mem1_we = 1'h1;
+ end
+ else
+ begin
+ mem0_data = api_wr_data;
+ mem0_addr = api_addr[7 : 0];
+ mem0_we = 1'h1;
+ end
+ end
+ end
endmodule // keywrap_mem
//======================================================================