aboutsummaryrefslogtreecommitdiff
path: root/src/rtl/keywrap.v
diff options
context:
space:
mode:
Diffstat (limited to 'src/rtl/keywrap.v')
-rw-r--r--src/rtl/keywrap.v43
1 files changed, 42 insertions, 1 deletions
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index f8fcbd7..b394c9c 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -53,6 +53,11 @@ module keywrap #(parameter ADDR_BITS = 13)
input wire clk,
input wire reset_n,
+ output wire mkm_spi_sclk,
+ output wire mkm_spi_cs_n,
+ input wire mkm_spi_do,
+ output wire mkm_spi_di,
+
input wire cs,
input wire we,
@@ -150,6 +155,12 @@ module keywrap #(parameter ADDR_BITS = 13)
wire [63 : 0] core_a_result;
wire [31 : 0] core_api_rd_data;
+ reg mem_cs;
+ reg mem_we;
+ reg [7 : 0] mem_address;
+ reg [31 : 0] mem_write_data;
+ wire [31 : 0] mem_read_data;
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
@@ -166,7 +177,7 @@ module keywrap #(parameter ADDR_BITS = 13)
//----------------------------------------------------------------
- // core instantiation.
+ // keywrap core instantiation.
//----------------------------------------------------------------
keywrap_core #(.MEM_BITS(MEM_BITS))
core(
@@ -194,6 +205,22 @@ module keywrap #(parameter ADDR_BITS = 13)
.api_rd_data(core_api_rd_data)
);
+ mkmif memory(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .spi_sclk(mkm_spi_sclk),
+ .spi_cs_n(mkm_spi_cs_n),
+ .spi_do(mkm_spi_do),
+ .spi_di(mkm_spi_di),
+
+ .cs(mem_cs),
+ .we(mem_we),
+ .address(mem_address),
+ .write_data(mem_write_data),
+ .read_data(mem_read_data)
+ );
+
//----------------------------------------------------------------
// reg_update
@@ -330,6 +357,20 @@ module keywrap #(parameter ADDR_BITS = 13)
end // else: !if(we)
end // if (cs)
end // block: api
+
+
+ //----------------------------------------------------------------
+ // mkmif_ctrl
+ // Logic needed to handle the integratrion of the mkmif
+ //----------------------------------------------------------------
+ always @*
+ begin : mkmif_ctrl
+ mem_cs = 1'h0;
+ mem_we = 1'h0;
+ mem_address = 8'h0;
+ mem_write_data = 32'h0;
+ end
+
endmodule // keywrap
//======================================================================