diff options
Diffstat (limited to 'src/rtl/keywrap.v')
| -rw-r--r-- | src/rtl/keywrap.v | 49 |
1 files changed, 13 insertions, 36 deletions
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index b394c9c..5604ce4 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -151,16 +151,11 @@ module keywrap #(parameter ADDR_BITS = 13) wire core_ready; wire core_valid; wire [255 : 0] core_key; + wire [255 : 0] core_read_key; wire [63 : 0] core_a_init; wire [63 : 0] core_a_result; wire [31 : 0] core_api_rd_data; - reg mem_cs; - reg mem_we; - reg [7 : 0] mem_address; - reg [31 : 0] mem_write_data; - wire [31 : 0] mem_read_data; - //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -184,6 +179,11 @@ module keywrap #(parameter ADDR_BITS = 13) .clk(clk), .reset_n(reset_n), + .mkm_spi_sclk(mkm_spi_sclk), + .mkm_spi_cs_n(mkm_spi_cs_n), + .mkm_spi_do(mkm_spi_do), + .mkm_spi_di(mkm_spi_di), + .init(init_reg), .next(next_reg), .encdec(encdec_reg), @@ -195,6 +195,7 @@ module keywrap #(parameter ADDR_BITS = 13) .key(core_key), .keylen(keylen_reg), + .read_key(core_read_key), .a_init(core_a_init), .a_result(core_a_result), @@ -205,22 +206,6 @@ module keywrap #(parameter ADDR_BITS = 13) .api_rd_data(core_api_rd_data) ); - mkmif memory( - .clk(clk), - .reset_n(reset_n), - - .spi_sclk(mkm_spi_sclk), - .spi_cs_n(mkm_spi_cs_n), - .spi_do(mkm_spi_do), - .spi_di(mkm_spi_di), - - .cs(mem_cs), - .we(mem_we), - .address(mem_address), - .write_data(mem_write_data), - .read_data(mem_read_data) - ); - //---------------------------------------------------------------- // reg_update @@ -303,6 +288,7 @@ module keywrap #(parameter ADDR_BITS = 13) begin if (we) begin + // Write access if (address == {{PAD{1'h0}}, ADDR_CTRL}) begin init_new = write_data[CTRL_INIT_BIT]; @@ -354,23 +340,14 @@ module keywrap #(parameter ADDR_BITS = 13) if (address == {{PAD{1'h0}}, ADDR_A1}) api_rd_delay_new = core_a_result[31 : 0]; + + // Not correct read key mux. + if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) && + (address <= {{PAD{1'h0}}, ADDR_KEY7})) + api_rd_delay_new = core_read_key[031 : 000]; end // else: !if(we) end // if (cs) end // block: api - - - //---------------------------------------------------------------- - // mkmif_ctrl - // Logic needed to handle the integratrion of the mkmif - //---------------------------------------------------------------- - always @* - begin : mkmif_ctrl - mem_cs = 1'h0; - mem_we = 1'h0; - mem_address = 8'h0; - mem_write_data = 32'h0; - end - endmodule // keywrap //====================================================================== |