diff options
| -rw-r--r-- | src/rtl/keywrap_mkmif.v | 40 | ||||
| -rw-r--r-- | src/tb/tb_keywrap_mkmif.v | 10 |
2 files changed, 33 insertions, 17 deletions
diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v index e2b9302..88af6f8 100644 --- a/src/rtl/keywrap_mkmif.v +++ b/src/rtl/keywrap_mkmif.v @@ -282,27 +282,33 @@ module keywrap_mkmif ( keywrap_mkmif_ctrl_new = CTRL_READ_STATUS_WAIT; keywrap_mkmif_ctrl_we = 1'h1; end + end + + if (write) + begin + ready_new = 1'h0; + ready_we = 1'h1; - if (write) - if (key_status) - begin - key_word_ctr_rst = 1'h1; - keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY; - keywrap_mkmif_ctrl_we = 1'h1; - end - else - begin - mkm_write_op = 1'h1; - mkm_addr_new = MKM_STATUS_WORD; - mkm_addr_we = 1'h1; - mkm_write_data_new = wr_status; - mkm_write_data_we = 1'h1; - keywrap_mkmif_ctrl_new = CTRL_WAIT; - keywrap_mkmif_ctrl_we = 1'h1; - end + if (key_status) + begin + key_word_ctr_rst = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY; + keywrap_mkmif_ctrl_we = 1'h1; + end + else + begin + mkm_write_op = 1'h1; + mkm_addr_new = MKM_STATUS_WORD; + mkm_addr_we = 1'h1; + mkm_write_data_new = wr_status; + mkm_write_data_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; + end end end + CTRL_WAIT: begin if (mkm_ready) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index b22be82..89e93c7 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -61,6 +61,7 @@ module tb_keywrap_mkmif(); integer show_spi; integer show_dut_state; integer show_mem_state; + integer show_mkm_state; reg tb_clk; reg tb_reset_n; @@ -149,6 +150,14 @@ module tb_keywrap_mkmif(); $display("ready: 0x%01x ctrl_state: 0x%02x", dut.ready, dut.keywrap_mkmif_ctrl_reg); $display(); end + + if (show_mkm_state) + begin + $display("MKM control state:"); + $display("ready: 0x%1x ctrl: 0x%1x", dut.mkm_ready, dut.mkm.mkmif_ctrl_reg); + $display(); + end + if (show_mem_state) begin $display("Memory control state:"); @@ -208,6 +217,7 @@ module tb_keywrap_mkmif(); show_spi = 0; show_dut_state = 1; show_mem_state = 1; + show_mkm_state = 1; tb_clk = 1'h0; tb_reset_n = 1'h1; |