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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-08-24 10:44:10 +0200 |
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| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-08-24 10:44:10 +0200 |
| commit | 860dc811015211ac41a33275d974434c323f7422 (patch) | |
| tree | 847d0d714dbc56f256d63d08e7a183a79f4c3020 /src/tech/README.md | |
| parent | 378cce57f387d42aa7bf90d28fb3b1f5559248b2 (diff) | |
Performed Verilog parameter magic to make the design scaleable in terms of capacity. Does not yet work, but at least the linter is fairly happy.
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