Integrated the DUT into the testbench and update Makefile to build the sim target-

1 files changed, 39 insertions, 19 deletions

diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v
index 09fe652..8d42c6d 100644
--- a/src/tb/tb_keywrap_mkmif.v
+++ b/src/tb/tb_keywrap_mkmif.v
@@ -55,8 +55,21 @@ module tb_keywrap_mkm();
   integer error_ctr;
   integer tc_ctr;
 
-  reg                            tb_clk;
-  reg                            tb_reset_n;
+  reg            tb_clk;
+  reg            tb_reset_n;
+  wire           tb_mkm_spi_sclk;
+  wire           tb_mkm_spi_cs_n;
+  reg            tb_mkm_spi_do;
+  wire           tb_mkm_spi_di;
+  reg            tb_init;
+  reg            tb_read;
+  reg            tb_write;
+  reg            tb_key_status;
+  wire           tb_ready;
+  reg [31 : 0]   tb_wr_status;
+  wire [31 : 0]  tb_rd_status;
+  reg [255 : 0]  tb_wr_key;
+  wire [255 : 0] tb_rd_key;
 
 
   //----------------------------------------------------------------
@@ -66,21 +79,21 @@ module tb_keywrap_mkm();
                     .clk(tb_clk),
                     .reset_n(tb_reset_n),
 
-                    .mkm_spi_sclk(),
-                    .mkm_spi_cs_n(),
-                    .mkm_spi_do(),
-                    .mkm_spi_di(),
-
-                    .init(),
-                    .read(),
-                    .write(),
-                    .key_status(),
-                    .ready(),
-
-                    .wr_status(),
-                    .rd_status(),
-                    .wr_key(),
-                    .rd_key
+                    .mkm_spi_sclk(tb_mkm_spi_sclk),
+                    .mkm_spi_cs_n(tb_mkm_spi_cs_n),
+                    .mkm_spi_do(tb_mkm_spi_do),
+                    .mkm_spi_di(tb_mkm_spi_di),
+
+                    .init(tb_init),
+                    .read(tb_read),
+                    .write(tb_write),
+                    .key_status(tb_key_status),
+                    .ready(tb_ready),
+
+                    .wr_status(tb_wr_status),
+                    .rd_status(tb_rd_status),
+                    .wr_key(tb_wr_key),
+                    .rd_key(tb_rd_key)
                    );
 
 
@@ -122,8 +135,15 @@ module tb_keywrap_mkm();
       error_ctr = 0;
       tc_ctr    = 0;
 
-      tb_clk     = 1'h0;
-      tb_reset_n = 1'h1
+      tb_clk        = 1'h0;
+      tb_reset_n    = 1'h1;
+      tb_mkm_spi_do = 1'h0;
+      tb_init       = 1'h0;
+      tb_read       = 1'h0;
+      tb_write      = 1'h0;
+      tb_key_status = 1'h0;
+      tb_wr_status  = 32'h0;
+      tb_wr_key     = 256'h0;
 
       #(CLK_PERIOD);
     end