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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-07-05 13:23:45 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-07-05 13:23:45 +0200
commit3bd8c3e1ca7d1aca7f96b27e157530f45a90d867 (patch)
tree7b27311dd134f794c93860bbb3990cacec485055 /src/tb
parente7aa2b3d029e617f1461343770358e67f3febd32 (diff)
Adding wrap test case with 4096 bit plaintext from NIST. Test result matches model.
Diffstat (limited to 'src/tb')
-rw-r--r--src/tb/tb_keywrap.v306
1 files changed, 299 insertions, 7 deletions
diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v
index 71823b6..d2ea8d8 100644
--- a/src/tb/tb_keywrap.v
+++ b/src/tb/tb_keywrap.v
@@ -357,14 +357,16 @@ module tb_keywrap();
//----------------------------------------------------------------
- // Implements test based on NIST KWP_AE 128 bit key test 4.
+ // test_kwp_ae_128_1
+ // Implements wrap test based on NIST KWP_AE 128 bit key
+ // with 248 bit plaintext.
//----------------------------------------------------------------
- task test_kwp_ae_128_4;
- begin : kwp_ae_128_4
+ task test_kwp_ae_128_1;
+ begin : kwp_ae_128_1
integer i;
tc_ctr = tc_ctr + 1;
- $display("** TC kwp_ae_128_4 START.");
+ $display("** TC kwp_ae_128_1 START.");
// Write key and keylength, we also want to encrypt/wrap.
write_word(ADDR_KEY0, 32'hc03db3cc);
@@ -434,9 +436,297 @@ module tb_keywrap();
$display("mem[0x%07x] = 0x%08x", i, read_data);
end
- $display("** TC kwp_ae_128_4 END.\n");
+ $display("** TC kwp_ae_128_2 END.\n");
end
- endtask // test_kwp_ae_128_4
+ endtask // test_kwp_ae_128_2
+
+
+
+ //----------------------------------------------------------------
+ // test_kwp_ad_128_1
+ // Implements unwrap test based on NIST KWP_AE 128 bit key
+ // with 248 bit plaintext.
+ //----------------------------------------------------------------
+ task test_kwp_ad_128_1;
+ begin : kwp_ad_128_1
+ integer i;
+ tc_ctr = tc_ctr + 1;
+
+ $display("** TC kwp_ad_128_1 START.");
+
+ // Write key and keylength, we also want to encrypt/wrap.
+ write_word(ADDR_KEY0, 32'hc03db3cc);
+ write_word(ADDR_KEY1, 32'h1416dcd1);
+ write_word(ADDR_KEY2, 32'hc069a195);
+ write_word(ADDR_KEY3, 32'ha8d77e3d);
+ write_word(ADDR_CONFIG, 32'h00000001);
+
+
+ // Initialize the AES engine (to expand the key).
+ // Wait for init to complete.
+ // Note, not actually needed to wait. We can write R data during init.
+ $display("* Trying to initialize.");
+ write_word(ADDR_CTRL, 32'h00000001);
+ #(2 * CLK_PERIOD);
+ wait_ready();
+ $display("* Init should be done.");
+
+
+ // Set the length or R in blocks.
+ // Write the R bank to be written to.
+ // Write the R blocks to be processed.
+ write_word(ADDR_RLEN, 32'h00000004);
+ write_word(ADDR_R_BANK, 32'h0);
+
+ write_word(ADDR_R_DATA0 + 0, 32'h46f87f58);
+ write_word(ADDR_R_DATA0 + 1, 32'hcdda4200);
+ write_word(ADDR_R_DATA0 + 2, 32'hf53d99ce);
+ write_word(ADDR_R_DATA0 + 3, 32'h2e49bdb7);
+ write_word(ADDR_R_DATA0 + 4, 32'h6212511f);
+ write_word(ADDR_R_DATA0 + 5, 32'he0cd4d0b);
+ write_word(ADDR_R_DATA0 + 6, 32'h5f37a27d);
+ write_word(ADDR_R_DATA0 + 7, 32'h45a28800);
+
+ // Write magic words to A.
+ write_word(ADDR_A0, 32'ha65959a6);
+ write_word(ADDR_A1, 32'h0000001f);
+
+
+ $display("* Contents of memory and dut before wrap processing:");
+ dump_mem(6);
+
+
+ // Start wrapping and wait for wrap to complete.
+ $display("* Trying to start processing.");
+ write_word(ADDR_CTRL, 32'h00000002);
+ #(2 * CLK_PERIOD);
+ wait_ready();
+ $display("* Processing should be done.");
+
+
+ $display("Contents of memory and dut after wrap processing:");
+ dump_mem(6);
+ dump_dut_state();
+
+
+ // Read and display the A registers.
+ read_word(ADDR_A0);
+ $display("A0 after wrap: 0x%08x", read_data);
+ read_word(ADDR_A1);
+ $display("A1 after wrap: 0x%08x", read_data);
+
+ // Read and display the R blocks that has been processed.
+ for (i = 0 ; i < 8 ; i = i + 1)
+ begin
+ read_word(ADDR_R_DATA0 + i);
+ $display("mem[0x%07x] = 0x%08x", i, read_data);
+ end
+
+ $display("** TC kwp_ad_128_1 END.\n");
+ end
+ endtask // test_kwp_ad_128_1
+
+
+ //----------------------------------------------------------------
+ // test_kwp_ae_128_2
+ // Implements wrap test based on NIST KWP_AE 128 bit key with
+ // 4096 bit plaintext.
+ //----------------------------------------------------------------
+ task test_kwp_ae_128_2;
+ begin : kwp_ae_128_2
+ integer i;
+ tc_ctr = tc_ctr + 1;
+
+ $display("** TC kwp_ae_128_2 START.");
+
+ // Write key and keylength, we also want to encrypt/wrap.
+ write_word(ADDR_KEY0, 32'h6b8ba9cc);
+ write_word(ADDR_KEY1, 32'h9b31068b);
+ write_word(ADDR_KEY2, 32'ha175abfc);
+ write_word(ADDR_KEY3, 32'hc60c1338);
+ write_word(ADDR_CONFIG, 32'h00000001);
+
+
+ // Initialize the AES engine (to expand the key).
+ // Wait for init to complete.
+ $display("* Trying to initialize.");
+ write_word(ADDR_CTRL, 32'h00000001);
+ #(2 * CLK_PERIOD);
+ wait_ready();
+ $display("* Init should be done.");
+
+
+ // Set the length or R in blocks.
+ // Write the R bank to be written to.
+ // Write the R blocks to be processed.
+ write_word(ADDR_RLEN, 32'h00000040);
+ write_word(ADDR_R_BANK, 32'h0);
+
+ write_word(ADDR_R_DATA0 + 0, 32'h8af887c5);
+ write_word(ADDR_R_DATA0 + 1, 32'h8dfbc38e);
+ write_word(ADDR_R_DATA0 + 2, 32'he0423eef);
+ write_word(ADDR_R_DATA0 + 3, 32'hcc0e032d);
+ write_word(ADDR_R_DATA0 + 4, 32'hcc79dd11);
+ write_word(ADDR_R_DATA0 + 5, 32'h6638ca65);
+ write_word(ADDR_R_DATA0 + 6, 32'had75dca2);
+ write_word(ADDR_R_DATA0 + 7, 32'ha2459f13);
+ write_word(ADDR_R_DATA0 + 8, 32'h934dbe61);
+ write_word(ADDR_R_DATA0 + 9, 32'ha62cb26d);
+ write_word(ADDR_R_DATA0 + 10, 32'h8bbddbab);
+ write_word(ADDR_R_DATA0 + 11, 32'hf9bf52bb);
+ write_word(ADDR_R_DATA0 + 12, 32'he137ef1d);
+ write_word(ADDR_R_DATA0 + 13, 32'h3e30eacf);
+ write_word(ADDR_R_DATA0 + 14, 32'h0fe456ec);
+ write_word(ADDR_R_DATA0 + 15, 32'h808d6798);
+ write_word(ADDR_R_DATA0 + 16, 32'hdc29fe54);
+ write_word(ADDR_R_DATA0 + 17, 32'hfa1f784a);
+ write_word(ADDR_R_DATA0 + 18, 32'ha3c11cf3);
+ write_word(ADDR_R_DATA0 + 19, 32'h94050095);
+ write_word(ADDR_R_DATA0 + 20, 32'h81d3f1d5);
+ write_word(ADDR_R_DATA0 + 21, 32'h96843813);
+ write_word(ADDR_R_DATA0 + 22, 32'ha6685e50);
+ write_word(ADDR_R_DATA0 + 23, 32'h3fac8535);
+ write_word(ADDR_R_DATA0 + 24, 32'he0c06ecc);
+ write_word(ADDR_R_DATA0 + 25, 32'ha8561b6a);
+ write_word(ADDR_R_DATA0 + 26, 32'h1f22c578);
+ write_word(ADDR_R_DATA0 + 27, 32'heefb6919);
+ write_word(ADDR_R_DATA0 + 28, 32'h12be2e16);
+ write_word(ADDR_R_DATA0 + 29, 32'h67946101);
+ write_word(ADDR_R_DATA0 + 30, 32'hae8c3501);
+ write_word(ADDR_R_DATA0 + 31, 32'he6c66eb1);
+ write_word(ADDR_R_DATA0 + 32, 32'h7e14f260);
+ write_word(ADDR_R_DATA0 + 33, 32'h8c9ce6fb);
+ write_word(ADDR_R_DATA0 + 34, 32'hab4a1597);
+ write_word(ADDR_R_DATA0 + 35, 32'hed49ccb3);
+ write_word(ADDR_R_DATA0 + 36, 32'h930b1060);
+ write_word(ADDR_R_DATA0 + 37, 32'hf98c97d8);
+ write_word(ADDR_R_DATA0 + 38, 32'hdc4ce81e);
+ write_word(ADDR_R_DATA0 + 39, 32'h35279c4d);
+ write_word(ADDR_R_DATA0 + 40, 32'h30d1bf86);
+ write_word(ADDR_R_DATA0 + 41, 32'hc9b919a3);
+ write_word(ADDR_R_DATA0 + 42, 32'hce4f0109);
+ write_word(ADDR_R_DATA0 + 43, 32'he77929e5);
+ write_word(ADDR_R_DATA0 + 44, 32'h8c4c3aeb);
+ write_word(ADDR_R_DATA0 + 45, 32'h5de1ec5e);
+ write_word(ADDR_R_DATA0 + 46, 32'h0afa38ae);
+ write_word(ADDR_R_DATA0 + 47, 32'h896df912);
+ write_word(ADDR_R_DATA0 + 48, 32'h1c72c255);
+ write_word(ADDR_R_DATA0 + 49, 32'h141f2f5c);
+ write_word(ADDR_R_DATA0 + 50, 32'h9a51be50);
+ write_word(ADDR_R_DATA0 + 51, 32'h72547cf8);
+ write_word(ADDR_R_DATA0 + 52, 32'ha3b06740);
+ write_word(ADDR_R_DATA0 + 53, 32'h4e62f961);
+ write_word(ADDR_R_DATA0 + 54, 32'h5a02479c);
+ write_word(ADDR_R_DATA0 + 55, 32'hf8c202e7);
+ write_word(ADDR_R_DATA0 + 56, 32'hfeb2e258);
+ write_word(ADDR_R_DATA0 + 57, 32'h314e0ebe);
+ write_word(ADDR_R_DATA0 + 58, 32'h62878a5c);
+ write_word(ADDR_R_DATA0 + 59, 32'h4ecd4e9d);
+ write_word(ADDR_R_DATA0 + 60, 32'hf7dab2e1);
+ write_word(ADDR_R_DATA0 + 61, 32'hfa9a7b53);
+ write_word(ADDR_R_DATA0 + 62, 32'h2c2169ac);
+ write_word(ADDR_R_DATA0 + 63, 32'hedb7998d);
+ write_word(ADDR_R_DATA0 + 64, 32'h5cd8a711);
+ write_word(ADDR_R_DATA0 + 65, 32'h8848ce7e);
+ write_word(ADDR_R_DATA0 + 66, 32'he9fb2f68);
+ write_word(ADDR_R_DATA0 + 67, 32'he28c2b27);
+ write_word(ADDR_R_DATA0 + 68, 32'h9ddc064d);
+ write_word(ADDR_R_DATA0 + 69, 32'hb70ad73c);
+ write_word(ADDR_R_DATA0 + 70, 32'h6dbe10c5);
+ write_word(ADDR_R_DATA0 + 71, 32'he1c56a70);
+ write_word(ADDR_R_DATA0 + 72, 32'h9c1407f9);
+ write_word(ADDR_R_DATA0 + 73, 32'h3a727cce);
+ write_word(ADDR_R_DATA0 + 74, 32'h1075103a);
+ write_word(ADDR_R_DATA0 + 75, 32'h4009ae2f);
+ write_word(ADDR_R_DATA0 + 76, 32'h7731b7d7);
+ write_word(ADDR_R_DATA0 + 77, 32'h1756eee1);
+ write_word(ADDR_R_DATA0 + 78, 32'h19b828ef);
+ write_word(ADDR_R_DATA0 + 79, 32'h4ed61eff);
+ write_word(ADDR_R_DATA0 + 80, 32'h16493553);
+ write_word(ADDR_R_DATA0 + 81, 32'h2a94fa8f);
+ write_word(ADDR_R_DATA0 + 82, 32'he62dc2e2);
+ write_word(ADDR_R_DATA0 + 83, 32'h2cf20f16);
+ write_word(ADDR_R_DATA0 + 84, 32'h8ae65f4b);
+ write_word(ADDR_R_DATA0 + 85, 32'h6785286c);
+ write_word(ADDR_R_DATA0 + 86, 32'h253f365f);
+ write_word(ADDR_R_DATA0 + 87, 32'h29453a47);
+ write_word(ADDR_R_DATA0 + 88, 32'h9dc2824b);
+ write_word(ADDR_R_DATA0 + 89, 32'h8bdabd96);
+ write_word(ADDR_R_DATA0 + 90, 32'h2da3b76a);
+ write_word(ADDR_R_DATA0 + 91, 32'he9c8a720);
+ write_word(ADDR_R_DATA0 + 92, 32'h155e158f);
+ write_word(ADDR_R_DATA0 + 93, 32'he389c8cc);
+ write_word(ADDR_R_DATA0 + 94, 32'h7fa6ad52);
+ write_word(ADDR_R_DATA0 + 95, 32'h2c951b5c);
+ write_word(ADDR_R_DATA0 + 96, 32'h236bf964);
+ write_word(ADDR_R_DATA0 + 97, 32'hb5b1bfb0);
+ write_word(ADDR_R_DATA0 + 98, 32'h98a39835);
+ write_word(ADDR_R_DATA0 + 99, 32'h759b9540);
+ write_word(ADDR_R_DATA0 + 100, 32'h4b72b17f);
+ write_word(ADDR_R_DATA0 + 101, 32'h7dbcda93);
+ write_word(ADDR_R_DATA0 + 102, 32'h6177ae05);
+ write_word(ADDR_R_DATA0 + 103, 32'h9269f41e);
+ write_word(ADDR_R_DATA0 + 104, 32'hcdac81a4);
+ write_word(ADDR_R_DATA0 + 105, 32'h9f5bbfd2);
+ write_word(ADDR_R_DATA0 + 106, 32'he801392a);
+ write_word(ADDR_R_DATA0 + 107, 32'h043ef068);
+ write_word(ADDR_R_DATA0 + 108, 32'h73550a67);
+ write_word(ADDR_R_DATA0 + 109, 32'hfcbc039f);
+ write_word(ADDR_R_DATA0 + 110, 32'h0b5d30ce);
+ write_word(ADDR_R_DATA0 + 111, 32'h490baa97);
+ write_word(ADDR_R_DATA0 + 112, 32'h9dbbaf9e);
+ write_word(ADDR_R_DATA0 + 113, 32'h53d45d7e);
+ write_word(ADDR_R_DATA0 + 114, 32'h2dff26b2);
+ write_word(ADDR_R_DATA0 + 115, 32'hf7e6628d);
+ write_word(ADDR_R_DATA0 + 116, 32'hed694217);
+ write_word(ADDR_R_DATA0 + 117, 32'ha39f454b);
+ write_word(ADDR_R_DATA0 + 118, 32'h288e7906);
+ write_word(ADDR_R_DATA0 + 119, 32'hb79faf4a);
+ write_word(ADDR_R_DATA0 + 120, 32'h407a7d20);
+ write_word(ADDR_R_DATA0 + 121, 32'h7646f930);
+ write_word(ADDR_R_DATA0 + 122, 32'h96a157f0);
+ write_word(ADDR_R_DATA0 + 123, 32'hd1dca05a);
+ write_word(ADDR_R_DATA0 + 124, 32'h7f92e318);
+ write_word(ADDR_R_DATA0 + 125, 32'hfc1ff62c);
+ write_word(ADDR_R_DATA0 + 126, 32'he2de7f12);
+ write_word(ADDR_R_DATA0 + 127, 32'h9b187053);
+
+ // Write magic words to A.
+ write_word(ADDR_A0, 32'ha65959a6);
+ write_word(ADDR_A1, 32'h00000200);
+
+ $display("* Contents of memory and dut before wrap processing:");
+ dump_mem(65);
+
+ // Start wrapping and wait for wrap to complete.
+ $display("* Trying to start processing.");
+ write_word(ADDR_CTRL, 32'h00000002);
+ #(2 * CLK_PERIOD);
+ wait_ready();
+ $display("* Processing should be done.");
+
+
+ $display("Contents of memory and dut after wrap processing:");
+ dump_mem(65);
+ dump_dut_state();
+
+
+ // Read and display the A registers.
+ read_word(ADDR_A0);
+ $display("A0 after wrap: 0x%08x", read_data);
+ read_word(ADDR_A1);
+ $display("A1 after wrap: 0x%08x", read_data);
+
+ // Read and display the R blocks that has been processed.
+ for (i = 0 ; i < 128 ; i = i + 1)
+ begin
+ read_word(ADDR_R_DATA0 + i);
+ $display("mem[0x%07x] = 0x%08x", i, read_data);
+ end
+
+ $display("** TC kwp_ae_128_2 END.\n");
+ end
+ endtask // test_kwp_ae_128_2
//----------------------------------------------------------------
@@ -454,7 +744,9 @@ module tb_keywrap();
reset_dut();
dump_dut_state();
- test_kwp_ae_128_4();
+ test_kwp_ae_128_1();
+ test_kwp_ad_128_1();
+// test_kwp_ae_128_2();
display_test_results();