diff options
author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-09-28 12:37:04 +0200 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-09-28 12:37:04 +0200 |
commit | 4da2caadb9219e5126ef15ec133faa36e61049c8 (patch) | |
tree | 47a41c664d68970755ae6885130dbfdd84247ef7 /src/rtl/keywrap_core.v | |
parent | 9619025dff8a3a28dea0bc9379f8e33cea1c48dd (diff) |
Integrated new mkmif_core wrapper.
Diffstat (limited to 'src/rtl/keywrap_core.v')
-rw-r--r-- | src/rtl/keywrap_core.v | 71 |
1 files changed, 24 insertions, 47 deletions
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 00e8391..533cc83 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -153,21 +153,6 @@ module keywrap_core #(parameter MEM_BITS = 11) reg iteration_ctr_set; reg iteration_ctr_rst; - reg [31 : 0] mkm_key [0 : 7]; - reg mkm_key_we; - - reg [2 : 0] mkm_word_ctr_reg; - reg [2 : 0] mkm_word_ctr_new; - reg mkm_word_ctr_we; - - reg [7 : 0] mkm_addr_reg; - reg [7 : 0] mkm_addr_new; - reg mkm_addr_we; - - reg [31 : 0] mkm_status_reg; - reg [31 : 0] mkm_status_new; - reg mkm_status_we; - reg [5 : 0] keywrap_core_ctrl_reg; reg [5 : 0] keywrap_core_ctrl_new; reg keywrap_core_ctrl_we; @@ -190,15 +175,14 @@ module keywrap_core #(parameter MEM_BITS = 11) reg [63 : 0] core_wr_data; wire [63 : 0] core_rd_data; - reg mkm_init_op; - reg mkm_read_op; - reg mkm_write_op; + reg mkm_init; + reg mkm_read; + reg mkm_write; + reg mkm_key_status; wire mkm_ready; - wire mkm_valid; - reg [15 : 0] mkm_sclk_div; - reg [15 : 0] mkm_addr; - reg [31 : 0] mkm_write_data; - wire [31 : 0] mkm_read_data; + wire [255 : 0] mkm_key; + wire [31 : 0] mkm_rd_status; + wire [31 : 0] mkm_wr_status; //---------------------------------------------------------------- @@ -239,27 +223,26 @@ module keywrap_core #(parameter MEM_BITS = 11) ); - mkmif_core mkm( - .clk(clk), - .reset_n(reset_n), - - .spi_sclk(mkm_spi_sclk), - .spi_cs_n(mkm_spi_cs_n), - .spi_do(mkm_spi_do), - .spi_di(mkm_spi_di), + keywrap_mkmif mkmif( + .clk(clk), + .reset_n(reset_n), - .init_op(mkm_init_op), - .read_op(mkm_read_op), - .write_op(mkm_write_op), + .mkm_spi_sclk(mkm_spi_sclk), + .mkm_spi_cs_n(mkm_spi_cs_n), + .mkm_spi_do(mkm_spi_do), + .mkm_spi_di(mkm_spi_di), - .ready(mkm_ready), - .valid(mkm_valid), + .init(mkm_init), + .read(mkm_read), + .write(mkm_write), + .key_status(mkm_key_status), + .ready(mkm_ready), - .sclk_div(mkm_sclk_div), - .addr(mkm_addr), - .write_data(mkm_write_data), - .read_data(mkm_read_data) - ); + .wr_status(mkm_wr_status), + .rd_status(mkm_rd_status), + .wr_key(key), + .rd_key(mkm_key) + ); //---------------------------------------------------------------- @@ -280,17 +263,11 @@ module keywrap_core #(parameter MEM_BITS = 11) if (!reset_n) begin - for (i = 0 ; i < 8 ; i = i + 1) - mkm_key[i] <= 32'h0; - a_reg <= 64'h0; ready_reg <= 1'h1; valid_reg <= 1'h1; block_ctr_reg <= {(MEM_BITS - 1){1'h0}}; iteration_ctr_reg <= 3'h0; - mkm_word_ctr_reg <= 3'h0; - mkm_addr_reg <= 8'h0; - mkm_status_reg <= 32'h0; keywrap_core_ctrl_reg <= CTRL_IDLE; end |