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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-09-25 13:44:06 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-09-25 13:44:06 +0200
commit384b029659d9205b32b2d9707c2fa24c554d0b27 (patch)
treea0e91ef4f0cf6584595fc379c2a793b91cefc86a /src/rtl/keywrap_core.v
parent241f9157a534a6f9d953fe06273e2abe2693f4ce (diff)
Integrate the mkmif_core instead of the mkmif wrapper.
Diffstat (limited to 'src/rtl/keywrap_core.v')
-rw-r--r--src/rtl/keywrap_core.v55
1 files changed, 34 insertions, 21 deletions
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 9f9b329..178cea1 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -112,6 +112,8 @@ module keywrap_core #(parameter MEM_BITS = 11)
localparam MKM_STATUS_WORD = 8'h00;
localparam MKM_KEY_BASE_WORD = 8'h04;
+ localparam DEFAULT_SCLK_DIV = 16'h0020;
+
//----------------------------------------------------------------
// Registers and memories including control signals.
@@ -182,9 +184,13 @@ module keywrap_core #(parameter MEM_BITS = 11)
reg [63 : 0] core_wr_data;
wire [63 : 0] core_rd_data;
- reg mkm_cs;
- reg mkm_we;
- reg [7 : 0] mkm_address;
+ reg mkm_init_op;
+ reg mkm_read_op;
+ reg mkm_write_op;
+ wire mkm_ready;
+ wire mkm_valid;
+ reg [15 : 0] mkm_sclk_div;
+ reg [15 : 0] mkm_addr;
reg [31 : 0] mkm_write_data;
wire [31 : 0] mkm_read_data;
@@ -227,21 +233,27 @@ module keywrap_core #(parameter MEM_BITS = 11)
);
- mkmif mkm(
- .clk(clk),
- .reset_n(reset_n),
+ mkmif_core mkm(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .spi_sclk(mkm_spi_sclk),
+ .spi_cs_n(mkm_spi_cs_n),
+ .spi_do(mkm_spi_do),
+ .spi_di(mkm_spi_di),
- .spi_sclk(mkm_spi_sclk),
- .spi_cs_n(mkm_spi_cs_n),
- .spi_do(mkm_spi_do),
- .spi_di(mkm_spi_di),
+ .init_op(mkm_init_op),
+ .read_op(mkm_read_op),
+ .write_op(mkm_write_op),
- .cs(mkm_cs),
- .we(mkm_we),
- .address(mkm_address),
- .write_data(mkm_write_data),
- .read_data(mkm_read_data)
- );
+ .ready(mkm_ready),
+ .valid(mkm_valid),
+
+ .sclk_div(mkm_sclk_div),
+ .addr(mkm_addr),
+ .write_data(mkm_write_data),
+ .read_data(mkm_read_data)
+ );
//----------------------------------------------------------------
@@ -434,12 +446,13 @@ module keywrap_core #(parameter MEM_BITS = 11)
iteration_ctr_dec = 1'h0;
iteration_ctr_set = 1'h0;
iteration_ctr_rst = 1'h0;
- mkm_cs = 1'h0;
- mkm_we = 1'h0;
- mkm_address = 8'h0;
+
+ mkm_init_op = 1'h0;
+ mkm_read_op = 1'h0;
+ mkm_write_op = 1'h0;
+ mkm_sclk_div = DEFAULT_SCLK_DIV;
+ mkm_addr = 16'h0;
mkm_write_data = 32'h0;
- mkm_word_ctr_we = 1'h0;
- mkm_status_we = 1'h0;
keywrap_core_ctrl_new = CTRL_IDLE;
keywrap_core_ctrl_we = 1'h0;