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Diffstat (limited to 'src/rtl/fpga_mkm.v')
-rw-r--r-- | src/rtl/fpga_mkm.v | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/src/rtl/fpga_mkm.v b/src/rtl/fpga_mkm.v new file mode 100644 index 0000000..133a3f8 --- /dev/null +++ b/src/rtl/fpga_mkm.v @@ -0,0 +1,66 @@ +//====================================================================== +// +// fpga_mkm.v +// ---------- +// Top level module for the FPGA based Master Key Memory (MKM). +// +// +// Author: Joachim Strombergson +// Copyright (c) 2019, NORDUnet A/S +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module fpga_mkm ( + input wire clk_in, + output wire rled1, + output wire rled2, + output wire rled3, + output wire rled4, + output wire gled5 + ); + + reg [31 : 0] counter_reg = 32'b0; + + assign rled1 = counter_reg[21]; + assign rled2 = counter_reg[22]; + assign rled3 = counter_reg[23]; + assign rled4 = counter_reg[24]; + assign gled5 = counter_reg[25]; + + always @ (posedge clk_in) + begin + counter_reg <= counter_reg + 1; + end + +endmodule // fpga_mkm + +//====================================================================== +// EOF fpga_mkm.v +//====================================================================== |