1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
G04 Gerber job file with board parameters*
%TF.FileFunction,JobInfo*%
%TF.Part,SinglePCB*%
G04 Single PCB fabrication instructions*
%TF.GenerationSoftware,KiCad,Pcbnew,no-vcs-found-e46fdb0~60~ubuntu17.04.1*%
%TF.CreationDate,2017-09-26T11:00:32+02:00*%
%TF.ProjectId,Cryptech Alpha,437279707465636820416C7068612E6B,rev?*%
%MOMM*%
G04 Overall board parameters*
%TJ.B.Size.X,99.700*%
%TJ.B.Size.Y,122.200*%
%TJ.B.LayerNum,8*%
%TJ.B.Overall.Thickness,1.600*%
%TJ.B.Legend.Present,Both*%
%TJ.B.SolderMask.Present,No*%
G04 board design rules*
%TJ.D.PadToPad.Out,0.127*%
%TJ.D.PadToPad.Inr,0.127*%
%TJ.D.PadToTrack.Out,0.127*%
%TJ.D.PadToTrack.Inr,0.127*%
%TJ.D.TrackToTrack.Out,0.127*%
%TJ.D.TrackToTrack.Inr,0.127*%
%TJ.D.MinLineWidth.Out,0.150*%
%TJ.D.MinLineWidth.Inr,0.100*%
%TJ.D.TrackToRegion.Out,0.150*%
%TJ.D.TrackToRegion.Inr,0.150*%
%TJ.D.RegionToRegion.Out,0.150*%
%TJ.D.RegionToRegion.Inr,0.150*%
G04 Layer Structure*
%TJ.L."Copper,L1,Top",Positive,Cryptech Alpha-F.Cu.gbr*%
%TJ.L."Copper,L2,Inr",Positive,Cryptech Alpha-In1.Cu.gbr*%
%TJ.L."Copper,L3,Inr",Positive,Cryptech Alpha-In2.Cu.gbr*%
%TJ.L."Copper,L4,Inr",Positive,Cryptech Alpha-In3.Cu.gbr*%
%TJ.L."Copper,L5,Inr",Positive,Cryptech Alpha-In4.Cu.gbr*%
%TJ.L."Copper,L6,Inr",Positive,Cryptech Alpha-In5.Cu.gbr*%
%TJ.L."Copper,L7,Inr",Positive,Cryptech Alpha-In6.Cu.gbr*%
%TJ.L."Copper,L8,Bot",Positive,Cryptech Alpha-B.Cu.gbr*%
%TJ.L."Legend,Bot",Positive,Cryptech Alpha-B.SilkS.gbr*%
%TJ.L."Legend,Top",Positive,Cryptech Alpha-F.SilkS.gbr*%
M02*
|
