diff options
Diffstat (limited to 'rev03-KiCad')
| -rw-r--r-- | rev03-KiCad/Cryptech Alpha.kicad_pcb | 7544 |
1 files changed, 3772 insertions, 3772 deletions
diff --git a/rev03-KiCad/Cryptech Alpha.kicad_pcb b/rev03-KiCad/Cryptech Alpha.kicad_pcb index f9c9232..0146ef1 100644 --- a/rev03-KiCad/Cryptech Alpha.kicad_pcb +++ b/rev03-KiCad/Cryptech Alpha.kicad_pcb @@ -3,7 +3,7 @@ (general (links 1412) (no_connects 695) - (area -32.294113 -104.25 148.466654 54.64848) + (area -32.294113 -104.250001 148.466654 54.64848) (thickness 1.6) (drawings 7054) (tracks 9335) @@ -15,12 +15,12 @@ (page A4) (layers (0 F.Cu signal) - (1 In1.Cu signal) - (2 In2.Cu signal) - (3 In3.Cu signal) - (4 In4.Cu signal) + (1 In1.Cu power) + (2 In2.Cu mixed) + (3 In3.Cu power) + (4 In4.Cu power) (5 In5.Cu signal) - (6 In6.Cu signal) + (6 In6.Cu power) (31 B.Cu signal) (32 B.Adhes user) (33 F.Adhes user) @@ -56,8 +56,8 @@ (via_min_drill 0.508) (uvia_size 0.508) (uvia_drill 0.127) - (uvias_allowed no) - (uvia_min_size 0.508) + (uvias_allowed yes) + (uvia_min_size 0.5) (uvia_min_drill 0.127) (pcb_text_width 0.3) (pcb_text_size 1.5 1.5) @@ -748,25 +748,25 @@ (fp_text value "Connector; Header; 10 Position" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 18 AVR_GPIO_1)) - (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 24 AVR_GPIO_7)) - (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 23 AVR_GPIO_6)) - (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 22 AVR_GPIO_5)) - (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 21 AVR_GPIO_4)) - (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 20 AVR_GPIO_3)) - (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 19 AVR_GPIO_2)) - (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 17 AVR_GPIO_0)) - (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) ) @@ -780,9 +780,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 thru_hole rect (at 0 1.27 90) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at 0 1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 2 thru_hole circle (at 0 -1.27 90) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at 0 -1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 211 MKM_AVR_MISO)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/3416A7AC-A52A.wrl (at (xyz 0 0 0)) @@ -864,9 +864,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 283 PWR_18V)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -885,9 +885,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 224 NetC5_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -906,9 +906,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 301 VCC_5V0)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -927,9 +927,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 283 PWR_18V)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -1011,9 +1011,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 5 15V_STABLE)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 225 NetC11_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1032,9 +1032,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 226 NetC12_2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1053,9 +1053,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 5 15V_STABLE)) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -1074,9 +1074,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 275 NOISE_IN)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1095,9 +1095,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 287 RAW_NOISE)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 7 NetC15_2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1116,9 +1116,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1137,9 +1137,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 227 NetC17_2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1158,9 +1158,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 279 OSC_OUT)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1179,9 +1179,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1200,9 +1200,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 277 NRST)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1326,9 +1326,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -1347,9 +1347,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -1368,9 +1368,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1389,9 +1389,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1410,9 +1410,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1431,9 +1431,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1452,9 +1452,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1473,9 +1473,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1494,9 +1494,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1515,9 +1515,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1536,9 +1536,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1557,9 +1557,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1578,9 +1578,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1599,9 +1599,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1620,9 +1620,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1641,9 +1641,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1662,9 +1662,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1683,9 +1683,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1704,9 +1704,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1725,9 +1725,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1746,9 +1746,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1767,9 +1767,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1788,9 +1788,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1809,9 +1809,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1830,9 +1830,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1851,9 +1851,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1872,9 +1872,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1893,9 +1893,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1914,9 +1914,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1935,9 +1935,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1956,9 +1956,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1977,9 +1977,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -1998,9 +1998,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2019,9 +2019,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2040,9 +2040,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2061,9 +2061,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2082,9 +2082,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2103,9 +2103,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2124,9 +2124,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2145,9 +2145,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2166,9 +2166,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2187,9 +2187,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2208,9 +2208,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2229,9 +2229,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2250,9 +2250,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 228 NetC70_2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2271,9 +2271,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 229 NetC71_2)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2292,9 +2292,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 205 FT_VREGIN)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -2313,9 +2313,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 205 FT_VREGIN)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2334,9 +2334,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 202 FT_VCCORE)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2355,9 +2355,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 230 NetC75_2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2376,9 +2376,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 200 FT_VCCA)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2397,9 +2397,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 203 FT_VPHY)) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -2418,9 +2418,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 231 NetC78_2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2439,9 +2439,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 203 FT_VPHY)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2460,9 +2460,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 204 FT_VPLL)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -2481,9 +2481,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 204 FT_VPLL)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2502,9 +2502,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 198 FT_VCC3V3)) - (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -2523,9 +2523,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 198 FT_VCC3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2544,9 +2544,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 198 FT_VCC3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2565,9 +2565,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 198 FT_VCC3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2586,9 +2586,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 198 FT_VCC3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2607,9 +2607,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask) (net 188 FT_MGMT_VREGIN)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -2628,9 +2628,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 188 FT_MGMT_VREGIN)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2649,9 +2649,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 201 FT_VCCORE1)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2670,9 +2670,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 232 NetC90_2)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2691,9 +2691,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 199 FT_VCCA1)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2712,9 +2712,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 186 FT_MGMT_VPHY)) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -2733,9 +2733,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 233 NetC93_2)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2754,9 +2754,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 186 FT_MGMT_VPHY)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2775,9 +2775,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 187 FT_MGMT_VPLL)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -2796,9 +2796,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 187 FT_MGMT_VPLL)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2817,9 +2817,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 185 FT_MGMT_VCC3V3)) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -2838,9 +2838,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 185 FT_MGMT_VCC3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2859,9 +2859,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 185 FT_MGMT_VCC3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2880,9 +2880,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 185 FT_MGMT_VCC3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2901,9 +2901,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 185 FT_MGMT_VCC3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2922,9 +2922,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 3 3V3_BATT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -2943,9 +2943,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 3V3_BATT)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2964,9 +2964,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 3V3_BATT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -2985,9 +2985,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3006,9 +3006,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 3V3_BATT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3027,9 +3027,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 3V3_BATT)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3048,9 +3048,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3069,9 +3069,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3090,9 +3090,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3111,9 +3111,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3132,9 +3132,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3195,9 +3195,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 234 NetC115_1)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3216,9 +3216,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 235 NetC116_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3237,9 +3237,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 236 NetC117_1)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 237 NetC117_2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3258,9 +3258,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 239 NetC118_2)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 238 NetC118_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3321,9 +3321,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3342,9 +3342,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3384,9 +3384,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3405,9 +3405,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3468,9 +3468,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3489,9 +3489,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3510,9 +3510,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3531,9 +3531,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3552,9 +3552,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3594,9 +3594,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3615,9 +3615,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3636,9 +3636,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 174 FPGA_VCCAUX_1V8)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3678,9 +3678,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3699,9 +3699,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3720,9 +3720,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3741,9 +3741,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3762,9 +3762,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3783,9 +3783,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3804,9 +3804,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3825,9 +3825,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3846,9 +3846,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3867,9 +3867,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3888,9 +3888,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3909,9 +3909,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3930,9 +3930,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3951,9 +3951,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -3972,9 +3972,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -3993,9 +3993,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4014,9 +4014,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4035,9 +4035,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4056,9 +4056,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4077,9 +4077,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4098,9 +4098,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4119,9 +4119,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4140,9 +4140,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4161,9 +4161,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4182,9 +4182,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4203,9 +4203,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4224,9 +4224,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 175 FPGA_VCCINT_1V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4329,9 +4329,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4350,9 +4350,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4371,9 +4371,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4392,9 +4392,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4413,9 +4413,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4434,9 +4434,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4455,9 +4455,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4476,9 +4476,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4497,9 +4497,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4518,9 +4518,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4539,9 +4539,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4560,9 +4560,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl (at (xyz 0 0 0)) @@ -4581,9 +4581,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4602,9 +4602,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4623,9 +4623,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4644,9 +4644,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4665,9 +4665,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4686,9 +4686,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4707,9 +4707,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4728,9 +4728,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4749,9 +4749,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4770,9 +4770,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4791,9 +4791,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4812,9 +4812,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4833,9 +4833,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4854,9 +4854,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4875,9 +4875,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4896,9 +4896,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4917,9 +4917,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4938,9 +4938,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4959,9 +4959,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -4980,9 +4980,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5001,9 +5001,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5022,9 +5022,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5043,9 +5043,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5064,9 +5064,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5127,9 +5127,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 240 NetC207_1)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5148,9 +5148,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 242 NetC208_2)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 241 NetC208_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5211,9 +5211,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 285 PWR_ENA_VCCINT)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5232,9 +5232,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 286 PWR_ENA_VCCO)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5253,9 +5253,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 284 PWR_ENA_VCCAUX)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5274,9 +5274,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 205 FT_VREGIN)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5295,9 +5295,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 188 FT_MGMT_VREGIN)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl (at (xyz 0 0 0)) @@ -5324,14 +5324,14 @@ (net 6 GND)) (pad GND smd rect (at -4.34 2) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad GND smd rect (at 1.6002 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask) + (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad ID smd rect (at 0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)) - (pad D+ smd rect (at 0 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask) + (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)) + (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask) (net 41 D1_P)) - (pad D- smd rect (at -0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask) + (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask) (net 40 D1_N)) - (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask) + (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask) (net 205 FT_VREGIN)) (pad GND smd rect (at -4.34 -3.5052) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) @@ -5356,14 +5356,14 @@ (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) (pad GND smd rect (at -4.34 -3.5052) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask) + (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask) (net 188 FT_MGMT_VREGIN)) - (pad D- smd rect (at -0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask) + (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask) (net 2 DM_N)) - (pad D+ smd rect (at 0 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask) + (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask) (net 1 DM_P)) - (pad ID smd rect (at 0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)) - (pad GND smd rect (at 1.6002 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask) + (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)) + (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (pad GND smd rect (at -4.34 2) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) @@ -5476,9 +5476,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask) (net 198 FT_VCC3V3)) - (pad 2 smd rect (at 0 0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask) (net 203 FT_VPHY)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl (at (xyz 0 0 0)) @@ -5497,9 +5497,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.85 0 90) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.85 0 90) (size 1 0.900001) (layers F.Cu F.Paste F.Mask) (net 204 FT_VPLL)) - (pad 1 smd rect (at -0.85 0 90) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.85 0 90) (size 1 0.900001) (layers F.Cu F.Paste F.Mask) (net 198 FT_VCC3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl (at (xyz 0 0 0)) @@ -5518,9 +5518,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask) (net 185 FT_MGMT_VCC3V3)) - (pad 2 smd rect (at 0 0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask) (net 186 FT_MGMT_VPHY)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl (at (xyz 0 0 0)) @@ -5539,9 +5539,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask) (net 187 FT_MGMT_VPLL)) - (pad 1 smd rect (at 0 -0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask) (net 185 FT_MGMT_VCC3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl (at (xyz 0 0 0)) @@ -5831,16 +5831,16 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)) - (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 277 NRST)) - (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 294 SWDIO)) - (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 293 SWDCLK)) - (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/670BFB14-85C2.wrl (at (xyz 0 0 0)) @@ -5859,17 +5859,17 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 205 FT_VREGIN)) - (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 298 USB_P)) - (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 297 USB_N)) - (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 194 FT_RXD1)) - (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 196 FT_TXD1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl (at (xyz 0 0 0)) @@ -5888,17 +5888,17 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 183 FT_MGMT_TXD1)) - (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 181 FT_MGMT_RXD1)) - (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 295 USB_MGMT_N)) - (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 296 USB_MGMT_P)) - (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 188 FT_MGMT_VREGIN)) - (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl (at (xyz 0 0 0)) @@ -5940,9 +5940,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 244 NetJP2_2)) - (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 4 15V_LDO_ENABLE)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/3416A7AC-A52A.wrl (at (xyz 0 0 0)) @@ -5961,17 +5961,17 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 211 MKM_AVR_MISO)) - (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 3V3_BATT)) - (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 213 MKM_AVR_SCK)) - (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 212 MKM_AVR_MOSI)) - (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 38 AVR_RESET)) - (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl (at (xyz 0 0 0)) @@ -5990,11 +5990,11 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 3 3V3_BATT)) - (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/836C6F64-A2E5.wrl (at (xyz 0 0 0)) @@ -6013,17 +6013,17 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 121 FPGA_CFG_CTRL_ARM_ENA)) - (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 291 SPI_A_TRISTATE)) - (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 122 FPGA_CFG_CTRL_FPGA_DIS)) - (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 292 SPI_B_TRISTATE)) - (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 173 FPGA_PROM_W_N)) - (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl (at (xyz 0 0 0)) @@ -6042,9 +6042,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 245 NetLED1_1)) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6063,9 +6063,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 246 NetLED2_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6084,9 +6084,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 247 NetLED3_1)) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6105,9 +6105,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 248 NetLED4_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6126,9 +6126,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 249 NetLED9_1)) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6147,9 +6147,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 250 NetLED10_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6168,9 +6168,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 251 NetLED11_1)) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6189,9 +6189,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 252 NetLED12_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6210,9 +6210,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 253 NetLED13_1)) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 129 FPGA_DONE_INT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6231,9 +6231,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 254 NetLED14_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6252,9 +6252,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 255 NetLED15_1)) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6273,9 +6273,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 256 NetLED16_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6294,9 +6294,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 257 NetLED17_1)) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6315,9 +6315,9 @@ (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 259 NetLED18_2)) - (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask) (net 258 NetLED18_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl (at (xyz 0 0 0)) @@ -6467,9 +6467,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 283 PWR_18V)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 263 NetR1_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6488,9 +6488,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 263 NetR1_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6509,9 +6509,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 264 NetR3_2)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 263 NetR1_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6530,9 +6530,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 132 FPGA_GCLK)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 262 NetQ5_3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6551,9 +6551,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 260 NetQ1_1)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 131 FPGA_ENTROPY_DISABLE)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6572,9 +6572,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 260 NetQ1_1)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6593,9 +6593,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 4 15V_LDO_ENABLE)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 283 PWR_18V)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6614,9 +6614,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 265 NetR8_1)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 301 VCC_5V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6635,9 +6635,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 265 NetR8_1)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6656,9 +6656,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 287 RAW_NOISE)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 275 NOISE_IN)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6677,9 +6677,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 287 RAW_NOISE)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 5 15V_STABLE)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6698,9 +6698,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 7 NetC15_2)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 8 AMPLIFIED)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6719,9 +6719,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 8 AMPLIFIED)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6740,9 +6740,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 278 OSC_IN)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 227 NetC17_2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6761,9 +6761,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 39 BOOT0)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6782,9 +6782,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 248 NetLED4_1)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 15 ARM_LED3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6803,9 +6803,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 243 NetIC1_3)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6824,9 +6824,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 206 KSM_PROM_CS_N)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6845,9 +6845,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 290 RTC_SDA)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6866,9 +6866,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 289 RTC_SCL)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6887,9 +6887,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 288 RTC_MFP)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6908,9 +6908,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 190 FT_REF)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6929,9 +6929,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 198 FT_VCC3V3)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 192 FT_RESET)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6950,9 +6950,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 189 FT_REF1)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6971,9 +6971,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 185 FT_MGMT_VCC3V3)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 191 FT_RESET1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -6992,9 +6992,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 38 AVR_RESET)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 3V3_BATT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7013,9 +7013,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 35 AVR_LED3)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 252 NetLED12_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7034,9 +7034,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 3 3V3_BATT)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 266 NetR32_2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7055,9 +7055,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 267 NetR33_2)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 3V3_BATT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7076,9 +7076,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 216 MKM_CS_N)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 3V3_BATT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7097,9 +7097,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 253 NetLED13_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7118,9 +7118,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 130 FPGA_DONE)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 129 FPGA_DONE_INT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7139,9 +7139,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 154 FPGA_INIT_B_INT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7160,9 +7160,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 168 FPGA_PROGRAM_B)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7181,9 +7181,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 155 FPGA_INIT_B)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7202,9 +7202,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 161 FPGA_JTAG_TDI)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7223,9 +7223,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 163 FPGA_JTAG_TMS)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7244,9 +7244,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 160 FPGA_JTAG_TCK)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7265,9 +7265,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 291 SPI_A_TRISTATE)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7286,9 +7286,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 292 SPI_B_TRISTATE)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7307,9 +7307,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 261 NetQ5_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7328,9 +7328,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 173 FPGA_PROM_W_N)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7349,9 +7349,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 169 FPGA_PROM_CS_N)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7370,9 +7370,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 268 NetR52_1)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 301 VCC_5V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7391,9 +7391,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 269 NetR53_2)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7412,9 +7412,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 270 NetR54_1)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 301 VCC_5V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7433,9 +7433,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 271 NetR55_2)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7454,9 +7454,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 237 NetC117_2)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 236 NetC117_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7475,9 +7475,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 237 NetC117_2)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7496,9 +7496,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 239 NetC118_2)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 238 NetC118_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7517,9 +7517,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 239 NetC118_2)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7538,9 +7538,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 236 NetC117_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7559,9 +7559,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 238 NetC118_1)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7580,9 +7580,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 154 FPGA_INIT_B_INT)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 153 FPGA_INIT_B_INT1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7601,9 +7601,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 167 FPGA_PROGRAM_B1)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 168 FPGA_PROGRAM_B)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7622,9 +7622,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 255 NetLED15_1)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 150 FPGA_GPIO_LED_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7643,9 +7643,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 272 NetR65_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7664,9 +7664,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 273 NetR66_1)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 301 VCC_5V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7685,9 +7685,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 241 NetC208_1)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 274 NetR67_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7706,9 +7706,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 242 NetC208_2)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 241 NetC208_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7727,9 +7727,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 242 NetC208_2)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7748,9 +7748,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 241 NetC208_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7769,9 +7769,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 127 FPGA_CFG_SCLK1)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 128 FPGA_CFG_SCLK)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7790,9 +7790,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 301 VCC_5V0)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 285 PWR_ENA_VCCINT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7811,9 +7811,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 301 VCC_5V0)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 280 POK_VCCAUX)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7832,9 +7832,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 280 POK_VCCAUX)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 286 PWR_ENA_VCCO)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7853,9 +7853,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 301 VCC_5V0)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 281 POK_VCCINT)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7874,9 +7874,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 281 POK_VCCINT)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 284 PWR_ENA_VCCAUX)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7895,9 +7895,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 301 VCC_5V0)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 282 POK_VCCO)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7916,9 +7916,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 258 NetLED18_1)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 301 VCC_5V0)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7937,9 +7937,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 3V3_BATT)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 214 MKM_CONTROL_AVR_ENA)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7958,9 +7958,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 215 MKM_CONTROL_FPGA_DIS)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -7979,9 +7979,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 3 3V3_BATT)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 37 AVR_PANIC)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8000,9 +8000,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 126 FPGA_CFG_MOSI)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 125 FPGA_CFG_MOSI1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8021,9 +8021,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 123 FPGA_CFG_MISO1)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 124 FPGA_CFG_MISO)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8042,9 +8042,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 120 FPGA_CFG_CS_N)) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 119 FPGA_CFG_CS_N1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8063,9 +8063,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 196 FT_TXD1)) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 197 FT_TXD)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8084,9 +8084,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 195 FT_RXD)) - (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 194 FT_RXD1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8105,9 +8105,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 183 FT_MGMT_TXD1)) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 184 FT_MGMT_TXD)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8126,9 +8126,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 182 FT_MGMT_RXD)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 181 FT_MGMT_RXD1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8147,9 +8147,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 184 FT_MGMT_TXD)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8168,9 +8168,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 197 FT_TXD)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8189,9 +8189,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 14 ARM_LED2)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 245 NetLED1_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8210,9 +8210,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 247 NetLED3_1)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 13 ARM_LED1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8231,9 +8231,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 16 ARM_LED4)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 246 NetLED2_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8252,9 +8252,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 249 NetLED9_1)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 34 AVR_LED2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8273,9 +8273,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 33 AVR_LED1)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 251 NetLED11_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8294,9 +8294,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 250 NetLED10_1)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 36 AVR_LED4)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8315,9 +8315,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 151 FPGA_GPIO_LED_2)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 256 NetLED16_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8336,9 +8336,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 254 NetLED14_1)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 152 FPGA_GPIO_LED_3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8357,9 +8357,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 149 FPGA_GPIO_LED_0)) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) (net 257 NetLED17_1)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -8422,9 +8422,9 @@ (fp_text value TACTILE_SWITCH (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.449999) (layers F.Cu F.Paste F.Mask) + (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.449999) (layers F.Cu F.Paste F.Mask) + (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (pad B2 smd rect (at -1.8542 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) (net 6 GND)) @@ -8445,21 +8445,21 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) - (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 160 FPGA_JTAG_TCK)) - (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 163 FPGA_JTAG_TMS)) - (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 161 FPGA_JTAG_TDI)) - (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 162 FPGA_JTAG_TDO)) - (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A962434E-CFE5.wrl (at (xyz 0 0 0)) @@ -8478,37 +8478,37 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 140 FPGA_GPIO_A_7)) - (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 139 FPGA_GPIO_A_6)) - (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 138 FPGA_GPIO_A_5)) - (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 137 FPGA_GPIO_A_4)) - (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 136 FPGA_GPIO_A_3)) - (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 135 FPGA_GPIO_A_2)) - (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 134 FPGA_GPIO_A_1)) - (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 133 FPGA_GPIO_A_0)) - (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 6 GND)) - (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) - (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) - (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) - (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B280C847-2543.wrl (at (xyz 0 0 0)) @@ -8527,37 +8527,37 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) - (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) - (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) (net 302 VCCO_3V3)) - (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask) + 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(at 4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W6 smd circle (at 5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W5 smd circle (at 6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W4 smd circle (at 7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W3 smd circle (at 8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad W2 smd circle (at 9.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad W2 smd circle (at 9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 217 MKM_FPGA_CS_N)) - (pad W1 smd circle (at 10.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad W1 smd circle (at 10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 219 MKM_FPGA_MOSI)) - (pad V22 smd circle (at -10.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad V21 smd circle (at -9.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu 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6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V16 smd circle (at -4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad V15 smd circle (at -3.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad V14 smd circle (at -2.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad V13 smd circle (at -1.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad V12 smd circle (at -0.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad V15 smd circle (at -3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V14 smd circle (at -2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V13 smd circle (at -1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V12 smd circle (at -0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 160 FPGA_JTAG_TCK)) - (pad V11 smd circle (at 0.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad V11 smd circle (at 0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad V10 smd circle (at 1.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad V9 smd circle (at 2.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad V8 smd circle (at 3.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad V7 smd circle (at 4.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad V6 smd circle (at 5.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad V10 smd circle (at 1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V9 smd circle (at 2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V8 smd circle (at 3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V7 smd circle (at 4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V6 smd circle (at 5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad V5 smd circle (at 6.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad V5 smd circle (at 6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 106 FMC_NE1)) - (pad V4 smd circle (at 7.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad V4 smd circle (at 7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 93 FMC_D23)) - (pad V3 smd circle (at 8.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad V3 smd circle (at 8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 220 MKM_FPGA_SCK)) - (pad V2 smd circle (at 9.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad V2 smd circle (at 9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 56 FMC_A13)) - (pad V1 smd circle (at 10.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad V1 smd circle (at 10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad U22 smd circle (at -10.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U22 smd circle (at -10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 272 NetR65_1)) - (pad U21 smd circle (at -9.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad U20 smd circle (at -8.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U21 smd circle (at -9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U20 smd circle (at -8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 82 FMC_D12)) - (pad U19 smd circle (at -7.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U19 smd circle (at -7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad U18 smd circle (at -6.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad U17 smd circle (at -5.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad U16 smd circle (at -4.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad U15 smd circle (at -3.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad U14 smd circle (at -2.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U18 smd circle (at -6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U17 smd circle (at -5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U16 smd circle (at -4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U15 smd circle (at -3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U14 smd circle (at -2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad U13 smd circle (at -1.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U13 smd circle (at -1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 162 FPGA_JTAG_TDO)) - (pad U12 smd circle (at -0.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U12 smd circle (at -0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 153 FPGA_INIT_B_INT1)) - (pad U11 smd circle (at 0.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U11 smd circle (at 0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 164 FPGA_M0)) - (pad U10 smd circle (at 1.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U10 smd circle (at 1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 165 FPGA_M1)) - (pad U9 smd circle (at 2.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U9 smd circle (at 2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 166 FPGA_M2)) - (pad U8 smd circle (at 3.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U8 smd circle (at 3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad U7 smd circle (at 4.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad U6 smd circle (at 5.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad U5 smd circle (at 6.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad U4 smd circle (at 7.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U7 smd circle (at 4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U6 smd circle (at 5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U5 smd circle (at 6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U4 smd circle (at 7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad U3 smd circle (at 8.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U3 smd circle (at 8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 149 FPGA_GPIO_LED_0)) - (pad U2 smd circle (at 9.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U2 smd circle (at 9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 73 FMC_D3)) - (pad U1 smd circle (at 10.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad U1 smd circle (at 10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 72 FMC_D2)) - (pad T22 smd circle (at -10.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad T22 smd circle (at -10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad T21 smd circle (at -9.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad T20 smd circle (at -8.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad T19 smd circle (at -7.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad T21 smd circle (at -9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T20 smd circle (at -8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T19 smd circle (at -7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 119 FPGA_CFG_CS_N1)) - (pad T18 smd circle (at -6.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad T17 smd circle (at -5.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad T18 smd circle (at -6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T17 smd circle (at -5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad T16 smd circle (at -4.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad T15 smd circle (at -3.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad T14 smd circle (at -2.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad T13 smd circle (at -1.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad T16 smd circle (at -4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T15 smd circle (at -3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T14 smd circle (at -2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad 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B.Mask)) + (pad T3 smd circle (at 8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T2 smd circle (at 9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad T1 smd circle (at 10.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad T1 smd circle (at 10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 150 FPGA_GPIO_LED_1)) - (pad R22 smd circle (at -10.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R22 smd circle (at -10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 123 FPGA_CFG_MISO1)) - (pad R21 smd circle (at -9.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R21 smd circle (at -9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 100 FMC_D30)) - (pad R20 smd circle (at -8.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R20 smd circle (at -8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad R19 smd circle (at -7.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad R18 smd circle (at -6.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad R17 smd circle (at -5.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad R16 smd circle (at -4.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad R15 smd circle (at -3.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R19 smd circle (at -7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R18 smd circle (at -6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R17 smd circle (at -5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R16 smd circle (at -4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R15 smd circle (at -3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad R14 smd circle (at -2.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad R13 smd circle (at -1.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R14 smd circle (at -2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R13 smd circle (at -1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 161 FPGA_JTAG_TDI)) - (pad R12 smd circle (at -0.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R12 smd circle (at -0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad R11 smd circle (at 0.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R11 smd circle (at 0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad R10 smd circle (at 1.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R10 smd circle (at 1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad R9 smd circle (at 2.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R9 smd circle (at 2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad R8 smd circle (at 3.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R8 smd circle (at 3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad R7 smd circle (at 4.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R7 smd circle (at 4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad R6 smd circle (at 5.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad R5 smd circle (at 6.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R6 smd circle (at 5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R5 smd circle (at 6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad R4 smd circle (at 7.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R4 smd circle (at 7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 95 FMC_D25)) - (pad R3 smd circle (at 8.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad R2 smd circle (at 9.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad R1 smd circle (at 10.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P22 smd circle (at -10.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad R3 smd circle (at 8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R2 smd circle (at 9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R1 smd circle (at 10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P22 smd circle (at -10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 125 FPGA_CFG_MOSI1)) - (pad P21 smd circle (at -9.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P21 smd circle (at -9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 101 FMC_D31)) - (pad P20 smd circle (at -8.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P19 smd circle (at -7.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P18 smd circle (at -6.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P20 smd circle (at -8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P19 smd circle (at -7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P18 smd circle (at -6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad P17 smd circle (at -5.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P16 smd circle (at -4.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P15 smd circle (at -3.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P14 smd circle (at -2.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P13 smd circle (at -1.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P17 smd circle (at -5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P16 smd circle (at -4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P15 smd circle (at -3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P14 smd circle (at -2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P13 smd circle (at -1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad P12 smd circle (at -0.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P12 smd circle (at -0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad P11 smd circle (at 0.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P11 smd circle (at 0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad P10 smd circle (at 1.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P10 smd circle (at 1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad P9 smd circle (at 2.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P9 smd circle (at 2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad P8 smd circle (at 3.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P8 smd circle (at 3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad P7 smd circle (at 4.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P7 smd circle (at 4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad P6 smd circle (at 5.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P5 smd circle (at 6.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P4 smd circle (at 7.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P3 smd circle (at 8.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P6 smd circle (at 5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P5 smd circle (at 6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P4 smd circle (at 7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P3 smd circle (at 8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad P2 smd circle (at 9.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad P1 smd circle (at 10.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N22 smd circle (at -10.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N21 smd circle (at -9.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad P2 smd circle (at 9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P1 smd circle (at 10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N22 smd circle (at -10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N21 smd circle (at -9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad N20 smd circle (at -8.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N19 smd circle (at -7.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N18 smd circle (at -6.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N17 smd circle (at -5.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N16 smd circle (at -4.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N20 smd circle (at -8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N19 smd circle (at -7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N18 smd circle (at -6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N17 smd circle (at -5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N16 smd circle (at -4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad N15 smd circle (at -3.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N15 smd circle (at -3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 81 FMC_D11)) - (pad N14 smd circle (at -2.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N13 smd circle (at -1.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N12 smd circle (at -0.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N14 smd circle (at -2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N13 smd circle (at -1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N12 smd circle (at -0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 167 FPGA_PROGRAM_B1)) - (pad N11 smd circle (at 0.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N11 smd circle (at 0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad N10 smd circle (at 1.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N10 smd circle (at 1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad N9 smd circle (at 2.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N9 smd circle (at 2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad N8 smd circle (at 3.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N8 smd circle (at 3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad N7 smd circle (at 4.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N7 smd circle (at 4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad N6 smd circle (at 5.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N6 smd circle (at 5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad N5 smd circle (at 6.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N4 smd circle (at 7.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N3 smd circle (at 8.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N2 smd circle (at 9.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad N1 smd circle (at 10.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad N5 smd circle (at 6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N4 smd circle (at 7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N3 smd circle (at 8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N2 smd circle (at 9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N1 smd circle (at 10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad M22 smd circle (at -10.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M21 smd circle (at -9.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M20 smd circle (at -8.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M19 smd circle (at -7.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) - (net 6 GND)) - (pad M18 smd circle (at -6.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M17 smd circle (at -5.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M16 smd circle (at -4.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M15 smd circle (at -3.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M14 smd circle (at -2.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad M22 smd circle (at -10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M21 smd circle (at -9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M20 smd circle (at -8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M19 smd circle (at -7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 6 GND)) + (pad M18 smd circle (at -6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M17 smd circle (at -5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M16 smd circle (at -4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M15 smd circle (at -3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M14 smd circle (at -2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad M13 smd circle (at -1.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M12 smd circle (at -0.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad M13 smd circle (at -1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M12 smd circle (at -0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad M11 smd circle (at 0.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad M11 smd circle (at 0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad M10 smd circle (at 1.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad M10 smd circle (at 1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad M9 smd circle (at 2.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M8 smd circle (at 3.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad M9 smd circle (at 2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M8 smd circle (at 3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad M7 smd circle (at 4.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad M7 smd circle (at 4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad M6 smd circle (at 5.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M5 smd circle (at 6.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M4 smd circle (at 7.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad M6 smd circle (at 5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M5 smd circle (at 6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M4 smd circle (at 7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad M3 smd circle (at 8.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M2 smd circle (at 9.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad M1 smd circle (at 10.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L22 smd circle (at -10.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) - (net 6 GND)) - (pad L21 smd circle (at -9.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L20 smd circle (at -8.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L19 smd circle (at -7.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L18 smd circle (at -6.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L17 smd circle (at -5.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad M3 smd circle (at 8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M2 smd circle (at 9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M1 smd circle (at 10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L22 smd circle (at -10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 6 GND)) + (pad L21 smd circle (at -9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L20 smd circle (at -8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L19 smd circle (at -7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L18 smd circle (at -6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L17 smd circle (at -5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad L16 smd circle (at -4.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L15 smd circle (at -3.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L14 smd circle (at -2.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L13 smd circle (at -1.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L12 smd circle (at -0.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad L16 smd circle (at -4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L15 smd circle (at -3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L14 smd circle (at -2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L13 smd circle (at -1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L12 smd circle (at -0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 127 FPGA_CFG_SCLK1)) - (pad L11 smd circle (at 0.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad L11 smd circle (at 0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad L10 smd circle (at 1.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L9 smd circle (at 2.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad L10 smd circle (at 1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L9 smd circle (at 2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad L8 smd circle (at 3.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad L8 smd circle (at 3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad L7 smd circle (at 4.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad L7 smd circle (at 4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 175 FPGA_VCCINT_1V0)) - (pad L6 smd circle (at 5.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L5 smd circle (at 6.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L4 smd circle (at 7.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L3 smd circle (at 8.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad L2 smd circle (at 9.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) - (net 6 GND)) - (pad L1 smd circle (at 10.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad K22 smd circle (at -10.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad K21 smd circle (at -9.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad K20 smd circle (at -8.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad L6 smd circle (at 5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L5 smd circle (at 6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L4 smd circle (at 7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L3 smd circle (at 8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L2 smd circle (at 9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 6 GND)) + (pad L1 smd circle (at 10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad K22 smd circle (at -10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad K21 smd circle (at -9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad K20 smd circle (at -8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 302 VCCO_3V3)) - (pad K19 smd circle (at -7.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad K18 smd circle (at -6.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu 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(size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 6 GND)) + (pad K14 smd circle (at -2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad K13 smd circle (at -1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad K12 smd circle (at -0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad K11 smd circle (at 0.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad K11 smd circle (at 0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad K10 smd circle (at 1.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad K10 smd circle (at 1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 174 FPGA_VCCAUX_1V8)) - (pad K9 smd circle (at 2.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad K9 smd circle (at 2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad K8 smd circle (at 3.5 -1.5 180) (size 0.449999 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(pad K5 smd circle (at 6.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 6 GND)) + (pad K4 smd circle (at 7.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad K3 smd circle (at 8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad K2 smd circle (at 9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad K1 smd circle (at 10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J22 smd circle (at -10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J21 smd circle (at -9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J20 smd circle (at -8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J19 smd circle (at -7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J18 smd circle (at -6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 6 GND)) + (pad J17 smd circle (at -5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J16 smd 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4.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad A8 smd circle (at 3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A7 smd circle (at 4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad A6 smd circle (at 5.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad A5 smd circle (at 6.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad A6 smd circle (at 5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A5 smd circle (at 6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad A4 smd circle (at 7.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) - (pad A3 smd circle (at 8.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad A4 smd circle (at 7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A3 smd circle (at 8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad A2 smd circle (at 9.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask) + (pad A2 smd circle (at 9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) (net 6 GND)) - (pad A1 smd circle (at 10.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)) + (pad A1 smd circle (at 10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/041B98A5-F02D.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -10922,9 +10922,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) - (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 166 FPGA_M2)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -10943,9 +10943,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 165 FPGA_M1)) - (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 6 GND)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -10964,9 +10964,9 @@ (fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (thickness 0.05))) ) - (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 164 FPGA_M0)) - (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) (net 302 VCCO_3V3)) (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl (at (xyz 0 0 0)) @@ -17165,7 +17165,7 @@ (gr_line (start 72.32 -100.2454) (end 95.32 -100.2454) (layer B.CrtYd) (width 0.254)) (gr_line (start 95.32 -77.7454) (end 95.32 -100.2454) (layer B.CrtYd) (width 0.254)) (gr_text "USB-\r\nUART" (at 57.25 -10.525 90) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text "Alpha rev.03\r\nRadically Open BSD License\r\nhttps://cryptech.is/" (at 16.4 -55.7 90) (layer F.SilkS) (effects (font (size 1.599999 1.599999) (thickness 0.1)) (justify left)) @@ -17174,754 +17174,754 @@ (effects (font (size 1.5 1.5) (thickness 0.1)) (justify left)) ) (gr_text JP5 (at 30.8 4.2) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text JP6 (at 82.85 -27.25) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text C7 (at 72.35 -84.275) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text C11 (at 76.15 -89.9 90) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text C12 (at 72.4 -92.2) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text C13 (at 78.55 -86.675 90) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text C19 (at 11.7 -21.125) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text C20 (at 27.35 -23) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text C35 (at 38.4 -21.6 90) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text C37 (at 39.975 -21.575 90) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) (gr_text C47 (at 96.3 -37.7 90) (layer F.SilkS) - (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left)) + (effects (font (size 1 1) (thickness 0.1)) (justify left)) ) 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