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Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 15 |
1 files changed, 10 insertions, 5 deletions
@@ -23,11 +23,8 @@ All the copper layers convert reasonably well. The challenges are mostly around filled polygons on the various layers. A python script (fix-pcb.py) modifies parameters to get a fairly close result. -Importing WRL files (3D models) required some hacking of the altium2kicad -tool that I haven't been able to work on upstreaming yet. - -Another hack that has not been upstreamed is loading more of the source -files, IIRC to get all component footprints properly converted. +I'm currently looking into ensuring the drill hole sizes are right, and the +non-copper layers have been largely ignored this far. Issues @@ -40,3 +37,11 @@ on those layers. Drill hole sizes have not been checked. KiCAD seems to add ~0.85 mil more clearance around vias. This needs to be double checked but I'm hoping that we can just tolerate that. + +Importing WRL files (3D models) required some hacking of the altium2kicad +tool that I haven't been able to work on upstreaming yet. Something is still +not right here, but the board does have a fair amount of component (including +the more special ones) in KiCAD 3D view. + +Another hack that has not been upstreamed is loading more of the source +files, IIRC to get all component footprints properly converted. |