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-rwxr-xr-xconvert.sh2
-rwxr-xr-xfix-pcb.py (renamed from fix-layer-4.py)116
2 files changed, 82 insertions, 36 deletions
diff --git a/convert.sh b/convert.sh
index 7bc1a4f..b5538ec 100755
--- a/convert.sh
+++ b/convert.sh
@@ -73,7 +73,7 @@ done
# Make a copy used as input file in fix-layer-4.py
cp "Cryptech Alpha.kicad_pcb" "convert.kicad_pcb"
-../fix-layer-4.py "convert.kicad_pcb" "Cryptech Alpha.kicad_pcb"
+../fix-pcb.py "convert.kicad_pcb" "Cryptech Alpha.kicad_pcb"
echo ""
diff --git a/fix-layer-4.py b/fix-pcb.py
index 78f851c..d04d7a5 100755
--- a/fix-layer-4.py
+++ b/fix-pcb.py
@@ -1,17 +1,4 @@
#!/usr/bin/python
-"""
-
-Layer 4 is a layer with large polygons (GND and Power). In Altium, this was made
-like an inverted layer with drawn lines separating polygons. Issues were with
-line thickness in Kicad, clearance parameters preventing copper to flow in between
-pins under the FPGA and the fact that KiCAD doesn't do inverted layers so the
-lines had to be removed and zone clearances adjusted to create the same result.
-
-Compare with
-
- $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In4.Cu.gbr' /path/to/CrypTech.GP3
-
-"""
import sys
import pcbnew
@@ -40,7 +27,26 @@ def remove_tracks(board, layer):
# this.SetLayer(board.GetLayerID(to_layer))
-def layer_zone_fixes(board, layer):
+def hide_layers_except(board, layers):
+ """
+ As a convenience when working on getting a particular layer right, hide other layers.
+ """
+ lset = board.GetVisibleLayers()
+ print('Layer set: {} / {}'.format(lset, lset.FmtHex()))
+ #help(lset)
+ mask = 0
+ for x in lset.Seq():
+ name = board.GetLayerName(x)
+ print(' {} {}'.format(x, name))
+ if name in layers:
+ mask |= 1 << x
+ hexset = '{0:013x}'.format(mask)
+ visible_set = pcbnew.LSET()
+ visible_set.ParseHex(hexset, len(hexset))
+ board.SetVisibleLayers(visible_set)
+
+
+def layer_zone_fixes(board, layer, gnd_clearance=0.25):
for i in range(board.GetAreaCount()):
area = board.GetArea(i)
if area.GetLayerName() != layer:
@@ -60,40 +66,80 @@ def layer_zone_fixes(board, layer):
# 0.25 clearance on the 'background' GND zone keeps the distance to the island
# zones in the bottom half of layer 4, matching the clearance between the areas
# but creating a bit more clearance around vias in KiCAD plot than in Altium
- area.SetZoneClearance(int(0.25 * 1000000))
+ area.SetZoneClearance(int(gnd_clearance * 1000000))
area.SetThermalReliefCopperBridge(int(0.5 * 1000000))
#help(area)
-def hide_layers_except(board, layers):
+def fix_layer_4(board):
"""
- As a convenience when working on getting a particular layer right, hide other layers.
+
+ Layer 4 is a layer with large polygons (GND and Power). In Altium, this was made
+ like an inverted layer with drawn lines separating polygons. Issues were with
+ line thickness in Kicad, clearance parameters preventing copper to flow in between
+ vias under the FPGA and the fact that KiCAD doesn't do inverted layers so the
+ lines had to be removed and zone clearances adjusted to create the same result.
+
+ Compare with
+
+ $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In4.Cu.gbr' /path/to/CrypTech.GP3
"""
- lset = board.GetVisibleLayers()
- print('Layer set: {} / {}'.format(lset, lset.FmtHex()))
- #help(lset)
- mask = 0
- for x in lset.Seq():
- name = board.GetLayerName(x)
- print(' {} {}'.format(x, name))
- if name in layers:
- mask |= 1 << x
- hexset = '{0:013x}'.format(mask)
- visible_set = pcbnew.LSET()
- visible_set.ParseHex(hexset, len(hexset))
- board.SetVisibleLayers(visible_set)
+ remove_tracks(board, 'In4.Cu')
+ #set_tracks_width(board, 'In4.Cu', int(0.15 * 1000000))
+ #move_tracks(board, 'In4.Cu', 'Eco2.User')
+ layer_zone_fixes(board, 'In4.Cu', gnd_clearance=0.25)
+
+
+def fix_layer_6(board):
+ """
+ Layer 6 has a GND polygon that needs a little less clearance in order to fill in between
+ the vias of the FPGA.
+
+ Compare with
+
+ $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In6.Cu.gbr' /path/to/CrypTech.GP4
+ """
+ layer_zone_fixes(board, 'In6.Cu', gnd_clearance=0.15)
+
+
+def fix_layer_bottom(board):
+ """
+ There is one small segment that ends up on Net 1 instead of GND (Net 7) for some reason:
+
+ #Tracks#3898: 200C000500FFFFFFFFFFFFFFFF41A799058A60450341A7990561AE4803E50106000000000000000000FFFF0001
+ - (segment (start 38.75 -74.875) (end 38.75 -75.425) (width 1) (layer B.Cu) (net 1))
+ + (segment (start 38.75 -74.875) (end 38.75 -75.425) (width 1) (layer B.Cu) (net 7))
+
+ I'm guessing the surrounding GND polygon somehow has priority in Altium so this small
+ bug is not visible there. This is a segment connected to one of the seven stiching vias
+ for the GND polygon under and to the right of U14 (bottom left one of the four grouped together).
+
+ The OSHW logo is lost, but I think we can live with that.
+
+ The copper print saying PCB rev.03 is messed up, but I don't think we can expect the fonts
+ to be similar in Altium and KiCAD anyways, so might as well just redo that.
+
+ Compare with
+
+ $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-B.Cu.gbr' /path/to/CrypTech.GBL
+ """
+ for this in [x for x in board.GetTracks() if x.GetLayerName() == 'B.Cu']:
+ if tuple(this.GetStart()) == (38750000, -74875000):
+ print('Moving track to net GND: {}'.format(this))
+ this.SetNet(board.FindNet('GND'))
+
+ layer_zone_fixes(board, 'B.Cu', gnd_clearance=0.15)
def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alpha.kicad_pcb'):
board = pcbnew.LoadBoard(in_fn)
pcbnew.SaveBoard(in_fn + '.before-fix-layer-4', board)
- remove_tracks(board, 'In4.Cu')
- #set_tracks_width(board, 'In4.Cu', int(0.15 * 1000000))
- #move_tracks(board, 'In4.Cu', 'Eco2.User')
- layer_zone_fixes(board, 'In4.Cu')
+ fix_layer_4(board)
+ fix_layer_6(board)
+ fix_layer_bottom(board)
- hide_layers_except(board, ['In4.Cu'])
+ hide_layers_except(board, ['B.Cu'])
# Only show Through Via while working on Layer 4
board.SetVisibleElements(0x7FFC0009)