new attempt with updated upstream tool (still a lot of local changes)

1 files changed, 200 insertions, 200 deletions

diff --git a/rev03-KiCad/rev02_24.sch b/rev03-KiCad/rev02_24.sch
index 3e14445..bc80ab6 100644
--- a/rev03-KiCad/rev02_24.sch
+++ b/rev03-KiCad/rev02_24.sch
@@ -42,409 +42,409 @@ Comment2 ""
 Comment3 ""
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 *) FPGA Power Subsystem -- CORE
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 *) VCCINT = 0.6V x (1 + 150 / 226) = 0.998V\n*) OCP_ADJ is not used (default over-current threshold)\n*) MARx are not used (output at nominal 100%)\n*) S_IN/S_OUT are not used (single regulator mode)\n*) S_DELAY is not used (single regulator mode)\n*) M/S is not used (parallel operation not needed)\n*) EA_OUT is not used (default control loop)\n*) Minimal load current is 0A, but we still place\nload of 100 Ohms just in case (gives 10 mA)
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