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authorFredrik Thulin <fredrik@thulin.net>2018-05-09 17:07:17 +0200
committerFredrik Thulin <fredrik@thulin.net>2018-05-09 17:07:17 +0200
commit97de5e209b1a009be76a79b7a1c3d30eb5b53a04 (patch)
treee3162ecb72a9aee00036b7f29445081955272b5c /rev03-KiCad/rev02_24.sch
parent1f342938585b1cd3b4def00f62e53a5da18a9718 (diff)
parent071cd256c55c4ad9b1f8918df2766d141a0da0f2 (diff)
Merge branch 'ft-add_components'HEADmaster
Diffstat (limited to 'rev03-KiCad/rev02_24.sch')
-rw-r--r--rev03-KiCad/rev02_24.sch36
1 files changed, 35 insertions, 1 deletions
diff --git a/rev03-KiCad/rev02_24.sch b/rev03-KiCad/rev02_24.sch
index 95cca53..94dfe10 100644
--- a/rev03-KiCad/rev02_24.sch
+++ b/rev03-KiCad/rev02_24.sch
@@ -175,7 +175,7 @@ Wire Wire Line
7600 7400 7600 7600
Wire Wire Line
8300 6400 8100 6400
-Text Label 8300 6400 2 48 ~ 0
+Text Label 8300 6400 0 48 ~ 0
FPGA_VCCINT_1V0
Wire Wire Line
1600 6200 1600 6400
@@ -456,4 +456,38 @@ F 3 "" H 5440 7540 60 0000 C CNN
1 5500 7300
0 -1 -1 0
$EndComp
+NoConn ~ 5300 8100
+NoConn ~ 5300 8300
+NoConn ~ 3600 7400
+NoConn ~ 3600 7600
+NoConn ~ 3600 7800
+NoConn ~ 3600 8000
+NoConn ~ 3600 8200
+NoConn ~ 3600 8700
+NoConn ~ 5300 8700
+Wire Wire Line
+ 8300 6400 8300 6200
+$Comp
+L Cryptech_Alpha:FPGA_VCCINT_1V0 #PWR?
+U 1 1 5AF3F25C
+P 8300 6200
+F 0 "#PWR?" H 8300 6050 50 0001 C CNN
+F 1 "FPGA_VCCINT_1V0" H 8315 6373 50 0000 C CNN
+F 2 "" H 8300 6200 60 0000 C CNN
+F 3 "" H 8300 6200 60 0000 C CNN
+ 1 8300 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:PWR_FLAG #FLG?
+U 1 1 5AFA77EC
+P 8150 6400
+F 0 "#FLG?" H 8150 6475 50 0001 C CNN
+F 1 "PWR_FLAG" H 8150 6574 50 0000 C CNN
+F 2 "" H 8150 6400 50 0001 C CNN
+F 3 "~" H 8150 6400 50 0001 C CNN
+ 1 8150 6400
+ 1 0 0 -1
+$EndComp
+Connection ~ 8150 6400
$EndSCHEMATC