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authorFredrik Thulin <fredrik@thulin.net>2017-09-22 09:03:46 +0200
committerFredrik Thulin <fredrik@thulin.net>2017-09-22 09:03:46 +0200
commita2bf24a6a8274b41e1a27fec97498ef7ed4085a5 (patch)
tree16934dc2f7f041b233fe3e3139bf7de1b1eeba03 /rev03-KiCad/rev02_20.sch
parent94b57baa19b06fd9172ef00173578512d17ecf4f (diff)
new attempt with updated upstream tool (still a lot of local changes)
Diffstat (limited to 'rev03-KiCad/rev02_20.sch')
-rw-r--r--rev03-KiCad/rev02_20.sch210
1 files changed, 105 insertions, 105 deletions
diff --git a/rev03-KiCad/rev02_20.sch b/rev03-KiCad/rev02_20.sch
index 52a3a15..3cac044 100644
--- a/rev03-KiCad/rev02_20.sch
+++ b/rev03-KiCad/rev02_20.sch
@@ -42,221 +42,221 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
-Text Notes 1760 3410 0 60 ~ 12
+Text Notes 1600 4100 0 60 ~ 12
*) Lower Right Bank
-Text Notes 4202 7051 0 60 ~ 12
+Text Notes 3820 7410 0 60 ~ 12
DIGITIZED_NOISE signal should go into\neither W19 or Y18 (i.e. into one of the two\npositive (master) sides of the two available\nMRCC differential pairs)
-Text Notes 7150 3410 0 60 ~ 12
+Text Notes 6500 4100 0 60 ~ 12
*) Signals, that are allowed to be swapped, can be be swapped\nwith each other and/or moved to different pins within their bank.
-Text Notes 5280 6050 0 60 ~ 12
+Text Notes 4800 6500 0 60 ~ 12
<-- FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped
-Text Notes 5478 4191 0 60 ~ 12
+Text Notes 4980 4810 0 60 ~ 12
<-- Disable pull-ups on all pins during configuration
-Text Notes 9350 10142 0 84 ~ 12
+Text Notes 8500 10220 0 84 ~ 12
FPGA MKM interface
-Text Notes 4708 4279 0 60 ~ 12
+Text Notes 4280 4890 0 60 ~ 12
R65
-Text Label 4697 4367 0 70 ~
+Text Label 4270 4970 0 70 ~
1k
-Text Label 3718 4532 0 70 ~
+Text Label 3380 5120 0 70 ~
0
-Text Label 3729 4917 0 70 ~
+Text Label 3390 5470 0 70 ~
0
-Text Label 3773 5830 0 70 ~
+Text Label 3430 6300 0 70 ~
0
$Comp
L VCCO_3V3 #PWR?58023EEC
U 1 1 58023EEC
-P 4620 3630
-F 0 "VCCO_3V3_38" H 4620 3630 20 0000 C CNN
-F 1 "+VCCO_3V3" H 4620 3560 30 0000 C CNN
-F 2 "" H 4620 3630 70 0000 C CNN
-F 3 "" H 4620 3630 70 0000 C CNN
- 1 4620 3630
+P 4200 4300
+F 0 "VCCO_3V3_38" H 4200 4300 20 0000 C CNN
+F 1 "+VCCO_3V3" H 4200 4230 30 0000 C CNN
+F 2 "" H 4200 4300 70 0000 C CNN
+F 3 "" H 4200 4300 70 0000 C CNN
+ 1 4200 4300
1 0 0 -1
$EndComp
Wire Wire Line
- 3960 7040 2640 7040
-Text Label 2706 7040 0 70 ~
+ 3600 7400 2400 7400
+Text Label 2460 7400 0 70 ~
DIGITIZED_NOISE
Wire Wire Line
- 3960 6050 2640 6050
-Text Label 2717 6050 0 70 ~
+ 3600 6500 2400 6500
+Text Label 2470 6500 0 70 ~
FPGA_GPIO_LED_2
Wire Wire Line
- 3960 6160 2640 6160
-Text Label 2717 6160 0 70 ~
+ 3600 6600 2400 6600
+Text Label 2470 6600 0 70 ~
FPGA_GPIO_LED_3
Wire Wire Line
- 3960 5940 2640 5940
+ 3600 6400 2400 6400
Wire Wire Line
- 3190 5060 2640 5060
+ 2900 5600 2400 5600
Wire Wire Line
- 2860 3850 2640 3850
+ 2600 4500 2400 4500
Wire Wire Line
- 2860 3850 2860 3960
+ 2600 4500 2600 4600
Wire Wire Line
- 2860 3960 2860 4070
+ 2600 4600 2600 4700
Wire Wire Line
- 2860 4070 2860 4180
+ 2600 4700 2600 4800
Wire Wire Line
- 2860 4180 2860 4290
+ 2600 4800 2600 4900
Wire Wire Line
- 2860 4290 2640 4290
+ 2600 4900 2400 4900
Wire Wire Line
- 2860 4180 2640 4180
+ 2600 4800 2400 4800
Wire Wire Line
- 2860 4070 2640 4070
+ 2600 4700 2400 4700
Wire Wire Line
- 2860 3960 2640 3960
+ 2600 4600 2400 4600
Wire Wire Line
- 3190 3850 2860 3850
+ 2900 4500 2600 4500
Wire Wire Line
- 4620 3630 4620 3850
+ 4200 4300 4200 4500
Wire Wire Line
- 2860 4290 2860 4400
+ 2600 4900 2600 5000
Wire Wire Line
- 2860 4400 2640 4400
+ 2600 5000 2400 5000
Wire Wire Line
- 3960 4620 3850 4620
-Text Label 3960 4620 0 70 ~
+ 3600 5200 3500 5200
+Text Label 3600 5200 0 70 ~
FPGA_CFG_MOSI
Wire Wire Line
- 3960 4730 3850 4730
-Text Label 3960 4730 0 70 ~
+ 3600 5300 3500 5300
+Text Label 3600 5300 0 70 ~
FPGA_CFG_MISO
Wire Wire Line
- 3960 5720 3850 5720
-Text Label 3960 5720 0 70 ~
+ 3600 6200 3500 6200
+Text Label 3600 6200 0 70 ~
FPGA_CFG_CS_N
Wire Wire Line
- 3410 4730 2640 4730
-Text Label 2706 4730 0 70 ~
+ 3100 5300 2400 5300
+Text Label 2460 5300 0 70 ~
FPGA_CFG_MISO1
Wire Wire Line
- 3410 4620 2640 4620
-Text Label 2706 4620 0 70 ~
+ 3100 5200 2400 5200
+Text Label 2460 5200 0 70 ~
FPGA_CFG_MOSI1
Wire Wire Line
- 3410 5720 2640 5720
-Text Label 2706 5720 0 70 ~
+ 3100 6200 2400 6200
+Text Label 2460 6200 0 70 ~
FPGA_CFG_CS_N1
-Text Label 2706 6600 0 70 ~
+Text Label 2460 7000 0 70 ~
FMC_A19
-Text Label 2706 6710 0 70 ~
+Text Label 2460 7100 0 70 ~
FMC_A20
Wire Wire Line
- 3960 6600 2640 6600
+ 3600 7000 2400 7000
Wire Wire Line
- 3960 6710 2640 6710
-Text Label 2706 7810 0 70 ~
+ 3600 7100 2400 7100
+Text Label 2460 8100 0 70 ~
FMC_A21
Wire Wire Line
- 3971 7810 2640 7810
-Text Label 2706 6380 0 70 ~
+ 3610 8100 2400 8100
+Text Label 2460 6800 0 70 ~
FMC_A22
-Text Label 2706 6490 0 70 ~
+Text Label 2460 6900 0 70 ~
FMC_A23
Wire Wire Line
- 3960 6490 2640 6490
+ 3600 6900 2400 6900
Wire Wire Line
- 3960 6380 2640 6380
-Text Label 2706 8250 0 70 ~
+ 3600 6800 2400 6800
+Text Label 2460 8500 0 70 ~
FMC_A24
Wire Wire Line
- 3960 8250 2640 8250
-Text Label 2706 7700 0 70 ~
+ 3600 8500 2400 8500
+Text Label 2460 8000 0 70 ~
FMC_A25
Wire Wire Line
- 3960 7700 2640 7700
-Text Label 2706 7260 0 70 ~
+ 3600 8000 2400 8000
+Text Label 2460 7600 0 70 ~
FMC_D8
Wire Wire Line
- 3960 7260 2640 7260
-Text Label 2706 6270 0 70 ~
+ 3600 7600 2400 7600
+Text Label 2460 6700 0 70 ~
FMC_D9
Wire Wire Line
- 3960 6270 2640 6270
-Text Label 2706 7150 0 70 ~
+ 3600 6700 2400 6700
+Text Label 2460 7500 0 70 ~
FMC_D10
Wire Wire Line
- 3960 7150 2640 7150
-Text Label 2706 6820 0 70 ~
+ 3600 7500 2400 7500
+Text Label 2460 7200 0 70 ~
FMC_D12
Wire Wire Line
- 3960 6820 2640 6820
-Text Label 2706 6930 0 70 ~
+ 3600 7200 2400 7200
+Text Label 2460 7300 0 70 ~
FMC_D28
Wire Wire Line
- 3960 6930 2640 6930
-Text Label 2706 7480 0 70 ~
+ 3600 7300 2400 7300
+Text Label 2460 7800 0 70 ~
FMC_D29
Wire Wire Line
- 3960 7480 2640 7480
-Text Label 2706 4950 0 70 ~
+ 3600 7800 2400 7800
+Text Label 2460 5500 0 70 ~
FMC_D30
Wire Wire Line
- 3410 4950 2640 4950
-Text Label 2706 4840 0 70 ~
+ 3100 5500 2400 5500
+Text Label 2460 5400 0 70 ~
FMC_D31
Wire Wire Line
- 3410 4840 2640 4840
-Text Label 2706 8030 0 70 ~
+ 3100 5400 2400 5400
+Text Label 2460 8300 0 70 ~
FMC_NL
Wire Wire Line
- 3960 8030 2640 8030
-Text Label 2695 9900 0 70 ~
+ 3600 8300 2400 8300
+Text Label 2450 10000 0 70 ~
FMC_D11
Wire Wire Line
- 3960 9900 2640 9900
+ 3600 10000 2400 10000
Wire Wire Line
- 4620 5060 3190 5060
+ 4200 5600 2900 5600
Wire Wire Line
- 4620 4400 4620 5060
+ 4200 5000 4200 5600
Wire Wire Line
- 4620 3850 3190 3850
+ 4200 4500 2900 4500
Wire Wire Line
- 4620 3960 4620 3850
+ 4200 4600 4200 4500
$Comp
L R-EU_R0402 IC289
U 1 1 58023EEB
- 1 4620 4180
+ 1 4200 4800
0 -1 -1 0
$EndComp
$Comp
L R-EU_R0603 R83
U 1 1 58023EEA
-F 0 "R83" H 3751 4532 60 0000 R TNN
-F 1 "" H 3542 4532 60 0000 R TNN
-F 2 "" H 3542 4532 60 0000 C CNN
-F 3 "" H 3542 4532 60 0000 C CNN
- 1 3630 4620
+F 0 "R83" H 3410 5120 60 0000 R TNN
+F 1 "" H 3220 5120 60 0000 R TNN
+F 2 "" H 3220 5120 60 0000 C CNN
+F 3 "" H 3220 5120 60 0000 C CNN
+ 1 3300 5200
-1 0 0 1
$EndComp
$Comp
L R-EU_R0603 R84
U 1 1 58023EE9
-F 0 "R84" H 3740 4928 60 0000 R TNN
-F 1 "" H 3531 4928 60 0000 R TNN
-F 2 "" H 3531 4928 60 0000 C CNN
-F 3 "" H 3531 4928 60 0000 C CNN
- 1 3630 4730
+F 0 "R84" H 3400 5480 60 0000 R TNN
+F 1 "" H 3210 5480 60 0000 R TNN
+F 2 "" H 3210 5480 60 0000 C CNN
+F 3 "" H 3210 5480 60 0000 C CNN
+ 1 3300 5300
-1 0 0 1
$EndComp
$Comp
L R-EU_R0603 R85
U 1 1 58023EE8
-F 0 "R85" H 3498 5720 60 0000 R TNN
-F 1 "" H 3498 5841 60 0000 R TNN
-F 2 "" H 3498 5841 60 0000 C CNN
-F 3 "" H 3498 5841 60 0000 C CNN
- 1 3630 5720
+F 0 "R85" H 3180 6200 60 0000 R TNN
+F 1 "" H 3180 6310 60 0000 R TNN
+F 2 "" H 3180 6310 60 0000 C CNN
+F 3 "" H 3180 6310 60 0000 C CNN
+ 1 3300 6200
-1 0 0 1
$EndComp
$Comp
L XC7A200TFBG484_3 IC293
U 1 1 58023EE7
- 1 2420 6820
+ 1 2200 7200
1 0 0 -1
$EndComp
$EndSCHEMATC \ No newline at end of file