new attempt with updated upstream tool (still a lot of local changes)

1 files changed, 281 insertions, 281 deletions

diff --git a/rev03-KiCad/rev02_19.sch b/rev03-KiCad/rev02_19.sch
index fde475a..ad31198 100644
--- a/rev03-KiCad/rev02_19.sch
+++ b/rev03-KiCad/rev02_19.sch
@@ -42,576 +42,576 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
-Text Notes 1100 3300 0    60   ~ 12
+Text Notes 1000 4000 0    60   ~ 12
 *) Upper Right Bank
-Text Notes 3619 7161 0    60   ~ 12
+Text Notes 3290 7510 0    60   ~ 12
 *) FPGA_GCLK signal _MUST_ go into either D17 or C18\n(i.e. into one of the two positive (master) sides\nof the two available MRCC differential pairs)
-Text Notes 3586 7535 0    60   ~ 12
+Text Notes 3260 7850 0    60   ~ 12
 *) FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped
-Text Notes 7623 3201 0    60   ~ 12
+Text Notes 6930 3910 0    60   ~ 12
 *) Signals, that are allowed to be swapped, can be be swapped\nwith each other and/or moved to different pins within their bank.
-Text Notes 3630 6050 0    60   ~ 12
+Text Notes 3300 6500 0    60   ~ 12
 NOTE: One of the FPGA_GPIO_* pins\nshould be connected to one of the\nMRCC pins.\nThe non-MRCC GPIO signals should be\nlength matched to within 500 ps of\nthe MRCC signal.
-Text Notes 9724 10153 0    84   ~ 12
+Text Notes 8840 10230 0    84   ~ 12
 FPGA GPIO
-Text Notes 9845 3850 2    60   ~ 12
+Text Notes 8950 4500 2    60   ~ 12
 MA08-2
-Text Notes 9845 4983 2    60   ~ 12
+Text Notes 8950 5530 2    60   ~ 12
 SV2
-Text Notes 9845 5940 2    60   ~ 12
+Text Notes 8950 6400 2    60   ~ 12
 MA08-2
-Text Notes 9845 7073 2    60   ~ 12
+Text Notes 8950 7430 2    60   ~ 12
 SV3
-Text Notes 7986 4499 0    60   ~ 12
+Text Notes 7260 5090 0    60   ~ 12
 C121
-Text Label 8052 4609 0 70 ~
+Text Label 7320 5190 0 70 ~
 0.1uF
-Text Notes 7986 6589 0    60   ~ 12
+Text Notes 7260 6990 0    60   ~ 12
 C122
-Text Label 8063 6699 0 70 ~
+Text Label 7330 7090 0 70 ~
 0.1uF
 $Comp
 L GND #PWR?58023F03
 U 1 1 58023F03
-P 7920 5060
-F 0 "GND_125" H 7920 5060 20  0000 C CNN
-F 1 "+GND" H 7920 4990 30  0000 C CNN
-F 2 "" H 7920 5060 70  0000 C CNN
-F 3 "" H 7920 5060 70  0000 C CNN
-	1    7920 5060
+P 7200 5600
+F 0 "GND_125" H 7200 5600 20  0000 C CNN
+F 1 "+GND" H 7200 5530 30  0000 C CNN
+F 2 "" H 7200 5600 70  0000 C CNN
+F 3 "" H 7200 5600 70  0000 C CNN
+	1    7200 5600
 	1    0    0    -1  
 $EndComp
 $Comp
 L GND #PWR?58023F02
 U 1 1 58023F02
-P 9240 5060
-F 0 "GND_126" H 9240 5060 20  0000 C CNN
-F 1 "+GND" H 9240 4990 30  0000 C CNN
-F 2 "" H 9240 5060 70  0000 C CNN
-F 3 "" H 9240 5060 70  0000 C CNN
-	1    9240 5060
+P 8400 5600
+F 0 "GND_126" H 8400 5600 20  0000 C CNN
+F 1 "+GND" H 8400 5530 30  0000 C CNN
+F 2 "" H 8400 5600 70  0000 C CNN
+F 3 "" H 8400 5600 70  0000 C CNN
+	1    8400 5600
 	1    0    0    -1  
 $EndComp
 $Comp
 L GND #PWR?58023F01
 U 1 1 58023F01
-P 10120 5060
-F 0 "GND_127" H 10120 5060 20  0000 C CNN
-F 1 "+GND" H 10120 4990 30  0000 C CNN
-F 2 "" H 10120 5060 70  0000 C CNN
-F 3 "" H 10120 5060 70  0000 C CNN
-	1    10120 5060
+P 9200 5600
+F 0 "GND_127" H 9200 5600 20  0000 C CNN
+F 1 "+GND" H 9200 5530 30  0000 C CNN
+F 2 "" H 9200 5600 70  0000 C CNN
+F 3 "" H 9200 5600 70  0000 C CNN
+	1    9200 5600
 	1    0    0    -1  
 $EndComp
 $Comp
 L GND #PWR?58023F00
 U 1 1 58023F00
-P 7920 7150
-F 0 "GND_128" H 7920 7150 20  0000 C CNN
-F 1 "+GND" H 7920 7080 30  0000 C CNN
-F 2 "" H 7920 7150 70  0000 C CNN
-F 3 "" H 7920 7150 70  0000 C CNN
-	1    7920 7150
+P 7200 7500
+F 0 "GND_128" H 7200 7500 20  0000 C CNN
+F 1 "+GND" H 7200 7430 30  0000 C CNN
+F 2 "" H 7200 7500 70  0000 C CNN
+F 3 "" H 7200 7500 70  0000 C CNN
+	1    7200 7500
 	1    0    0    -1  
 $EndComp
 $Comp
 L GND #PWR?58023EFF
 U 1 1 58023EFF
-P 9240 7150
-F 0 "GND_129" H 9240 7150 20  0000 C CNN
-F 1 "+GND" H 9240 7080 30  0000 C CNN
-F 2 "" H 9240 7150 70  0000 C CNN
-F 3 "" H 9240 7150 70  0000 C CNN
-	1    9240 7150
+P 8400 7500
+F 0 "GND_129" H 8400 7500 20  0000 C CNN
+F 1 "+GND" H 8400 7430 30  0000 C CNN
+F 2 "" H 8400 7500 70  0000 C CNN
+F 3 "" H 8400 7500 70  0000 C CNN
+	1    8400 7500
 	1    0    0    -1  
 $EndComp
 $Comp
 L GND #PWR?58023EFE
 U 1 1 58023EFE
-P 10120 7150
-F 0 "GND_130" H 10120 7150 20  0000 C CNN
-F 1 "+GND" H 10120 7080 30  0000 C CNN
-F 2 "" H 10120 7150 70  0000 C CNN
-F 3 "" H 10120 7150 70  0000 C CNN
-	1    10120 7150
+P 9200 7500
+F 0 "GND_130" H 9200 7500 20  0000 C CNN
+F 1 "+GND" H 9200 7430 30  0000 C CNN
+F 2 "" H 9200 7500 70  0000 C CNN
+F 3 "" H 9200 7500 70  0000 C CNN
+	1    9200 7500
 	1    0    0    -1  
 $EndComp
 $Comp
 L VCCO_3V3 #PWR?58023EFD
 U 1 1 58023EFD
-P 2310 3520
-F 0 "VCCO_3V3_35" H 2310 3520 20  0000 C CNN
-F 1 "+VCCO_3V3" H 2310 3450 30  0000 C CNN
-F 2 "" H 2310 3520 70  0000 C CNN
-F 3 "" H 2310 3520 70  0000 C CNN
-	1    2310 3520
+P 2100 4200
+F 0 "VCCO_3V3_35" H 2100 4200 20  0000 C CNN
+F 1 "+VCCO_3V3" H 2100 4130 30  0000 C CNN
+F 2 "" H 2100 4200 70  0000 C CNN
+F 3 "" H 2100 4200 70  0000 C CNN
+	1    2100 4200
 	1    0    0    -1  
 $EndComp
 $Comp
 L VCCO_3V3 #PWR?58023EFC
 U 1 1 58023EFC
-P 7920 3630
-F 0 "VCCO_3V3_36" H 7920 3630 20  0000 C CNN
-F 1 "+VCCO_3V3" H 7920 3560 30  0000 C CNN
-F 2 "" H 7920 3630 70  0000 C CNN
-F 3 "" H 7920 3630 70  0000 C CNN
-	1    7920 3630
+P 7200 4300
+F 0 "VCCO_3V3_36" H 7200 4300 20  0000 C CNN
+F 1 "+VCCO_3V3" H 7200 4230 30  0000 C CNN
+F 2 "" H 7200 4300 70  0000 C CNN
+F 3 "" H 7200 4300 70  0000 C CNN
+	1    7200 4300
 	1    0    0    -1  
 $EndComp
 $Comp
 L VCCO_3V3 #PWR?58023EFB
 U 1 1 58023EFB
-P 7920 5720
-F 0 "VCCO_3V3_37" H 7920 5720 20  0000 C CNN
-F 1 "+VCCO_3V3" H 7920 5650 30  0000 C CNN
-F 2 "" H 7920 5720 70  0000 C CNN
-F 3 "" H 7920 5720 70  0000 C CNN
-	1    7920 5720
+P 7200 6200
+F 0 "VCCO_3V3_37" H 7200 6200 20  0000 C CNN
+F 1 "+VCCO_3V3" H 7200 6130 30  0000 C CNN
+F 2 "" H 7200 6200 70  0000 C CNN
+F 3 "" H 7200 6200 70  0000 C CNN
+	1    7200 6200
 	1    0    0    -1  
 $EndComp
 $Comp
 L GND #PWR?58023EFA
 U 1 1 58023EFA
-P 10230 8910
-F 0 "GND_131" H 10230 8910 20  0000 C CNN
-F 1 "+GND" H 10230 8840 30  0000 C CNN
-F 2 "" H 10230 8910 70  0000 C CNN
-F 3 "" H 10230 8910 70  0000 C CNN
-	1    10230 8910
+P 9300 9100
+F 0 "GND_131" H 9300 9100 20  0000 C CNN
+F 1 "+GND" H 9300 9030 30  0000 C CNN
+F 2 "" H 9300 9100 70  0000 C CNN
+F 3 "" H 9300 9100 70  0000 C CNN
+	1    9300 9100
 	1    0    0    -1  
 $EndComp
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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+	8500 6600 8400 6600
 Wire Wire Line
-	3410 7810 2090 7810
-Text Label 2310 7810 0 70 ~
+	3100 8100 1900 8100
+Text Label 2100 8100 0 70 ~
 AVR_GPIO_FPGA_0
 Wire Wire Line
-	3410 7920 2090 7920
-Text Label 2310 7920 0 70 ~
+	3100 8200 1900 8200
+Text Label 2100 8200 0 70 ~
 AVR_GPIO_FPGA_1
 Wire Wire Line
-	3410 4620 2090 4620
-Text Label 2310 4620 0 70 ~
+	3100 5200 1900 5200
+Text Label 2100 5200 0 70 ~
 FPGA_IRQ_N_0
 Wire Wire Line
-	3410 4730 2090 4730
-Text Label 2310 4730 0 70 ~
+	3100 5300 1900 5300
+Text Label 2100 5300 0 70 ~
 FPGA_IRQ_N_1
 Wire Wire Line
-	3410 4840 2090 4840
-Text Label 2310 4840 0 70 ~
+	3100 5400 1900 5400
+Text Label 2100 5400 0 70 ~
 FPGA_IRQ_N_2
 Wire Wire Line
-	3410 4950 2090 4950
-Text Label 2310 4950 0 70 ~
+	3100 5500 1900 5500
+Text Label 2100 5500 0 70 ~
 FPGA_IRQ_N_3
 Wire Wire Line
-	3410 5060 2090 5060
-Text Label 2310 5280 0 70 ~
+	3100 5600 1900 5600
+Text Label 2100 5800 0 70 ~
 FPGA_GPIO_A_0
 Wire Wire Line
-	9350 4400 8360 4400
-Text Label 8360 4400 0 70 ~
+	8500 5000 7600 5000
+Text Label 7600 5000 0 70 ~
 FPGA_GPIO_A_0
 Wire Wire Line
-	3410 5170 2090 5170
-Text Label 2310 5170 0 70 ~
+	3100 5700 1900 5700
+Text Label 2100 5700 0 70 ~
 FPGA_GPIO_A_1
 Wire Wire Line
-	11000 4400 10010 4400
-Text Label 10230 4400 0 70 ~
+	10000 5000 9100 5000
+Text Label 9300 5000 0 70 ~
 FPGA_GPIO_A_1
 Wire Wire Line
-	3410 5280 2090 5280
-Text Label 2310 6490 0 70 ~
+	3100 5800 1900 5800
+Text Label 2100 6900 0 70 ~
 FPGA_GPIO_A_2
 Wire Wire Line
-	9350 4510 8360 4510
-Text Label 8360 4510 0 70 ~
+	8500 5100 7600 5100
+Text Label 7600 5100 0 70 ~
 FPGA_GPIO_A_2
-Text Label 2310 6600 0 70 ~
+Text Label 2100 7000 0 70 ~
 FPGA_GPIO_A_3
 Wire Wire Line
-	11000 4510 10010 4510
-Text Label 10230 4510 0 70 ~
+	10000 5100 9100 5100
+Text Label 9300 5100 0 70 ~
 FPGA_GPIO_A_3
-Text Label 2310 6050 0 70 ~
+Text Label 2100 6500 0 70 ~
 FPGA_GPIO_A_4
 Wire Wire Line
-	9350 4730 8360 4730
-Text Label 8360 4730 0 70 ~
+	8500 5300 7600 5300
+Text Label 7600 5300 0 70 ~
 FPGA_GPIO_A_4
 Wire Wire Line
-	3410 5610 2090 5610
-Text Label 2310 6160 0 70 ~
+	3100 6100 1900 6100
+Text Label 2100 6600 0 70 ~
 FPGA_GPIO_A_5
 Wire Wire Line
-	11000 4730 10010 4730
-Text Label 10230 4730 0 70 ~
+	10000 5300 9100 5300
+Text Label 9300 5300 0 70 ~
 FPGA_GPIO_A_5
-Text Label 2321 6270 0 70 ~
+Text Label 2110 6700 0 70 ~
 FPGA_GPIO_A_6
 Wire Wire Line
-	9350 4840 8360 4840
-Text Label 8360 4840 0 70 ~
+	8500 5400 7600 5400
+Text Label 7600 5400 0 70 ~
 FPGA_GPIO_A_6
 Wire Wire Line
-	3410 5830 2090 5830
-Text Label 2310 5830 0 70 ~
+	3100 6300 1900 6300
+Text Label 2100 6300 0 70 ~
 FPGA_GPIO_A_7
 Wire Wire Line
-	11000 4840 10010 4840
-Text Label 10230 4840 0 70 ~
+	10000 5400 9100 5400
+Text Label 9300 5400 0 70 ~
 FPGA_GPIO_A_7
 Wire Wire Line
-	3410 5940 2090 5940
-Text Label 2321 6380 0 70 ~
+	3100 6400 1900 6400
+Text Label 2110 6800 0 70 ~
 FPGA_GPIO_B_0
 Wire Wire Line
-	9350 6490 8360 6490
-Text Label 8360 6490 0 70 ~
+	8500 6900 7600 6900
+Text Label 7600 6900 0 70 ~
 FPGA_GPIO_B_0
 Wire Wire Line
-	3410 6050 2090 6050
-Text Label 2310 5060 0 70 ~
+	3100 6500 1900 6500
+Text Label 2100 5600 0 70 ~
 FPGA_GPIO_B_1
 Wire Wire Line
-	11000 6490 10010 6490
-Text Label 10230 6490 0 70 ~
+	10000 6900 9100 6900
+Text Label 9300 6900 0 70 ~
 FPGA_GPIO_B_1
 Wire Wire Line
-	3410 6160 2090 6160
-Text Label 2310 5940 0 70 ~
+	3100 6600 1900 6600
+Text Label 2100 6400 0 70 ~
 FPGA_GPIO_B_2
 Wire Wire Line
-	9350 6600 8360 6600
-Text Label 8360 6600 0 70 ~
+	8500 7000 7600 7000
+Text Label 7600 7000 0 70 ~
 FPGA_GPIO_B_2
 Wire Wire Line
-	3410 6270 2090 6270
-Text Label 2321 5610 0 70 ~
+	3100 6700 1900 6700
+Text Label 2110 6100 0 70 ~
 FPGA_GPIO_B_3
 Wire Wire Line
-	11000 6600 10010 6600
-Text Label 10230 6600 0 70 ~
+	10000 7000 9100 7000
+Text Label 9300 7000 0 70 ~
 FPGA_GPIO_B_3
 Wire Wire Line
-	3410 6380 2090 6380
-Text Label 2310 7150 0 70 ~
+	3100 6800 1900 6800
+Text Label 2100 7500 0 70 ~
 FPGA_GPIO_B_4
 Wire Wire Line
-	9350 6820 8360 6820
-Text Label 8360 6820 0 70 ~
+	8500 7200 7600 7200
+Text Label 7600 7200 0 70 ~
 FPGA_GPIO_B_4
 Wire Wire Line
-	3410 6490 2090 6490
-Text Label 2310 9020 0 70 ~
+	3100 6900 1900 6900
+Text Label 2100 9200 0 70 ~
 FPGA_GPIO_B_5
 Wire Wire Line
-	11000 6820 10010 6820
-Text Label 10230 6820 0 70 ~
+	10000 7200 9100 7200
+Text Label 9300 7200 0 70 ~
 FPGA_GPIO_B_5
 Wire Wire Line
-	3410 6600 2090 6600
-Text Label 2310 8580 0 70 ~
+	3100 7000 1900 7000
+Text Label 2100 8800 0 70 ~
 FPGA_GPIO_B_6
 Wire Wire Line
-	9350 6930 8360 6930
-Text Label 8360 6930 0 70 ~
+	8500 7300 7600 7300
+Text Label 7600 7300 0 70 ~
 FPGA_GPIO_B_6
-Text Label 2310 8690 0 70 ~
+Text Label 2100 8900 0 70 ~
 FPGA_GPIO_B_7
 Wire Wire Line
-	11000 6930 10010 6930
-Text Label 10230 6930 0 70 ~
+	10000 7300 9100 7300
+Text Label 9300 7300 0 70 ~
 FPGA_GPIO_B_7
 Wire Wire Line
-	3410 6930 2090 6930
-Text Label 2310 6930 0 70 ~
+	3100 7300 1900 7300
+Text Label 2100 7300 0 70 ~
 FPGA_GCLK
 Wire Wire Line
-	8679 8470 8030 8470
-Text Label 8030 8470 0 70 ~
+	7890 8700 7300 8700
+Text Label 7300 8700 0 70 ~
 FPGA_GPIO_LED_2
 Wire Wire Line
-	9020 8360 8030 8360
-Text Label 8030 8360 0 70 ~
+	8200 8600 7300 8600
+Text Label 7300 8600 0 70 ~
 FPGA_GPIO_LED_3
 Wire Wire Line
-	8679 8690 8030 8690
-Text Label 8030 8690 0 70 ~
+	7890 8900 7300 8900
+Text Label 7300 8900 0 70 ~
 FPGA_GPIO_LED_0
 Wire Wire Line
-	9020 8580 8030 8580
-Text Label 8030 8580 0 70 ~
+	8200 8800 7300 8800
+Text Label 7300 8800 0 70 ~
 FPGA_GPIO_LED_1
 Wire Wire Line
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+	8900 8900 8290 8900
 Wire Wire Line
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+	8700 8800 8600 8800
 Wire Wire Line
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 Wire Wire Line
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+	8700 8600 8600 8600
 Wire Wire Line
-	3410 6820 2090 6820
-Text Label 2310 6820 0 70 ~
+	3100 7200 1900 7200
+Text Label 2100 7200 0 70 ~
 FPGA_ENTROPY_DISABLE
 Wire Wire Line
-	3410 8030 2090 8030
-Text Label 2310 8030 0 70 ~
+	3100 8300 1900 8300
+Text Label 2100 8300 0 70 ~
 AVR_GPIO_FPGA_2
 Wire Wire Line
-	3410 8140 2090 8140
-Text Label 2310 8140 0 70 ~
+	3100 8400 1900 8400
+Text Label 2100 8400 0 70 ~
 AVR_GPIO_FPGA_3
-Text Label 9130 8261 0 70 ~
+Text Label 8300 8510 0 70 ~
 330
-Text Label 8745 8261 0 70 ~
+Text Label 7950 8510 0 70 ~
 330
-Text Label 9581 8250 0 70 ~
+Text Label 8710 8500 0 70 ~
 330
-Text Label 8789 8976 0 70 ~
+Text Label 7990 9160 0 70 ~
 330
 Wire Wire Line
-	3410 7150 2090 7150
+	3100 7500 1900 7500
 Wire Wire Line
-	3410 8580 2090 8580
+	3100 8800 1900 8800
 Wire Wire Line
-	3410 8690 2090 8690
+	3100 8900 1900 8900
 Wire Wire Line
-	3410 9020 2090 9020
+	3100 9200 1900 9200
 $Comp
 L MA08-2 IC276
 U 1 1 58023EF9
-	1    9680 4400
+	1    8800 5000
 	-1   0    0    1
 $EndComp
 $Comp
 L R-EU_R0402 R99
 U 1 1 58023EF8
-F 0 "R99" H 9339 8162 60  0000 R TNN
-F 1 "" H 9339 8261 60  0000 R TNN
-F 2 "" H 9339 8261 60  0000 C CNN
-F 3 "" H 9339 8261 60  0000 C CNN
-	1    9240 8360
+F 0 "R99" H 8490 8420 60  0000 R TNN
+F 1 "" H 8490 8510 60  0000 R TNN
+F 2 "" H 8490 8510 60  0000 C CNN
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\ No newline at end of file