loads of updates

1 files changed, 113 insertions, 24 deletions

diff --git a/fix-pcb.py b/fix-pcb.py
index d04d7a5..a5887ec 100755
--- a/fix-pcb.py
+++ b/fix-pcb.py
@@ -15,7 +15,7 @@ def remove_tracks(board, layer):
     in KiCAD.
     """
     for this in [x for x in board.GetTracks() if x.GetLayerName() == layer]:
-        print('Removing track {}'.format(this))
+        print('Removing track {} on Layer 4'.format(this))
         board.Delete(this)
 
 #def set_tracks_width(board, layer, width):
@@ -46,32 +46,88 @@ def hide_layers_except(board, layers):
     board.SetVisibleLayers(visible_set)
 
 
-def layer_zone_fixes(board, layer, gnd_clearance=0.25):
+def layer_zone_fixes(board, layer, clearance=0.15, min_width=0.05, thermal=0.5,
+                     gnd_clearance=0.25, gnd_min_width=0.05, gnd_thermal=0.5, gnd_priority=50):
     for i in range(board.GetAreaCount()):
         area = board.GetArea(i)
         if area.GetLayerName() != layer:
             continue
         print('Area {} {}'.format(area, area.GetNetname()))
-        # This makes sharp edges matching Altium Designer
-        # 0.0255 is the minimum KiCad wants in order to allow changes to the zone inside KiCad
-        area.SetMinThickness(int(2 * 0.0255 * 1000000))
-        # 0.25 works better for the distance between zones in the bottom half of layer 4,
-        # but does not allow copper between the vias under the FPGA
-        #area.SetZoneClearance(int(0.25 * 1000000))
-        #
-        # Values below 0.15 or somewhere there does not seem to make a difference at all
-        area.SetZoneClearance(int(0.15 * 1000000))
         if area.GetNetname() == 'GND':
-            area.SetPriority(50)
+            area.SetZoneClearance(int(gnd_clearance * 1000000))
+            area.SetMinThickness(int(gnd_min_width * 1000000))
             # 0.25 clearance on the 'background' GND zone keeps the distance to the island
             # zones in the bottom half of layer 4, matching the clearance between the areas
             # but creating a bit more clearance around vias in KiCAD plot than in Altium
-            area.SetZoneClearance(int(gnd_clearance * 1000000))
-            area.SetThermalReliefCopperBridge(int(0.5 * 1000000))
-            #help(area)
+            area.SetThermalReliefCopperBridge(int(gnd_thermal * 1000000))
+            area.SetPriority(gnd_priority)
+        else:
+            # 0.25 works better for the distance between zones in the bottom half of layer 4,
+            # but does not allow copper between the vias under the FPGA
+            #
+            # Values below 0.15 or somewhere there does not seem to make a difference at all
+            area.SetZoneClearance(int(clearance * 1000000))
+            # This makes sharp edges matching Altium Designer
+            # 0.0255 is the minimum KiCad wants in order to allow changes to the zone inside KiCad
+            area.SetMinThickness(int(min_width * 1000000))
+            area.SetThermalReliefCopperBridge(int(thermal * 1000000))
+
+
+def fix_layer_GTL(board):
+    """
+    There are four segments of Net1 to the far left, just below the four vias for
+    VCCO_3V3. Altium covers this up in the GND polygon, much the same way as on the
+    bottom layer. Wonder if Net1 is some kind of alias for GND in Altium?
+
+    Anyway, remove the four segments.
+
+    Compare with
+
+      $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-F.Cu.gbr' /path/to/CrypTech.GTL
+    """
+    for this in [x for x in board.GetTracks() if x.GetLayerName() == 'F.Cu']:
+        pos = tuple(this.GetStart())
+        if this.GetNetname() == 'Net1' and pos[0] > 6000000 and pos[0] < 12000000:
+            print('Removing Net1 segment on top layer: {}'.format(pos))
+            board.Delete(this)
+    layer_zone_fixes(board, 'F.Cu', gnd_clearance=0.15)
+
+
+def fix_layer_GP1(board):
+    """
+    Layer 1 has a GND polygon that needs a little less clearance in order to fill in between
+    the vias of the FPGA.
+
+    Compare with
+
+      $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In1.Cu.gbr' /path/to/CrypTech.GP1
+    """
+    layer_zone_fixes(board, 'In1.Cu', gnd_clearance=0.15)
+
+
+def fix_layer_G1(board):
+    """
+    Layer 2 has a GND fill with unusual fill properties. We could easilly change parameters
+    on this zone to reach many more places on the board. There are even a few isolated islands
+    that must be connected to GND on other layers, that would easilly get connected with the
+    normal zone parameters.
 
+    Compare with
+
+      $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In1.Cu.gbr' /path/to/CrypTech.GP1
+    """
+    layer_zone_fixes(board, 'In2.Cu', gnd_clearance=0.5, gnd_min_width=0.7, gnd_thermal=0.71)
+
+
+def fix_layer_GP2(board):
+    """
+    Compare with
 
-def fix_layer_4(board):
+      $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In3.Cu.gbr' /path/to/CrypTech.GP2
+    """
+    layer_zone_fixes(board, 'In3.Cu')
+
+def fix_layer_GP3(board):
     """
 
     Layer 4 is a layer with large polygons (GND and Power). In Altium, this was made
@@ -85,12 +141,19 @@ def fix_layer_4(board):
       $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In4.Cu.gbr' /path/to/CrypTech.GP3
     """
     remove_tracks(board, 'In4.Cu')
-    #set_tracks_width(board, 'In4.Cu', int(0.15 * 1000000))
-    #move_tracks(board, 'In4.Cu', 'Eco2.User')
     layer_zone_fixes(board, 'In4.Cu', gnd_clearance=0.25)
 
 
-def fix_layer_6(board):
+def fix_layer_G2(board):
+    """
+    Compare with
+
+      $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In5.Cu.gbr' /path/to/CrypTech.G2
+    """
+    layer_zone_fixes(board, 'In5.Cu', gnd_clearance=0.5, gnd_min_width=0.7, gnd_thermal=0.71)
+
+
+def fix_layer_GP4(board):
     """
     Layer 6 has a GND polygon that needs a little less clearance in order to fill in between
     the vias of the FPGA.
@@ -102,7 +165,7 @@ def fix_layer_6(board):
     layer_zone_fixes(board, 'In6.Cu', gnd_clearance=0.15)
 
 
-def fix_layer_bottom(board):
+def fix_layer_GBL(board):
     """
     There is one small segment that ends up on Net 1 instead of GND (Net 7) for some reason:
 
@@ -131,15 +194,41 @@ def fix_layer_bottom(board):
     layer_zone_fixes(board, 'B.Cu', gnd_clearance=0.15)
 
 
+#def change_via_drill_size(board, from_, to_):
+#    for this in board.GetTracks():
+#        if type(this) is pcbnew.VIA:
+#            if this.GetDrill() == from_:
+#                this.SetDrill(pcbnew.FromMM(to_))
+#            else:
+#                help(this)
+#                print('Not changing drill {} to {}'.format(this.GetDrill(), to_))
+
+def change_netclass_drill_size(board, from_, to_):
+    help(board.GetDesignSettings())
+    names = board.GetAllNetClasses()
+    for name, net in names.iterator():
+        if net.GetViaDrill() == int(from_ * 1000000):
+            print("Netclass {} has drill size {}, changing to {}".format(name, net.GetViaDrill(), int(to_ * 1000000)))
+            net.SetViaDrill(int(to_ * 1000000))
+
+
 def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alpha.kicad_pcb'):
     board = pcbnew.LoadBoard(in_fn)
     pcbnew.SaveBoard(in_fn + '.before-fix-layer-4', board)
 
-    fix_layer_4(board)
-    fix_layer_6(board)
-    fix_layer_bottom(board)
+    fix_layer_GTL(board)
+    fix_layer_GP1(board)
+    fix_layer_G1(board)
+    fix_layer_GP2(board)
+    fix_layer_GP3(board)
+    fix_layer_G2(board)
+    fix_layer_GP4(board)
+    fix_layer_GBL(board)
+
+    #change_via_drill_size(board, 0.635, 0.250)
+    change_netclass_drill_size(board, 0.635, 0.250)
 
-    hide_layers_except(board, ['B.Cu'])
+    hide_layers_except(board, ['In5.Cu'])
 
     # Only show Through Via while working on Layer 4
     board.SetVisibleElements(0x7FFC0009)