fixed some throughholes to be on layers *.Cu instead of just front and back

2 files changed, 110 insertions, 99 deletions

diff --git a/convert.sh b/convert.sh
index 556d02a..c0ce866 100755
--- a/convert.sh
+++ b/convert.sh
@@ -33,13 +33,24 @@ mkdir "${kicaddir}"
 cp ${altiumdir}/*.{sch,lib} "${kicaddir}"/
 rm ${kicaddir}/rev02*-cache.lib
 cp ${altiumdir}/CrypTech-PcbDoc.kicad_pcb "${kicaddir}/Cryptech Alpha.kicad_pcb"
+cp -rp ${altiumdir}/wrlshp ${kicaddir}/wrlshp
 cp "Cryptech Alpha.pro.template" "${kicaddir}/Cryptech Alpha.pro"
 cp "Cryptech Alpha.sch.template" "${kicaddir}/Cryptech Alpha.sch"
 
+# Fix wrl paths
+wrlpath=$(readlink -f ${altiumdir}/wrlshp)
+sed -i -e "s!${wrlpath}!wrlshp!g" ${kicaddir}/rev02_*
+
+cd ${kicaddir}
+
 # Change to more sensible filenames
-cd "${kicaddir}"
 rename 's/-SchDoc//' rev02_*
-sed -i -e 's/-SchDoc//g' *
+sed -i -e 's/-SchDoc//g' *.{sch,lib}
+
+# Change some PCB parameters
+sed -i -e 's/trace_min 0.254/trace_min 0.15/g' "Cryptech Alpha.kicad_pcb"
+# show ratsnest
+sed -i -e 's/visible_elements 7FFFF77F/visible_elements 7FFFFF7F/g' "Cryptech Alpha.kicad_pcb"
 
 # Sheet number fixups. This hides all the hierarchical sub-sheets from the project view.
 num_sheets=$(ls Cryptech\ Alpha.sch rev02*sch | wc -l)
diff --git a/rev03-KiCad/Cryptech Alpha.kicad_pcb b/rev03-KiCad/Cryptech Alpha.kicad_pcb
index 3a346b2..f9c9232 100644
--- a/rev03-KiCad/Cryptech Alpha.kicad_pcb
+++ b/rev03-KiCad/Cryptech Alpha.kicad_pcb
@@ -2,7 +2,7 @@
 
   (general
     (links 1412)
-    (no_connects 729)
+    (no_connects 695)
     (area -32.294113 -104.25 148.466654 54.64848)
     (thickness 1.6)
     (drawings 7054)
@@ -47,7 +47,7 @@
     (trace_clearance 0.15)
     (zone_clearance 0.0144)
     (zone_45_only no)
-    (trace_min 0.254)
+    (trace_min 0.15)
     (segment_width 0.2)
     (edge_width 0.1)
     (via_size 0.889)
@@ -68,7 +68,7 @@
     (pad_drill 0.6)
     (pad_to_mask_clearance 0)
     (aux_axis_origin 0 0)
-    (visible_elements 7FFFF77F)
+    (visible_elements 7FFFFF7F)
     (pcbplotparams
       (layerselection 0x00030_80000001)
       (usegerberextensions false)
@@ -748,25 +748,25 @@
     (fp_text value "Connector; Header; 10 Position" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 18 AVR_GPIO_1))
-    (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 24 AVR_GPIO_7))
-    (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 23 AVR_GPIO_6))
-    (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 22 AVR_GPIO_5))
-    (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 21 AVR_GPIO_4))
-    (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 20 AVR_GPIO_3))
-    (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 19 AVR_GPIO_2))
-    (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 17 AVR_GPIO_0))
-    (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
   )
 
@@ -780,9 +780,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at 0 1.27 90) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at 0 1.27 90) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 2 thru_hole circle (at 0 -1.27 90) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 0 -1.27 90) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 211 MKM_AVR_MISO))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/3416A7AC-A52A.wrl
       (at (xyz 0 0 0))
@@ -5316,8 +5316,8 @@
     (fp_text value USB-MINIB (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers F&B.Cu *.Paste *.Mask))
-    (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers F&B.Cu *.Paste *.Mask))
+    (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask))
+    (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask))
     (pad GND smd rect (at 4.36 2) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (pad GND smd rect (at 4.36 -3.5052) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
@@ -5352,8 +5352,8 @@
     (fp_text value USB-MINIB (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers F&B.Cu *.Paste *.Mask))
-    (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers F&B.Cu *.Paste *.Mask))
+    (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask))
+    (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask))
     (pad GND smd rect (at -4.34 -3.5052) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
@@ -5831,16 +5831,16 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask))
-    (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask))
+    (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 277 NRST))
-    (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 294 SWDIO))
-    (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 293 SWDCLK))
-    (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/670BFB14-85C2.wrl
       (at (xyz 0 0 0))
@@ -5859,17 +5859,17 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 205 FT_VREGIN))
-    (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 298 USB_P))
-    (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 297 USB_N))
-    (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 194 FT_RXD1))
-    (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 196 FT_TXD1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
       (at (xyz 0 0 0))
@@ -5888,17 +5888,17 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 183 FT_MGMT_TXD1))
-    (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 181 FT_MGMT_RXD1))
-    (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 295 USB_MGMT_N))
-    (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 296 USB_MGMT_P))
-    (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 188 FT_MGMT_VREGIN))
-    (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
       (at (xyz 0 0 0))
@@ -5917,11 +5917,11 @@
     (fp_text value "Wurth DC Power Jack, 2.1mm, PCB Mount" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 3 thru_hole oval (at 4.8 -10.6 90) (size 4.500001 2.000001) (drill 0.800001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole oval (at 4.8 -10.6 90) (size 4.500001 2.000001) (drill 0.800001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 2 thru_hole oval (at 0 -7.8 90) (size 2.000001 4.500001) (drill 0.800001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole oval (at 0 -7.8 90) (size 2.000001 4.500001) (drill 0.800001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 1 thru_hole oval (at 0 -13.6 90) (size 2.000001 4.500001) (drill 0.800001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole oval (at 0 -13.6 90) (size 2.000001 4.500001) (drill 0.800001) (layers *.Cu *.Paste *.Mask)
       (net 283 PWR_18V))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/51D2E761-0F4D.wrl
       (at (xyz 0 0 0))
@@ -5940,9 +5940,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 244 NetJP2_2))
-    (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 4 15V_LDO_ENABLE))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/3416A7AC-A52A.wrl
       (at (xyz 0 0 0))
@@ -5961,17 +5961,17 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 211 MKM_AVR_MISO))
-    (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 3 3V3_BATT))
-    (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 213 MKM_AVR_SCK))
-    (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 212 MKM_AVR_MOSI))
-    (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 38 AVR_RESET))
-    (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
       (at (xyz 0 0 0))
@@ -5990,11 +5990,11 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 3 3V3_BATT))
-    (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/836C6F64-A2E5.wrl
       (at (xyz 0 0 0))
@@ -6013,17 +6013,17 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 121 FPGA_CFG_CTRL_ARM_ENA))
-    (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 291 SPI_A_TRISTATE))
-    (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 122 FPGA_CFG_CTRL_FPGA_DIS))
-    (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 292 SPI_B_TRISTATE))
-    (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 173 FPGA_PROM_W_N))
-    (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
       (at (xyz 0 0 0))
@@ -8445,21 +8445,21 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 160 FPGA_JTAG_TCK))
-    (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 163 FPGA_JTAG_TMS))
-    (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 161 FPGA_JTAG_TDI))
-    (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 162 FPGA_JTAG_TDO))
-    (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A962434E-CFE5.wrl
       (at (xyz 0 0 0))
@@ -8478,37 +8478,37 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 140 FPGA_GPIO_A_7))
-    (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 139 FPGA_GPIO_A_6))
-    (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 138 FPGA_GPIO_A_5))
-    (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 137 FPGA_GPIO_A_4))
-    (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 136 FPGA_GPIO_A_3))
-    (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 135 FPGA_GPIO_A_2))
-    (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 134 FPGA_GPIO_A_1))
-    (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 133 FPGA_GPIO_A_0))
-    (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B280C847-2543.wrl
       (at (xyz 0 0 0))
@@ -8527,37 +8527,37 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 141 FPGA_GPIO_B_0))
-    (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 142 FPGA_GPIO_B_1))
-    (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 143 FPGA_GPIO_B_2))
-    (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 144 FPGA_GPIO_B_3))
-    (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 145 FPGA_GPIO_B_4))
-    (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 146 FPGA_GPIO_B_5))
-    (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 147 FPGA_GPIO_B_6))
-    (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers F&B.Cu *.Paste *.Mask)
+    (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
       (net 148 FPGA_GPIO_B_7))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B280C847-2543.wrl
       (at (xyz 0 0 0))