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author | Fredrik Thulin <fredrik@thulin.net> | 2017-09-26 10:02:18 +0200 |
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committer | Fredrik Thulin <fredrik@thulin.net> | 2017-09-26 10:02:18 +0200 |
commit | 247c039850d23399c53d0af445b93f55a15fcf7b (patch) | |
tree | 38221d309c022e479ae6c2c1ffd0ded6041e53ff | |
parent | 19a36f254fe1007827d6e83a90250d625bb7ae2e (diff) |
update
-rw-r--r-- | README.md | 27 |
1 files changed, 27 insertions, 0 deletions
@@ -9,3 +9,30 @@ project files from and the altium2kicad project from https://github.com/thesourcerer8/altium2kicad + + +Current status +-------------- +The schematics are successfully converted. + +All the copper layers convert reasonably well. The challenges are mostly +around filled polygons on the various layers. A python script (fix-pcb.py) +modifies parameters to get a fairly close result. + +Importing WRL files (3D models) required some hacking of the altium2kicad +tool that I haven't been able to work on upstreaming yet. + +Another hack that has not been upstreamed is loading more of the source +files, IIRC to get all component footprints properly converted. + + +Issues +------ +Two layers (Altium Gerber files CrypTech.G1 and CrypTech.G2) have fills +that I have not been able to reproduce. I targeted not missing any copper, +accepting that the KiCAD gerber fills reach more places, so add some copper +on those layers. + +Drill hole sizes have not been checked. KiCAD seems to add ~0.85 mil more +clearance around vias. This needs to be double checked but I'm hoping that +we can just tolerate that. |