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authorFredrik Thulin <fredrik@thulin.net>2017-09-26 12:15:14 +0200
committerFredrik Thulin <fredrik@thulin.net>2017-09-26 12:15:14 +0200
commit3af4c15e929f046f955b3222c5f5f1a5ec987ad5 (patch)
tree21da0b7a0c1746aef5c8992b801caddcacd8d196
parenta3c49f090d31398e5004c502071c061137874a4e (diff)
a comment about a difference on layer In2
-rwxr-xr-xfix-pcb.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/fix-pcb.py b/fix-pcb.py
index fb75dc9..939191f 100755
--- a/fix-pcb.py
+++ b/fix-pcb.py
@@ -133,6 +133,9 @@ def fix_layer_In2_aka_G1(board):
that must be connected to GND on other layers, that would easilly get connected with the
normal zone parameters.
+ The current result is missing the connection of the three GND pins on SV1 (FPGA JTAG), but
+ these three pins are connected on layer In5 aka G2.
+
Compare with
$ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In2.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.G1