diff options
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/coretest_hashes.v | 273 | ||||
| -rw-r--r-- | src/rtl/i2c_core.v | 581 | ||||
| -rw-r--r-- | src/rtl/novena_fpga.v | 147 | ||||
| -rw-r--r-- | src/rtl/sha1.v | 421 | ||||
| -rw-r--r-- | src/rtl/sha256.v | 433 | ||||
| -rw-r--r-- | src/rtl/sha512.v | 497 |
6 files changed, 2352 insertions, 0 deletions
diff --git a/src/rtl/coretest_hashes.v b/src/rtl/coretest_hashes.v new file mode 100644 index 0000000..567d4f7 --- /dev/null +++ b/src/rtl/coretest_hashes.v @@ -0,0 +1,273 @@ +//====================================================================== +// +// coretest_hashes.v +// ----------------- +// Top level wrapper that creates the Cryptech coretest system. +// The wrapper contains instances of the external interface and the +// cores to be tested, as well as address and data muxes. +// +// +// Authors: Joachim Strombergson, Paul Selkirk +// Copyright (c) 2014, SUNET +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module coretest_hashes( + input wire clk, + input wire reset_n, + + // External interface. + input wire SCL, + input wire SDA, + output wire SDA_pd, + + output wire [7 : 0] debug + ); + + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter I2C_SHA1_ADDR = 7'h1e; + parameter I2C_SHA256_ADDR = 7'h1f; + parameter I2C_SHA512_224_ADDR = 7'h20; + parameter I2C_SHA512_256_ADDR = 7'h21; + parameter I2C_SHA384_ADDR = 7'h22; + parameter I2C_SHA512_ADDR = 7'h23; + + parameter MODE_SHA_512_224 = 2'h0; + parameter MODE_SHA_512_256 = 2'h1; + parameter MODE_SHA_384 = 2'h2; + parameter MODE_SHA_512 = 2'h3; + + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + // i2c connections + wire i2c_rxd_syn; + wire [7 : 0] i2c_rxd_data; + reg i2c_rxd_ack; + reg i2c_txd_syn; + reg [7 : 0] i2c_txd_data; + wire i2c_txd_ack; + wire [6 : 0] i2c_device_addr; + + // sha1 connections. + reg sha1_rxd_syn; + reg [7 : 0] sha1_rxd_data; + wire sha1_rxd_ack; + wire sha1_txd_syn; + wire [7 : 0] sha1_txd_data; + reg sha1_txd_ack; + + // sha256 connections. + reg sha256_rxd_syn; + reg [7 : 0] sha256_rxd_data; + wire sha256_rxd_ack; + wire sha256_txd_syn; + wire [7 : 0] sha256_txd_data; + reg sha256_txd_ack; + + // sha512 connections. + reg [1 : 0] sha512_mode; + reg sha512_rxd_syn; + reg [7 : 0] sha512_rxd_data; + wire sha512_rxd_ack; + wire sha512_txd_syn; + wire [7 : 0] sha512_txd_data; + reg sha512_txd_ack; + + + //---------------------------------------------------------------- + // Core instantiations. + //---------------------------------------------------------------- + i2c_core i2c( + .clk(clk), + .reset(!reset_n), // active high + + .SCL(SCL), + .SDA(SDA), + .SDA_pd(SDA_pd), + .i2c_addr_low(I2C_SHA1_ADDR), + .i2c_addr_high(I2C_SHA512_ADDR), + .i2c_device_addr(i2c_device_addr), + + .rxd_syn(i2c_rxd_syn), + .rxd_data(i2c_rxd_data), + .rxd_ack(i2c_rxd_ack), + + .txd_syn(i2c_txd_syn), + .txd_data(i2c_txd_data), + .txd_ack(i2c_txd_ack) + ); + + sha1 sha1( + .clk(clk), + .reset_n(reset_n), + + .rx_syn(sha1_rxd_syn), + .rx_data(sha1_rxd_data), + .rx_ack(sha1_rxd_ack), + + .tx_syn(sha1_txd_syn), + .tx_data(sha1_txd_data), + .tx_ack(sha1_txd_ack) + ); + + sha256 sha256( + .clk(clk), + .reset_n(reset_n), + + .rx_syn(sha256_rxd_syn), + .rx_data(sha256_rxd_data), + .rx_ack(sha256_rxd_ack), + + .tx_syn(sha256_txd_syn), + .tx_data(sha256_txd_data), + .tx_ack(sha256_txd_ack) + ); + + sha512 sha512( + .clk(clk), + .reset_n(reset_n), + + .mode(sha512_mode), + + .rx_syn(sha512_rxd_syn), + .rx_data(sha512_rxd_data), + .rx_ack(sha512_rxd_ack), + + .tx_syn(sha512_txd_syn), + .tx_data(sha512_txd_data), + .tx_ack(sha512_txd_ack) + ); + + //---------------------------------------------------------------- + // address_mux + // + // Combinational data mux that handles addressing between + // cores using the I2C device address. + //---------------------------------------------------------------- + always @* + begin : address_mux + // Default assignments. + i2c_rxd_ack = 0; + i2c_txd_syn = 0; + i2c_txd_data = 8'h00; + + sha1_rxd_syn = 0; + sha1_rxd_data = 8'h00; + sha1_txd_ack = 0; + + sha256_rxd_syn = 0; + sha256_rxd_data = 8'h00; + sha256_txd_ack = 0; + + sha512_rxd_syn = 0; + sha512_rxd_data = 8'h00; + sha512_txd_ack = 0; + sha512_mode = 2'b00; + + case (i2c_device_addr) + I2C_SHA1_ADDR: + begin + sha1_rxd_syn = i2c_rxd_syn; + sha1_rxd_data = i2c_rxd_data; + i2c_rxd_ack = sha1_rxd_ack; + i2c_txd_syn = sha1_txd_syn; + i2c_txd_data = sha1_txd_data; + sha1_txd_ack = i2c_txd_ack; + end + + I2C_SHA256_ADDR: + begin + sha256_rxd_syn = i2c_rxd_syn; + sha256_rxd_data = i2c_rxd_data; + i2c_rxd_ack = sha256_rxd_ack; + i2c_txd_syn = sha256_txd_syn; + i2c_txd_data = sha256_txd_data; + sha256_txd_ack = i2c_txd_ack; + end + + I2C_SHA512_224_ADDR: + begin + sha512_rxd_syn = i2c_rxd_syn; + sha512_rxd_data = i2c_rxd_data; + i2c_rxd_ack = sha512_rxd_ack; + i2c_txd_syn = sha512_txd_syn; + i2c_txd_data = sha512_txd_data; + sha512_txd_ack = i2c_txd_ack; + sha512_mode = MODE_SHA_512_224; + end + + I2C_SHA512_256_ADDR: + begin + sha512_rxd_syn = i2c_rxd_syn; + sha512_rxd_data = i2c_rxd_data; + i2c_rxd_ack = sha512_rxd_ack; + i2c_txd_syn = sha512_txd_syn; + i2c_txd_data = sha512_txd_data; + sha512_txd_ack = i2c_txd_ack; + sha512_mode = MODE_SHA_512_256; + end + + I2C_SHA384_ADDR: + begin + sha512_rxd_syn = i2c_rxd_syn; + sha512_rxd_data = i2c_rxd_data; + i2c_rxd_ack = sha512_rxd_ack; + i2c_txd_syn = sha512_txd_syn; + i2c_txd_data = sha512_txd_data; + sha512_txd_ack = i2c_txd_ack; + sha512_mode = MODE_SHA_384; + end + + I2C_SHA512_ADDR: + begin + sha512_rxd_syn = i2c_rxd_syn; + sha512_rxd_data = i2c_rxd_data; + i2c_rxd_ack = sha512_rxd_ack; + i2c_txd_syn = sha512_txd_syn; + i2c_txd_data = sha512_txd_data; + sha512_txd_ack = i2c_txd_ack; + sha512_mode = MODE_SHA_512; + end + + default: + begin + end + endcase // case (i2c_device_addr) + end // address_mux + +endmodule // coretest_hashes + +//====================================================================== +// EOF coretest_hashes.v +//====================================================================== diff --git a/src/rtl/i2c_core.v b/src/rtl/i2c_core.v new file mode 100644 index 0000000..cbf76c6 --- /dev/null +++ b/src/rtl/i2c_core.v @@ -0,0 +1,581 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2011, Andrew "bunnie" Huang +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY +// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT +// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +////////////////////////////////////////////////////////////////////////////// +// A simple I2C slave implementation. Oversampled for robustness. +// The slave is extended into the snoop & surpress version for the DDC bus; +// this is just a starting point for basic testing and also simple comms +// with the CPU. +// +// i2c slave module requires the top level module to implement the IOBs +// This is just to keep the tri-state easy to implemen across the hierarchy +// +// The code required on the top level is: +// IOBUF #(.DRIVE(12), .SLEW("SLOW")) IOBUF_sda (.IO(SDA), .I(1'b0), .T(!SDA_pd)); +// +/////////// +`timescale 1 ns / 1 ps + +module i2c_core ( + input wire clk, + input wire reset, + + // External data interface + input wire SCL, + input wire SDA, + output reg SDA_pd, + input wire [6:0] i2c_addr_low, + input wire [6:0] i2c_addr_high, + output wire [6:0] i2c_device_addr, + + // Internal receive interface. + output wire rxd_syn, + output [7 : 0] rxd_data, + input wire rxd_ack, + + // Internal transmit interface. + input wire txd_syn, + input wire [7 : 0] txd_data, + output wire txd_ack + ); + + /////// I2C physical layer components + /// SDA is stable when SCL is high. + /// If SDA moves while SCL is high, this is considered a start or stop condition. + /// + /// Otherwise, SDA can move around when SCL is low (this is where we suppress bits or + /// overdrive as needed). SDA is a wired-AND bus, so you only "drive" zero. + /// + /// In an oversampled implementation, a rising and falling edge de-glitcher is needed + /// for SCL and SDA. + /// + + // rise fall time cycles computation: + // At 400kHz operation, 2.5us is a cycle. "chatter" from transition should be about + // 5% of total cycle time max (just rule of thumb), so 0.125us should be the equiv + // number of cycles. + // For the demo board, a 25 MHz clock is provided, and 0.125us ~ 4 cycles + // At 100kHz operation, 10us is a cycle, so 0.5us ~ 12 cycles + parameter TRF_CYCLES = 5'd4; // number of cycles for rise/fall time + + //////////////// + ///// protocol-level state machine + //////////////// + parameter I2C_START = 16'b1 << 0; // should only pass through this state for one cycle + parameter I2C_RESTART = 16'b1 << 1; + parameter I2C_DADDR = 16'b1 << 2; + parameter I2C_ACK_DADDR = 16'b1 << 3; + parameter I2C_WR_DATA = 16'b1 << 4; + parameter I2C_ACK_WR = 16'b1 << 5; + parameter I2C_END_WR = 16'b1 << 6; + parameter I2C_RD_DATA = 16'b1 << 7; + parameter I2C_ACK_RD = 16'b1 << 8; + parameter I2C_END_RD = 16'b1 << 9; + parameter I2C_END_RD2 = 16'b1 << 10; + parameter I2C_WAITSTOP = 16'b1 << 11; + parameter I2C_RXD_SYN = 16'b1 << 12; + parameter I2C_RXD_ACK = 16'b1 << 13; + parameter I2C_TXD_SYN = 16'b1 << 14; + parameter I2C_TXD_ACK = 16'b1 << 15; + + parameter I2C_nSTATES = 16; + + reg [(I2C_nSTATES-1):0] I2C_cstate = {{(I2C_nSTATES-1){1'b0}}, 1'b1}; //current and next states + reg [(I2C_nSTATES-1):0] I2C_nstate; + +//`define SIMULATION +`ifdef SIMULATION + // synthesis translate_off + reg [8*20:1] I2C_state_ascii = "I2C_START "; + always @(I2C_cstate) begin + if (I2C_cstate == I2C_START) I2C_state_ascii <= "I2C_START "; + else if (I2C_cstate == I2C_RESTART) I2C_state_ascii <= "I2C_RESTART "; + else if (I2C_cstate == I2C_DADDR) I2C_state_ascii <= "I2C_DADDR "; + else if (I2C_cstate == I2C_ACK_DADDR) I2C_state_ascii <= "I2C_ACK_DADDR "; + else if (I2C_cstate == I2C_WR_DATA) I2C_state_ascii <= "I2C_WR_DATA "; + else if (I2C_cstate == I2C_ACK_WR) I2C_state_ascii <= "I2C_ACK_WR "; + else if (I2C_cstate == I2C_END_WR) I2C_state_ascii <= "I2C_END_WR "; + else if (I2C_cstate == I2C_RD_DATA) I2C_state_ascii <= "I2C_RD_DATA "; + else if (I2C_cstate == I2C_ACK_RD) I2C_state_ascii <= "I2C_ACK_RD "; + else if (I2C_cstate == I2C_END_RD) I2C_state_ascii <= "I2C_END_RD "; + else if (I2C_cstate == I2C_END_RD2) I2C_state_ascii <= "I2C_END_RD2 "; + else if (I2C_cstate == I2C_WAITSTOP) I2C_state_ascii <= "I2C_WAITSTOP "; + else if (I2C_cstate == I2C_RXD_SYN) I2C_state_ascii <= "I2C_RXD_SYN "; + else if (I2C_cstate == I2C_RXD_ACK) I2C_state_ascii <= "I2C_RXD_ACK "; + else if (I2C_cstate == I2C_TXD_SYN) I2C_state_ascii <= "I2C_TXD_SYN "; + else if (I2C_cstate == I2C_TXD_ACK) I2C_state_ascii <= "I2C_TXD_ACK "; + else I2C_state_ascii <= "WTF "; + end + // synthesis translate_on +`endif + + reg [3:0] I2C_bitcnt; + reg [7:0] I2C_daddr; + reg [7:0] I2C_wdata; + reg [7:0] I2C_rdata; + + reg rxd_syn_reg; + reg txd_ack_reg; + + assign rxd_data = I2C_wdata; + assign rxd_syn = rxd_syn_reg; + assign txd_ack = txd_ack_reg; + + assign i2c_device_addr = I2C_daddr[7:1]; + + + ////////// code begins here + always @ (posedge clk) begin + if (reset || ((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_RISE))) // stop condition always resets + I2C_cstate <= I2C_START; + else + I2C_cstate <= I2C_nstate; + end + + always @ (*) begin + case (I2C_cstate) //synthesis parallel_case full_case + I2C_START: begin // wait for the start condition + I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_DADDR : I2C_START; + end + I2C_RESTART: begin // repeated start moves immediately to DADDR + I2C_nstate = I2C_DADDR; + end + + // device address branch + I2C_DADDR: begin // 8 bits to get the address + I2C_nstate = ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_DADDR : I2C_DADDR; + end + I2C_ACK_DADDR: begin // depending upon W/R bit state, go to one of two branches + I2C_nstate = (SCL_cstate == SCL_FALL) ? + ((I2C_daddr[7:1] >= i2c_addr_low) && + (I2C_daddr[7:1] <= i2c_addr_high)) ? + (I2C_daddr[0] == 1'b0 ? I2C_WR_DATA : I2C_TXD_SYN) : + I2C_WAITSTOP : // !I2C_daddr match + I2C_ACK_DADDR; // !SCL_FALL + end + + // write branch + I2C_WR_DATA: begin // 8 bits to get the write data + I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_RESTART : // repeated start + ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_RXD_SYN : I2C_WR_DATA; + end + I2C_RXD_SYN: begin // put data on the coretest bus + I2C_nstate = I2C_RXD_ACK; + end + I2C_RXD_ACK: begin // wait for coretest ack + I2C_nstate = rxd_ack ? I2C_ACK_WR : I2C_RXD_ACK; + end + I2C_ACK_WR: begin // trigger the ack response (pull SDA low until next falling edge) + // and stay in this state until the next falling edge of SCL + I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_END_WR : I2C_ACK_WR; + end + I2C_END_WR: begin // one-cycle state to update address+1, reset SDA pulldown + I2C_nstate = I2C_WR_DATA; // SCL is now low + end + + // read branch + I2C_TXD_SYN: begin // get data from the coretest bus + // if data isn't available (txd_syn isn't asserted) by the time we + // get to this state, it probably never will be, so skip it + I2C_nstate = txd_syn ? I2C_TXD_ACK : I2C_RD_DATA; + end + I2C_TXD_ACK: begin // send coretest ack + // hold ack high until syn is lowered + I2C_nstate = txd_syn ? I2C_TXD_ACK : I2C_RD_DATA; + end + I2C_RD_DATA: begin // 8 bits to get the read data + I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_RESTART : // repeated start + ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_RD : I2C_RD_DATA; + end + I2C_ACK_RD: begin // wait for an (n)ack response + // need to sample (n)ack on a rising edge + I2C_nstate = (SCL_cstate == SCL_RISE) ? I2C_END_RD : I2C_ACK_RD; + end + I2C_END_RD: begin // if nack, just go to start state (don't explicitly check stop event) + // single cycle state for adr+1 update + I2C_nstate = (SDA_cstate == SDA_LOW) ? I2C_END_RD2 : I2C_START; + end + I2C_END_RD2: begin // before entering I2C_RD_DATA, we need to have seen a falling edge. + I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_RD_DATA : I2C_END_RD2; + end + + // we're not the addressed device, so we just idle until we see a stop + I2C_WAITSTOP: begin + I2C_nstate = (((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_RISE))) ? // stop + I2C_START : + (((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_FALL))) ? // or start + I2C_RESTART : + I2C_WAITSTOP; + end + endcase // case (cstate) + end + + always @ (posedge clk) begin + if( reset ) begin + I2C_bitcnt <= 4'b0; + I2C_daddr <= 8'b0; + I2C_wdata <= 8'b0; + SDA_pd <= 1'b0; + I2C_rdata <= 8'b0; + end else begin + case (I2C_cstate) // synthesis parallel_case full_case + I2C_START: begin // everything in reset + I2C_bitcnt <= 4'b0; + I2C_daddr <= 8'b0; + I2C_wdata <= 8'b0; + I2C_rdata <= 8'b0; + SDA_pd <= 1'b0; + end + + I2C_RESTART: begin + I2C_bitcnt <= 4'b0; + I2C_daddr <= 8'b0; + I2C_wdata <= 8'b0; + I2C_rdata <= 8'b0; + SDA_pd <= 1'b0; + end + + // get my i2c device address (am I being talked to?) + I2C_DADDR: begin // shift in the address on rising edges of clock + if( SCL_cstate == SCL_RISE ) begin + I2C_bitcnt <= I2C_bitcnt + 4'b1; + I2C_daddr[7] <= I2C_daddr[6]; + I2C_daddr[6] <= I2C_daddr[5]; + I2C_daddr[5] <= I2C_daddr[4]; + I2C_daddr[4] <= I2C_daddr[3]; + I2C_daddr[3] <= I2C_daddr[2]; + I2C_daddr[2] <= I2C_daddr[1]; + I2C_daddr[1] <= I2C_daddr[0]; + I2C_daddr[0] <= (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0; + end else begin // we're oversampled so we need a hold-state gutter + I2C_bitcnt <= I2C_bitcnt; + I2C_daddr <= I2C_daddr; + end // else: !if( SCL_cstate == SCL_RISE ) + SDA_pd <= 1'b0; + I2C_wdata <= 8'b0; + I2C_rdata <= 8'b0; + end // case: I2C_DADDR + I2C_ACK_DADDR: begin + SDA_pd <= 1'b1; // active pull down ACK + I2C_daddr <= I2C_daddr; + I2C_bitcnt <= 4'b0; + I2C_wdata <= 8'b0; + I2C_rdata <= 8'b0; + end + + // write branch + I2C_WR_DATA: begin // shift in data on rising edges of clock + if( SCL_cstate == SCL_RISE ) begin + I2C_bitcnt <= I2C_bitcnt + 4'b1; + I2C_wdata[7] <= I2C_wdata[6]; + I2C_wdata[6] <= I2C_wdata[5]; + I2C_wdata[5] <= I2C_wdata[4]; + I2C_wdata[4] <= I2C_wdata[3]; + I2C_wdata[3] <= I2C_wdata[2]; + I2C_wdata[2] <= I2C_wdata[1]; + I2C_wdata[1] <= I2C_wdata[0]; + I2C_wdata[0] <= (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0; + end else begin + I2C_bitcnt <= I2C_bitcnt; // hold state gutter + I2C_wdata <= I2C_wdata; + end // else: !if( SCL_cstate == SCL_RISE ) + SDA_pd <= 1'b0; + I2C_daddr <= I2C_daddr; + I2C_rdata <= I2C_rdata; + end // case: I2C_WR_DATA + I2C_RXD_SYN: begin // put data on the coretest bus and raise syn + rxd_syn_reg <= 1; + end + I2C_RXD_ACK: begin // wait for coretest ack + if (rxd_ack) + rxd_syn_reg <= 0; + end + I2C_ACK_WR: begin + SDA_pd <= 1'b1; // active pull down ACK + I2C_daddr <= I2C_daddr; + I2C_bitcnt <= 4'b0; + I2C_wdata <= I2C_wdata; + I2C_rdata <= I2C_rdata; + end + I2C_END_WR: begin + SDA_pd <= 1'b0; // let SDA rise (host may look for this to know ack is done + I2C_bitcnt <= 4'b0; + I2C_wdata <= 8'b0; + I2C_rdata <= I2C_rdata; + I2C_daddr <= I2C_daddr; + end + + // read branch + I2C_TXD_SYN: begin // get data from the coretest bus + if (txd_syn) begin + I2C_rdata <= txd_data; + txd_ack_reg <= 1; + end + end + I2C_TXD_ACK: begin // send coretest ack + if (!txd_syn) + txd_ack_reg <= 0; + end + I2C_RD_DATA: begin // shift out data on falling edges of clock + SDA_pd <= I2C_rdata[7] ? 1'b0 : 1'b1; + if( SCL_cstate == SCL_RISE ) begin + I2C_bitcnt <= I2C_bitcnt + 4'b1; + end else begin + I2C_bitcnt <= I2C_bitcnt; // hold state gutter + end + + if( SCL_cstate == SCL_FALL ) begin + I2C_rdata[7] <= I2C_rdata[6]; + I2C_rdata[6] <= I2C_rdata[5]; + I2C_rdata[5] <= I2C_rdata[4]; + I2C_rdata[4] <= I2C_rdata[3]; + I2C_rdata[3] <= I2C_rdata[2]; + I2C_rdata[2] <= I2C_rdata[1]; + I2C_rdata[1] <= I2C_rdata[0]; + I2C_rdata[0] <= 1'b0; + end else begin + I2C_rdata <= I2C_rdata; + end // else: !if( SCL_cstate == SCL_RISE ) + I2C_daddr <= I2C_daddr; + I2C_wdata <= I2C_wdata; + end // case: I2C_RD_DATA + I2C_ACK_RD: begin + SDA_pd <= 1'b0; // in ack state don't pull down, we are listening to host + I2C_daddr <= I2C_daddr; + I2C_bitcnt <= 4'b0; + I2C_rdata <= I2C_rdata; + I2C_wdata <= I2C_wdata; + end + I2C_END_RD: begin + SDA_pd <= 1'b0; // let SDA rise (host may look for this to know ack is done + I2C_daddr <= I2C_daddr; + I2C_bitcnt <= 4'b0; + I2C_rdata <= I2C_rdata; + I2C_wdata <= I2C_wdata; + end + I2C_END_RD2: begin + SDA_pd <= 1'b0; + I2C_daddr <= 8'b0; + I2C_bitcnt <= 4'b0; + I2C_rdata <= I2C_rdata; + I2C_wdata <= I2C_wdata; + end + + I2C_WAITSTOP: begin + SDA_pd <= 1'b0; + I2C_daddr <= 8'b0; + I2C_bitcnt <= 4'b0; + I2C_rdata <= I2C_rdata; + I2C_wdata <= I2C_wdata; + end + endcase // case (cstate) + end // else: !if( reset ) + end // always @ (posedge clk or posedge reset) + + + /////////////////////////////////////////////////////////////// + /////////// low level state machines ////////////////////////// + /////////////////////////////////////////////////////////////// + + + //////////////// + ///// SCL low-level sampling state machine + //////////////// + parameter SCL_HIGH = 4'b1 << 0; // should only pass through this state for one cycle + parameter SCL_FALL = 4'b1 << 1; + parameter SCL_LOW = 4'b1 << 2; + parameter SCL_RISE = 4'b1 << 3; + parameter SCL_nSTATES = 4; + + reg [(SCL_nSTATES-1):0] SCL_cstate = {{(SCL_nSTATES-1){1'b0}}, 1'b1}; //current and next states + reg [(SCL_nSTATES-1):0] SCL_nstate; + +//`define SIMULATION +`ifdef SIMULATION + // synthesis translate_off + reg [8*20:1] SCL_state_ascii = "SCL_HIGH "; + + always @(SCL_cstate) begin + if (SCL_cstate == SCL_HIGH) SCL_state_ascii <= "SCL_HIGH "; + else if (SCL_cstate == SCL_FALL) SCL_state_ascii <= "SCL_FALL "; + else if (SCL_cstate == SCL_LOW ) SCL_state_ascii <= "SCL_LOW "; + else if (SCL_cstate == SCL_RISE) SCL_state_ascii <= "SCL_RISE "; + else SCL_state_ascii <= "WTF "; + end + // synthesis translate_on +`endif + + reg [4:0] SCL_rfcnt; + reg SCL_s, SCL_sync; + reg SDA_s, SDA_sync; + + always @ (posedge clk) begin + if (reset) + SCL_cstate <= SCL_HIGH; // always start here even if it's wrong -- easier to test + else + SCL_cstate <= SCL_nstate; + end + + always @ (*) begin + case (SCL_cstate) //synthesis parallel_case full_case + SCL_HIGH: begin + SCL_nstate = ((SCL_rfcnt > TRF_CYCLES) && (SCL_sync == 1'b0)) ? SCL_FALL : SCL_HIGH; + end + SCL_FALL: begin + SCL_nstate = SCL_LOW; + end + SCL_LOW: begin + SCL_nstate = ((SCL_rfcnt > TRF_CYCLES) && (SCL_sync == 1'b1)) ? SCL_RISE : SCL_LOW; + end + SCL_RISE: begin + SCL_nstate = SCL_HIGH; + end + endcase // case (cstate) + end // always @ (*) + + always @ (posedge clk) begin + if( reset ) begin + SCL_rfcnt <= 5'b0; + end else begin + case (SCL_cstate) // synthesis parallel_case full_case + SCL_HIGH: begin + if( SCL_sync == 1'b1 ) begin + SCL_rfcnt <= 5'b0; + end else begin + SCL_rfcnt <= SCL_rfcnt + 5'b1; + end + end + SCL_FALL: begin + SCL_rfcnt <= 5'b0; + end + SCL_LOW: begin + if( SCL_sync == 1'b0 ) begin + SCL_rfcnt <= 5'b0; + end else begin + SCL_rfcnt <= SCL_rfcnt + 5'b1; + end + end + SCL_RISE: begin + SCL_rfcnt <= 5'b0; + end + endcase // case (cstate) + end // else: !if( reset ) + end // always @ (posedge clk or posedge reset) + + + //////////////// + ///// SDA low-level sampling state machine + //////////////// + parameter SDA_HIGH = 4'b1 << 0; // should only pass through this state for one cycle + parameter SDA_FALL = 4'b1 << 1; + parameter SDA_LOW = 4'b1 << 2; + parameter SDA_RISE = 4'b1 << 3; + parameter SDA_nSTATES = 4; + + reg [(SDA_nSTATES-1):0] SDA_cstate = {{(SDA_nSTATES-1){1'b0}}, 1'b1}; //current and next states + reg [(SDA_nSTATES-1):0] SDA_nstate; + +//`define SIMULATION +`ifdef SIMULATION + // synthesis translate_off + reg [8*20:1] SDA_state_ascii = "SDA_HIGH "; + + always @(SDA_cstate) begin + if (SDA_cstate == SDA_HIGH) SDA_state_ascii <= "SDA_HIGH "; + else if (SDA_cstate == SDA_FALL) SDA_state_ascii <= "SDA_FALL "; + else if (SDA_cstate == SDA_LOW ) SDA_state_ascii <= "SDA_LOW "; + else if (SDA_cstate == SDA_RISE) SDA_state_ascii <= "SDA_RISE "; + else SDA_state_ascii <= "WTF "; + end + // synthesis translate_on +`endif + + reg [4:0] SDA_rfcnt; + + always @ (posedge clk) begin + if (reset) + SDA_cstate <= SDA_HIGH; // always start here even if it's wrong -- easier to test + else + SDA_cstate <= SDA_nstate; + end + + always @ (*) begin + case (SDA_cstate) //synthesis parallel_case full_case + SDA_HIGH: begin + SDA_nstate = ((SDA_rfcnt > TRF_CYCLES) && (SDA_sync == 1'b0)) ? SDA_FALL : SDA_HIGH; + end + SDA_FALL: begin + SDA_nstate = SDA_LOW; + end + SDA_LOW: begin + SDA_nstate = ((SDA_rfcnt > TRF_CYCLES) && (SDA_sync == 1'b1)) ? SDA_RISE : SDA_LOW; + end + SDA_RISE: begin + SDA_nstate = SDA_HIGH; + end + endcase // case (cstate) + end // always @ (*) + + always @ (posedge clk) begin + if( reset ) begin + SDA_rfcnt <= 5'b0; + end else begin + case (SDA_cstate) // synthesis parallel_case full_case + SDA_HIGH: begin + if( SDA_sync == 1'b1 ) begin + SDA_rfcnt <= 5'b0; + end else begin + SDA_rfcnt <= SDA_rfcnt + 5'b1; + end + end + SDA_FALL: begin + SDA_rfcnt <= 5'b0; + end + SDA_LOW: begin + if( SDA_sync == 1'b0 ) begin + SDA_rfcnt <= 5'b0; + end else begin + SDA_rfcnt <= SDA_rfcnt + 5'b1; + end + end + SDA_RISE: begin + SDA_rfcnt <= 5'b0; + end + endcase // case (cstate) + end // else: !if( reset ) + end // always @ (posedge clk or posedge reset) + + + + ///////////////////// + /////// synchronizers + ///////////////////// + always @ (posedge clk) begin + SCL_s <= SCL; + SCL_sync <= SCL_s; + SDA_s <= SDA; + SDA_sync <= SDA_s; + end // always @ (posedge clk or posedge reset) + +endmodule // i2c_slave diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v new file mode 100644 index 0000000..fd0f667 --- /dev/null +++ b/src/rtl/novena_fpga.v @@ -0,0 +1,147 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013, Andrew "bunnie" Huang +// +// See the NOTICE file distributed with this work for additional +// information regarding copyright ownership. The copyright holder +// licenses this file to you under the Apache License, Version 2.0 +// (the "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// code distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +////////////////////////////////////////////////////////////////////////////// + +/// note: must set "-g UnusedPin:Pullnone" to avoid conflicts with unused pins + +`timescale 1ns / 1ps + +module novena_fpga( + // CPU side mapping + input wire [15:0] EIM_DA, + output reg EIM_A16, // relay of the trigger output + output reg EIM_A17, // relay of the trigger data (read path) + + // connector side mapping + //input wire F_LVDS_N3, // output of trigger + //input wire F_DX2, // output of trigger + //output wire F_LVDS_N5, // trigger reset + output wire F_LVDS_P4, // trigger reset + //inout wire F_LVDS_P5, // trigger data (bidir) + //input wire F_DX18, // trigger data in from sticker (DUT->CPU) + output wire F_LVDS_P11, // trigger data out to sticker (CPU->DUT) + //output wire F_LVDS_N8, // trigger clock + //output wire F_DX14, // trigger clock + + output wire F_LVDS_N7, // drive TPI data line + output wire F_LVDS_P7, // drive TPI signal lines + + output wire F_DX15, // 1 = drive 5V, 0 = drive 3V to DUT + + output wire F_LVDS_CK1_N, + output wire F_LVDS_CK1_P, + output wire F_LVDS_N11, + + output wire F_LVDS_N0, + output wire F_LVDS_P0, + output wire F_DX1, + + output wire F_LVDS_N15, + output wire F_LVDS_P15, + output wire F_LVDS_NC, + + //input wire F_DX11, + //input wire F_DX3, + //input wire F_DX0, + + //input wire F_LVDS_CK0_P, + //input wire F_LVDS_CK0_N, + //input wire F_LVDS_P9, + + //input wire [1:0] EIM_CS, + //input wire EIM_LBA, + + input wire CLK2_N, + input wire CLK2_P, + output wire FPGA_LED2, + + input wire I2C3_SCL, + inout wire I2C3_SDA, + + input wire RESETBMCU, + output wire F_DX17, // dummy + output wire APOPTOSIS +); + wire clk; + + IBUFGDS clkibufgds( + .I(CLK2_P), + .IB(CLK2_N), + .O(clk) + ); + + assign FPGA_LED2 = 1'b1; + + assign APOPTOSIS = 1'b0; + assign F_DX15 = 1'b1; //+5V P_DUT + + // OE on bank to drive signals; signal not inverted in software + assign F_LVDS_P7 = !EIM_DA[3]; + // OE on bank to drive the data; signal not inverted in software + assign F_LVDS_N7 = !EIM_DA[4]; + assign F_LVDS_P4 = 1'b0; + assign F_LVDS_P11 = 1'b0; + assign F_LVDS_CK1_N = 1'b0; + assign F_LVDS_CK1_P = 1'b0; + assign F_LVDS_N11 = 1'b0; + assign F_LVDS_N0 = 1'b0; + assign F_LVDS_P0 = 1'b0; + assign F_DX1 = 1'b0; + assign F_LVDS_N15 = 1'b0; + assign F_LVDS_P15 = 1'b0; + assign F_LVDS_NC = 1'b0; + + // reduction and of EIM_DA, dummy-map to keep compiler quiet + assign F_DX17 = &EIM_DA | RESETBMCU; + + //////////////////////////////////// + ///// I2C register set + //////////////////////////////////// + wire SDA_pd; + wire SDA_int; + reg clk25; + + initial begin + clk25 <= 1'b0; + end + always @ (posedge clk) begin + clk25 <= ~clk25; + EIM_A16 <= 1'b0; + EIM_A17 <= 1'b0; + end + + IOBUF #( + .DRIVE(8), + .SLEW("SLOW") + ) IOBUF_sda ( + .IO(I2C3_SDA), + .I(1'b0), + .T(!SDA_pd), + .O(SDA_int) + ); + + coretest_hashes top( + .clk(clk25), + .reset_n(1'b1), + + .SCL(I2C3_SCL), + .SDA(SDA_int), + .SDA_pd(SDA_pd) + ); + +endmodule diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v new file mode 100644 index 0000000..2bf0de7 --- /dev/null +++ b/src/rtl/sha1.v @@ -0,0 +1,421 @@ +//====================================================================== +// +// sha1.v +// ------ +// Top level wrapper for the SHA-1 hash function providing +// a simple write()/read() interface with 8 bit data access. +// +// +// Authors: Joachim Strombergson, Paul Selkirk +// Copyright (c) 2014, SUNET +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module sha1( + // Clock and reset. + input wire clk, + input wire reset_n, + + // Interface to communication core + input wire rx_syn, + input wire [7 : 0] rx_data, + output wire rx_ack, + + output wire tx_syn, + output wire [7 : 0] tx_data, + input wire tx_ack + ); + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter RX_INIT = 0; + parameter RX_SYN = 1; + parameter RX_ACK = 2; + parameter RX_WAIT = 3; + + parameter TX_INIT = 0; + parameter TX_SYN = 1; + parameter TX_ACK = 2; + + parameter BLOCK_BITS = 512; + parameter BLOCK_BYTES = BLOCK_BITS / 8; + parameter DIGEST_BITS = 160; + parameter DIGEST_BYTES = DIGEST_BITS / 8; + + //---------------------------------------------------------------- + // Registers including update variables and write enable. + //---------------------------------------------------------------- + reg rx_ack_reg; + reg rx_ack_new; + reg rx_ack_we; + + reg [6 : 0] rx_ptr_reg; + reg [7 : 0] rx_ptr_new; + reg rx_ptr_we; + + reg [1 : 0] rx_ctrl_reg; + reg [1 : 0] rx_ctrl_new; + reg rx_ctrl_we; + + reg [7 : 0] block_reg [0 : BLOCK_BYTES - 1]; + reg [7 : 0] block_new; + reg block_we; + + reg init_reg; + reg init_new; + reg init_we; + + reg next_reg; + reg next_new; + reg next_we; + + reg initnext_reg; + reg initnext_new; + reg initnext_we; + + reg tx_syn_reg; + reg tx_syn_new; + reg tx_syn_we; + + reg [6 : 0] tx_ptr_reg; + reg [7 : 0] tx_ptr_new; + reg tx_ptr_we; + + reg [1 : 0] tx_ctrl_reg; + reg [1 : 0] tx_ctrl_new; + reg tx_ctrl_we; + + reg tx_active_reg; + reg tx_active_new; + reg tx_active_we; + + wire [7 : 0] digest_reg [0 : DIGEST_BYTES - 1]; + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + wire core_init; + wire core_next; + wire core_ready; + wire [BLOCK_BITS - 1 : 0] core_block; + wire [DIGEST_BITS - 1 : 0] core_digest; + wire core_digest_valid; + + //---------------------------------------------------------------- + // Concurrent connectivity for ports etc. + //---------------------------------------------------------------- + assign core_init = init_reg; + assign core_next = next_reg; + assign core_block = {block_reg[0], block_reg[1], block_reg[2], block_reg[3], + block_reg[4], block_reg[5], block_reg[6], block_reg[7], + block_reg[8], block_reg[9], block_reg[10], block_reg[11], + block_reg[12], block_reg[13], block_reg[14], block_reg[15], + block_reg[16], block_reg[17], block_reg[18], block_reg[19], + block_reg[20], block_reg[21], block_reg[22], block_reg[23], + block_reg[24], block_reg[25], block_reg[26], block_reg[27], + block_reg[28], block_reg[29], block_reg[30], block_reg[31], + block_reg[32], block_reg[33], block_reg[34], block_reg[35], + block_reg[36], block_reg[37], block_reg[38], block_reg[39], + block_reg[40], block_reg[41], block_reg[42], block_reg[43], + block_reg[44], block_reg[45], block_reg[46], block_reg[47], + block_reg[48], block_reg[49], block_reg[50], block_reg[51], + block_reg[52], block_reg[53], block_reg[54], block_reg[55], + block_reg[56], block_reg[57], block_reg[58], block_reg[59], + block_reg[60], block_reg[61], block_reg[62], block_reg[63]}; + + assign rx_ack = rx_ack_reg; + assign tx_syn = tx_syn_reg; + assign tx_data = digest_reg[tx_ptr_reg]; + + assign digest_reg[0] = core_digest[159 : 152]; + assign digest_reg[1] = core_digest[151 : 144]; + assign digest_reg[2] = core_digest[143 : 136]; + assign digest_reg[3] = core_digest[135 : 128]; + assign digest_reg[4] = core_digest[127 : 120]; + assign digest_reg[5] = core_digest[119 : 112]; + assign digest_reg[6] = core_digest[111 : 104]; + assign digest_reg[7] = core_digest[103 : 96]; + assign digest_reg[8] = core_digest[95 : 88]; + assign digest_reg[9] = core_digest[87 : 80]; + assign digest_reg[10] = core_digest[79 : 72]; + assign digest_reg[11] = core_digest[71 : 64]; + assign digest_reg[12] = core_digest[63 : 56]; + assign digest_reg[13] = core_digest[55 : 48]; + assign digest_reg[14] = core_digest[47 : 40]; + assign digest_reg[15] = core_digest[39 : 32]; + assign digest_reg[16] = core_digest[31 : 24]; + assign digest_reg[17] = core_digest[23 : 16]; + assign digest_reg[18] = core_digest[15 : 8]; + assign digest_reg[19] = core_digest[7 : 0]; + + //---------------------------------------------------------------- + // core instantiation. + //---------------------------------------------------------------- + sha1_core core( + .clk(clk), + .reset_n(reset_n), + + .init(core_init), + .next(core_next), + + .block(core_block), + + .ready(core_ready), + + .digest(core_digest), + .digest_valid(core_digest_valid) + ); + + //---------------------------------------------------------------- + // reg_update + // Update functionality for all registers in the core. + // All registers are positive edge triggered with synchronous + // active low reset. All registers have write enable. + //---------------------------------------------------------------- + + always @ (posedge clk) + begin: reg_update + if (!reset_n) + begin: reset_reg + reg[7:0] i; + for (i = 0; i < BLOCK_BYTES; i = i + 1) + block_reg[i] <= 0; + rx_ack_reg <= 0; + rx_ptr_reg <= 0; + rx_ctrl_reg <= RX_INIT; + tx_syn_reg <= 0; + tx_ptr_reg <= 0; + tx_ctrl_reg <= TX_INIT; + initnext_reg <= 0; + end + else + begin + if (rx_ack_we) + begin + rx_ack_reg <= rx_ack_new; + end + + if (rx_ptr_we) + begin + rx_ptr_reg <= rx_ptr_new[6:0]; + end + + if (rx_ctrl_we) + begin + rx_ctrl_reg <= rx_ctrl_new; + end + + if (block_we) + begin + block_reg[rx_ptr_reg] <= block_new; + end + + if (init_we) + begin + init_reg <= init_new; + end + + if (next_we) + begin + next_reg <= next_new; + end + + if (initnext_we) + begin + initnext_reg <= initnext_new; + end + + if (tx_syn_we) + begin + tx_syn_reg <= tx_syn_new; + end + + if (tx_ptr_we) + begin + tx_ptr_reg <= tx_ptr_new[6:0]; + end + + if (tx_ctrl_we) + begin + tx_ctrl_reg <= tx_ctrl_new; + end + + if (tx_active_we) + begin + tx_active_reg <= tx_active_new; + end + end + end // reg_update + + //---------------------------------------------------------------- + // rx_engine + //---------------------------------------------------------------- + always @* + begin: rx_engine + rx_ack_new = 0; + rx_ack_we = 0; + rx_ptr_new = 0; + rx_ptr_we = 0; + rx_ctrl_new = 0; + rx_ctrl_we = 0; + block_new = 0; + block_we = 0; + init_new = 0; + init_we = 0; + next_new = 0; + next_we = 0; + initnext_new = 0; + initnext_we = 0; + + if (tx_active_reg) + begin + initnext_we = 1; + end + + case (rx_ctrl_reg) + RX_INIT: + if (core_ready) + begin + rx_ctrl_new = RX_SYN; + rx_ctrl_we = 1; + end + RX_SYN: + if (rx_syn) + begin + rx_ack_new = 1; + rx_ack_we = 1; + block_new = rx_data; + block_we = 1; + rx_ctrl_new = RX_ACK; + rx_ctrl_we = 1; + end + RX_ACK: + if (!rx_syn) + begin + rx_ack_new = 0; + rx_ack_we = 1; + rx_ptr_new = rx_ptr_reg + 1; + rx_ptr_we = 1; + rx_ctrl_new = RX_SYN; + rx_ctrl_we = 1; + if (rx_ptr_new == BLOCK_BYTES) + begin + rx_ptr_new = 0; + rx_ctrl_new = RX_WAIT; + if (initnext_reg == 0) + begin + init_new = 1; + init_we = 1; + initnext_new = 1; + initnext_we = 1; + end + else + begin + next_new = 1; + next_we = 1; + end + end + end + RX_WAIT: + if (!core_ready) + begin + init_new = 0; + init_we = 1; + next_new = 0; + next_we = 1; + rx_ctrl_new = RX_INIT; + rx_ctrl_we = 1; + end + endcase // case (rx_ctrl_reg) + end // rx_engine + + //---------------------------------------------------------------- + // tx_engine + //---------------------------------------------------------------- + always @* + begin: tx_engine + tx_syn_new = 0; + tx_syn_we = 0; + tx_ptr_new = 0; + tx_ptr_we = 0; + tx_ctrl_new = 0; + tx_ctrl_we = 0; + tx_active_new = 0; + tx_active_we = 0; + + case (tx_ctrl_reg) + TX_INIT: + if (core_digest_valid) + begin + tx_ctrl_new = TX_SYN; + tx_ctrl_we = 1; + end + TX_SYN: + begin + tx_syn_new = 1; + tx_syn_we = 1; + tx_ctrl_new = TX_ACK; + tx_ctrl_we = 1; + end + TX_ACK: + if (!core_digest_valid) + begin + tx_syn_new = 0; + tx_syn_we = 1; + tx_ptr_new = 0; + tx_ptr_we = 1; + tx_ctrl_new = TX_INIT; + tx_ctrl_we = 1; + end + else if (tx_ack) + begin + tx_active_new = 1; + tx_active_we = 1; + tx_syn_new = 0; + tx_syn_we = 1; + tx_ptr_new = tx_ptr_reg + 1; + tx_ptr_we = 1; + tx_ctrl_new = TX_SYN; + tx_ctrl_we = 1; + if (tx_ptr_new == DIGEST_BYTES) + begin + tx_active_new = 0; + tx_ptr_new = 0; + tx_ctrl_new = TX_INIT; + end + end + endcase // case (tx_ctrl_reg) + end // tx_engine + +endmodule // sha1 + +//====================================================================== +// EOF sha1.v +//====================================================================== diff --git a/src/rtl/sha256.v b/src/rtl/sha256.v new file mode 100644 index 0000000..d28a914 --- /dev/null +++ b/src/rtl/sha256.v @@ -0,0 +1,433 @@ +//====================================================================== +// +// sha256.v +// -------- +// Top level wrapper for the SHA-256 hash function providing +// a simple write()/read() interface with 8 bit data access. +// +// +// Authors: Joachim Strombergson, Paul Selkirk +// Copyright (c) 2014, SUNET +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module sha256( + // Clock and reset. + input wire clk, + input wire reset_n, + + // Interface to communication core + input wire rx_syn, + input wire [7 : 0] rx_data, + output wire rx_ack, + + output wire tx_syn, + output wire [7 : 0] tx_data, + input wire tx_ack + ); + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter RX_INIT = 0; + parameter RX_SYN = 1; + parameter RX_ACK = 2; + parameter RX_WAIT = 3; + + parameter TX_INIT = 0; + parameter TX_SYN = 1; + parameter TX_ACK = 2; + + parameter BLOCK_BITS = 512; + parameter BLOCK_BYTES = BLOCK_BITS / 8; + parameter DIGEST_BITS = 256; + parameter DIGEST_BYTES = DIGEST_BITS / 8; + + //---------------------------------------------------------------- + // Registers including update variables and write enable. + //---------------------------------------------------------------- + reg rx_ack_reg; + reg rx_ack_new; + reg rx_ack_we; + + reg [6 : 0] rx_ptr_reg; + reg [7 : 0] rx_ptr_new; + reg rx_ptr_we; + + reg [1 : 0] rx_ctrl_reg; + reg [1 : 0] rx_ctrl_new; + reg rx_ctrl_we; + + reg [7 : 0] block_reg [0 : BLOCK_BYTES - 1]; + reg [7 : 0] block_new; + reg block_we; + + reg init_reg; + reg init_new; + reg init_we; + + reg next_reg; + reg next_new; + reg next_we; + + reg initnext_reg; + reg initnext_new; + reg initnext_we; + + reg tx_syn_reg; + reg tx_syn_new; + reg tx_syn_we; + + reg [6 : 0] tx_ptr_reg; + reg [7 : 0] tx_ptr_new; + reg tx_ptr_we; + + reg [1 : 0] tx_ctrl_reg; + reg [1 : 0] tx_ctrl_new; + reg tx_ctrl_we; + + reg tx_active_reg; + reg tx_active_new; + reg tx_active_we; + + wire [7 : 0] digest_reg [0 : DIGEST_BYTES - 1]; + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + wire core_init; + wire core_next; + wire core_ready; + wire [BLOCK_BITS - 1 : 0] core_block; + wire [DIGEST_BITS - 1 : 0] core_digest; + wire core_digest_valid; + + //---------------------------------------------------------------- + // Concurrent connectivity for ports etc. + //---------------------------------------------------------------- + assign core_init = init_reg; + assign core_next = next_reg; + assign core_block = {block_reg[0], block_reg[1], block_reg[2], block_reg[3], + block_reg[4], block_reg[5], block_reg[6], block_reg[7], + block_reg[8], block_reg[9], block_reg[10], block_reg[11], + block_reg[12], block_reg[13], block_reg[14], block_reg[15], + block_reg[16], block_reg[17], block_reg[18], block_reg[19], + block_reg[20], block_reg[21], block_reg[22], block_reg[23], + block_reg[24], block_reg[25], block_reg[26], block_reg[27], + block_reg[28], block_reg[29], block_reg[30], block_reg[31], + block_reg[32], block_reg[33], block_reg[34], block_reg[35], + block_reg[36], block_reg[37], block_reg[38], block_reg[39], + block_reg[40], block_reg[41], block_reg[42], block_reg[43], + block_reg[44], block_reg[45], block_reg[46], block_reg[47], + block_reg[48], block_reg[49], block_reg[50], block_reg[51], + block_reg[52], block_reg[53], block_reg[54], block_reg[55], + block_reg[56], block_reg[57], block_reg[58], block_reg[59], + block_reg[60], block_reg[61], block_reg[62], block_reg[63]}; + + assign rx_ack = rx_ack_reg; + assign tx_syn = tx_syn_reg; + assign tx_data = digest_reg[tx_ptr_reg]; + + assign digest_reg[0] = core_digest[255 : 248]; + assign digest_reg[1] = core_digest[247 : 240]; + assign digest_reg[2] = core_digest[239 : 232]; + assign digest_reg[3] = core_digest[231 : 224]; + assign digest_reg[4] = core_digest[223 : 216]; + assign digest_reg[5] = core_digest[215 : 208]; + assign digest_reg[6] = core_digest[207 : 200]; + assign digest_reg[7] = core_digest[199 : 192]; + assign digest_reg[8] = core_digest[191 : 184]; + assign digest_reg[9] = core_digest[183 : 176]; + assign digest_reg[10] = core_digest[175 : 168]; + assign digest_reg[11] = core_digest[167 : 160]; + assign digest_reg[12] = core_digest[159 : 152]; + assign digest_reg[13] = core_digest[151 : 144]; + assign digest_reg[14] = core_digest[143 : 136]; + assign digest_reg[15] = core_digest[135 : 128]; + assign digest_reg[16] = core_digest[127 : 120]; + assign digest_reg[17] = core_digest[119 : 112]; + assign digest_reg[18] = core_digest[111 : 104]; + assign digest_reg[19] = core_digest[103 : 96]; + assign digest_reg[20] = core_digest[95 : 88]; + assign digest_reg[21] = core_digest[87 : 80]; + assign digest_reg[22] = core_digest[79 : 72]; + assign digest_reg[23] = core_digest[71 : 64]; + assign digest_reg[24] = core_digest[63 : 56]; + assign digest_reg[25] = core_digest[55 : 48]; + assign digest_reg[26] = core_digest[47 : 40]; + assign digest_reg[27] = core_digest[39 : 32]; + assign digest_reg[28] = core_digest[31 : 24]; + assign digest_reg[29] = core_digest[23 : 16]; + assign digest_reg[30] = core_digest[15 : 8]; + assign digest_reg[31] = core_digest[7 : 0]; + + //---------------------------------------------------------------- + // core instantiation. + //---------------------------------------------------------------- + sha256_core core( + .clk(clk), + .reset_n(reset_n), + + .init(core_init), + .next(core_next), + + .block(core_block), + + .ready(core_ready), + + .digest(core_digest), + .digest_valid(core_digest_valid) + ); + + //---------------------------------------------------------------- + // reg_update + // Update functionality for all registers in the core. + // All registers are positive edge triggered with synchronous + // active low reset. All registers have write enable. + //---------------------------------------------------------------- + + always @ (posedge clk) + begin: reg_update + if (!reset_n) + begin: reset_reg + reg[7:0] i; + for (i = 0; i < BLOCK_BYTES; i = i + 1) + block_reg[i] <= 0; + rx_ack_reg <= 0; + rx_ptr_reg <= 0; + rx_ctrl_reg <= RX_INIT; + tx_syn_reg <= 0; + tx_ptr_reg <= 0; + tx_ctrl_reg <= TX_INIT; + initnext_reg <= 0; + end + else + begin + if (rx_ack_we) + begin + rx_ack_reg <= rx_ack_new; + end + + if (rx_ptr_we) + begin + rx_ptr_reg <= rx_ptr_new[6:0]; + end + + if (rx_ctrl_we) + begin + rx_ctrl_reg <= rx_ctrl_new; + end + + if (block_we) + begin + block_reg[rx_ptr_reg] <= block_new; + end + + if (init_we) + begin + init_reg <= init_new; + end + + if (next_we) + begin + next_reg <= next_new; + end + + if (initnext_we) + begin + initnext_reg <= initnext_new; + end + + if (tx_syn_we) + begin + tx_syn_reg <= tx_syn_new; + end + + if (tx_ptr_we) + begin + tx_ptr_reg <= tx_ptr_new[6:0]; + end + + if (tx_ctrl_we) + begin + tx_ctrl_reg <= tx_ctrl_new; + end + + if (tx_active_we) + begin + tx_active_reg <= tx_active_new; + end + end + end // reg_update + + //---------------------------------------------------------------- + // rx_engine + //---------------------------------------------------------------- + always @* + begin: rx_engine + rx_ack_new = 0; + rx_ack_we = 0; + rx_ptr_new = 0; + rx_ptr_we = 0; + rx_ctrl_new = 0; + rx_ctrl_we = 0; + block_new = 0; + block_we = 0; + init_new = 0; + init_we = 0; + next_new = 0; + next_we = 0; + initnext_new = 0; + initnext_we = 0; + + if (tx_active_reg) + begin + initnext_we = 1; + end + + case (rx_ctrl_reg) + RX_INIT: + if (core_ready) + begin + rx_ctrl_new = RX_SYN; + rx_ctrl_we = 1; + end + RX_SYN: + if (rx_syn) + begin + rx_ack_new = 1; + rx_ack_we = 1; + block_new = rx_data; + block_we = 1; + rx_ctrl_new = RX_ACK; + rx_ctrl_we = 1; + end + RX_ACK: + if (!rx_syn) + begin + rx_ack_new = 0; + rx_ack_we = 1; + rx_ptr_new = rx_ptr_reg + 1; + rx_ptr_we = 1; + rx_ctrl_new = RX_SYN; + rx_ctrl_we = 1; + if (rx_ptr_new == BLOCK_BYTES) + begin + rx_ptr_new = 0; + rx_ctrl_new = RX_WAIT; + if (initnext_reg == 0) + begin + init_new = 1; + init_we = 1; + initnext_new = 1; + initnext_we = 1; + end + else + begin + next_new = 1; + next_we = 1; + end + end + end + RX_WAIT: + if (!core_ready) + begin + init_new = 0; + init_we = 1; + next_new = 0; + next_we = 1; + rx_ctrl_new = RX_INIT; + rx_ctrl_we = 1; + end + endcase // case (rx_ctrl_reg) + end // rx_engine + + //---------------------------------------------------------------- + // tx_engine + //---------------------------------------------------------------- + always @* + begin: tx_engine + tx_syn_new = 0; + tx_syn_we = 0; + tx_ptr_new = 0; + tx_ptr_we = 0; + tx_ctrl_new = 0; + tx_ctrl_we = 0; + tx_active_new = 0; + tx_active_we = 0; + + case (tx_ctrl_reg) + TX_INIT: + if (core_digest_valid) + begin + tx_ctrl_new = TX_SYN; + tx_ctrl_we = 1; + end + TX_SYN: + begin + tx_syn_new = 1; + tx_syn_we = 1; + tx_ctrl_new = TX_ACK; + tx_ctrl_we = 1; + end + TX_ACK: + if (!core_digest_valid) + begin + tx_syn_new = 0; + tx_syn_we = 1; + tx_ptr_new = 0; + tx_ptr_we = 1; + tx_ctrl_new = TX_INIT; + tx_ctrl_we = 1; + end + else if (tx_ack) + begin + tx_active_new = 1; + tx_active_we = 1; + tx_syn_new = 0; + tx_syn_we = 1; + tx_ptr_new = tx_ptr_reg + 1; + tx_ptr_we = 1; + tx_ctrl_new = TX_SYN; + tx_ctrl_we = 1; + if (tx_ptr_new == DIGEST_BYTES) + begin + tx_active_new = 0; + tx_ptr_new = 0; + tx_ctrl_new = TX_INIT; + end + end + endcase // case (tx_ctrl_reg) + end // tx_engine + +endmodule // sha256 + +//====================================================================== +// EOF sha256.v +//====================================================================== diff --git a/src/rtl/sha512.v b/src/rtl/sha512.v new file mode 100644 index 0000000..9e9b3d5 --- /dev/null +++ b/src/rtl/sha512.v @@ -0,0 +1,497 @@ +//====================================================================== +// +// sha512.v +// -------- +// Top level wrapper for the SHA-512 hash function providing +// a simple write()/read() interface with 8 bit data access. +// +// +// Authors: Joachim Strombergson, Paul Selkirk +// Copyright (c) 2014, SUNET +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module sha512( + // Clock and reset. + input wire clk, + input wire reset_n, + + // SHA-512 mode + input wire [1 : 0] mode, + + // Interface to communication core + input wire rx_syn, + input wire [7 : 0] rx_data, + output wire rx_ack, + + output wire tx_syn, + output wire [7 : 0] tx_data, + input wire tx_ack + ); + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter RX_INIT = 0; + parameter RX_SYN = 1; + parameter RX_ACK = 2; + parameter RX_WAIT = 3; + + parameter TX_INIT = 0; + parameter TX_SYN = 1; + parameter TX_ACK = 2; + + parameter MODE_SHA_512_224 = 2'h0; + parameter MODE_SHA_512_256 = 2'h1; + parameter MODE_SHA_384 = 2'h2; + parameter MODE_SHA_512 = 2'h3; + + parameter BLOCK_BITS = 1024; + parameter BLOCK_BYTES = BLOCK_BITS / 8; + parameter DIGEST_BITS = 512; + parameter DIGEST_BYTES = DIGEST_BITS / 8; + parameter DIGEST_BYTES_512_224 = 224 / 8; + parameter DIGEST_BYTES_512_256 = 256 / 8; + parameter DIGEST_BYTES_384 = 384 / 8; + parameter DIGEST_BYTES_512 = 512 / 8; + + //---------------------------------------------------------------- + // Registers including update variables and write enable. + //---------------------------------------------------------------- + reg rx_ack_reg; + reg rx_ack_new; + reg rx_ack_we; + + reg [6 : 0] rx_ptr_reg; + reg [7 : 0] rx_ptr_new; + reg rx_ptr_we; + + reg [1 : 0] rx_ctrl_reg; + reg [1 : 0] rx_ctrl_new; + reg rx_ctrl_we; + + reg [7 : 0] block_reg [0 : BLOCK_BYTES - 1]; + reg [7 : 0] block_new; + reg block_we; + + reg init_reg; + reg init_new; + reg init_we; + + reg next_reg; + reg next_new; + reg next_we; + + reg initnext_reg; + reg initnext_new; + reg initnext_we; + + reg tx_syn_reg; + reg tx_syn_new; + reg tx_syn_we; + + reg [6 : 0] tx_ptr_reg; + reg [7 : 0] tx_ptr_new; + reg tx_ptr_we; + + reg [1 : 0] tx_ctrl_reg; + reg [1 : 0] tx_ctrl_new; + reg tx_ctrl_we; + + reg tx_active_reg; + reg tx_active_new; + reg tx_active_we; + + wire [7 : 0] digest_reg [0 : DIGEST_BYTES - 1]; + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + wire core_init; + wire core_next; + wire core_ready; + wire [BLOCK_BITS - 1 : 0] core_block; + wire [DIGEST_BITS - 1 : 0] core_digest; + wire core_digest_valid; + + //---------------------------------------------------------------- + // Concurrent connectivity for ports etc. + //---------------------------------------------------------------- + assign core_init = init_reg; + assign core_next = next_reg; + assign core_block = {block_reg[0], block_reg[1], block_reg[2], block_reg[3], + block_reg[4], block_reg[5], block_reg[6], block_reg[7], + block_reg[8], block_reg[9], block_reg[10], block_reg[11], + block_reg[12], block_reg[13], block_reg[14], block_reg[15], + block_reg[16], block_reg[17], block_reg[18], block_reg[19], + block_reg[20], block_reg[21], block_reg[22], block_reg[23], + block_reg[24], block_reg[25], block_reg[26], block_reg[27], + block_reg[28], block_reg[29], block_reg[30], block_reg[31], + block_reg[32], block_reg[33], block_reg[34], block_reg[35], + block_reg[36], block_reg[37], block_reg[38], block_reg[39], + block_reg[40], block_reg[41], block_reg[42], block_reg[43], + block_reg[44], block_reg[45], block_reg[46], block_reg[47], + block_reg[48], block_reg[49], block_reg[50], block_reg[51], + block_reg[52], block_reg[53], block_reg[54], block_reg[55], + block_reg[56], block_reg[57], block_reg[58], block_reg[59], + block_reg[60], block_reg[61], block_reg[62], block_reg[63], + block_reg[64], block_reg[65], block_reg[66], block_reg[67], + block_reg[68], block_reg[69], block_reg[70], block_reg[71], + block_reg[72], block_reg[73], block_reg[74], block_reg[75], + block_reg[76], block_reg[77], block_reg[78], block_reg[79], + block_reg[80], block_reg[81], block_reg[82], block_reg[83], + block_reg[84], block_reg[85], block_reg[86], block_reg[87], + block_reg[88], block_reg[89], block_reg[90], block_reg[91], + block_reg[92], block_reg[93], block_reg[94], block_reg[95], + block_reg[96], block_reg[97], block_reg[98], block_reg[99], + block_reg[100], block_reg[101], block_reg[102], block_reg[103], + block_reg[104], block_reg[105], block_reg[106], block_reg[107], + block_reg[108], block_reg[109], block_reg[110], block_reg[111], + block_reg[112], block_reg[113], block_reg[114], block_reg[115], + block_reg[116], block_reg[117], block_reg[118], block_reg[119], + block_reg[120], block_reg[121], block_reg[122], block_reg[123], + block_reg[124], block_reg[125], block_reg[126], block_reg[127]}; + + assign rx_ack = rx_ack_reg; + assign tx_syn = tx_syn_reg; + assign tx_data = digest_reg[tx_ptr_reg]; + + assign digest_reg[0] = core_digest[511 : 504]; + assign digest_reg[1] = core_digest[503 : 496]; + assign digest_reg[2] = core_digest[495 : 488]; + assign digest_reg[3] = core_digest[487 : 480]; + assign digest_reg[4] = core_digest[479 : 472]; + assign digest_reg[5] = core_digest[471 : 464]; + assign digest_reg[6] = core_digest[463 : 456]; + assign digest_reg[7] = core_digest[455 : 448]; + assign digest_reg[8] = core_digest[447 : 440]; + assign digest_reg[9] = core_digest[439 : 432]; + assign digest_reg[10] = core_digest[431 : 424]; + assign digest_reg[11] = core_digest[423 : 416]; + assign digest_reg[12] = core_digest[415 : 408]; + assign digest_reg[13] = core_digest[407 : 400]; + assign digest_reg[14] = core_digest[399 : 392]; + assign digest_reg[15] = core_digest[391 : 384]; + assign digest_reg[16] = core_digest[383 : 376]; + assign digest_reg[17] = core_digest[375 : 368]; + assign digest_reg[18] = core_digest[367 : 360]; + assign digest_reg[19] = core_digest[359 : 352]; + assign digest_reg[20] = core_digest[351 : 344]; + assign digest_reg[21] = core_digest[343 : 336]; + assign digest_reg[22] = core_digest[335 : 328]; + assign digest_reg[23] = core_digest[327 : 320]; + assign digest_reg[24] = core_digest[319 : 312]; + assign digest_reg[25] = core_digest[311 : 304]; + assign digest_reg[26] = core_digest[303 : 296]; + assign digest_reg[27] = core_digest[295 : 288]; + assign digest_reg[28] = core_digest[287 : 280]; + assign digest_reg[29] = core_digest[279 : 272]; + assign digest_reg[30] = core_digest[271 : 264]; + assign digest_reg[31] = core_digest[263 : 256]; + assign digest_reg[32] = core_digest[255 : 248]; + assign digest_reg[33] = core_digest[247 : 240]; + assign digest_reg[34] = core_digest[239 : 232]; + assign digest_reg[35] = core_digest[231 : 224]; + assign digest_reg[36] = core_digest[223 : 216]; + assign digest_reg[37] = core_digest[215 : 208]; + assign digest_reg[38] = core_digest[207 : 200]; + assign digest_reg[39] = core_digest[199 : 192]; + assign digest_reg[40] = core_digest[191 : 184]; + assign digest_reg[41] = core_digest[183 : 176]; + assign digest_reg[42] = core_digest[175 : 168]; + assign digest_reg[43] = core_digest[167 : 160]; + assign digest_reg[44] = core_digest[159 : 152]; + assign digest_reg[45] = core_digest[151 : 144]; + assign digest_reg[46] = core_digest[143 : 136]; + assign digest_reg[47] = core_digest[135 : 128]; + assign digest_reg[48] = core_digest[127 : 120]; + assign digest_reg[49] = core_digest[119 : 112]; + assign digest_reg[50] = core_digest[111 : 104]; + assign digest_reg[51] = core_digest[103 : 96]; + assign digest_reg[52] = core_digest[95 : 88]; + assign digest_reg[53] = core_digest[87 : 80]; + assign digest_reg[54] = core_digest[79 : 72]; + assign digest_reg[55] = core_digest[71 : 64]; + assign digest_reg[56] = core_digest[63 : 56]; + assign digest_reg[57] = core_digest[55 : 48]; + assign digest_reg[58] = core_digest[47 : 40]; + assign digest_reg[59] = core_digest[39 : 32]; + assign digest_reg[60] = core_digest[31 : 24]; + assign digest_reg[61] = core_digest[23 : 16]; + assign digest_reg[62] = core_digest[15 : 8]; + assign digest_reg[63] = core_digest[7 : 0]; + + //---------------------------------------------------------------- + // core instantiation. + //---------------------------------------------------------------- + sha512_core core( + .clk(clk), + .reset_n(reset_n), + + .init(core_init), + .next(core_next), + .mode(mode), + + .block(core_block), + + .ready(core_ready), + + .digest(core_digest), + .digest_valid(core_digest_valid) + ); + + //---------------------------------------------------------------- + // reg_update + // Update functionality for all registers in the core. + // All registers are positive edge triggered with synchronous + // active low reset. All registers have write enable. + //---------------------------------------------------------------- + + always @ (posedge clk) + begin: reg_update + if (!reset_n) + begin: reset_reg + reg[7:0] i; + for (i = 0; i < BLOCK_BYTES; i = i + 1) + block_reg[i] <= 0; + rx_ack_reg <= 0; + rx_ptr_reg <= 0; + rx_ctrl_reg <= RX_INIT; + tx_syn_reg <= 0; + tx_ptr_reg <= 0; + tx_ctrl_reg <= TX_INIT; + initnext_reg <= 0; + end + else + begin + if (rx_ack_we) + begin + rx_ack_reg <= rx_ack_new; + end + + if (rx_ptr_we) + begin + rx_ptr_reg <= rx_ptr_new[6:0]; + end + + if (rx_ctrl_we) + begin + rx_ctrl_reg <= rx_ctrl_new; + end + + if (block_we) + begin + block_reg[rx_ptr_reg] <= block_new; + end + + if (init_we) + begin + init_reg <= init_new; + end + + if (next_we) + begin + next_reg <= next_new; + end + + if (initnext_we) + begin + initnext_reg <= initnext_new; + end + + if (tx_syn_we) + begin + tx_syn_reg <= tx_syn_new; + end + + if (tx_ptr_we) + begin + tx_ptr_reg <= tx_ptr_new[6:0]; + end + + if (tx_ctrl_we) + begin + tx_ctrl_reg <= tx_ctrl_new; + end + + if (tx_active_we) + begin + tx_active_reg <= tx_active_new; + end + end + end // reg_update + + //---------------------------------------------------------------- + // rx_engine + //---------------------------------------------------------------- + always @* + begin: rx_engine + rx_ack_new = 0; + rx_ack_we = 0; + rx_ptr_new = 0; + rx_ptr_we = 0; + rx_ctrl_new = 0; + rx_ctrl_we = 0; + block_new = 0; + block_we = 0; + init_new = 0; + init_we = 0; + next_new = 0; + next_we = 0; + initnext_new = 0; + initnext_we = 0; + + if (tx_active_reg) + begin + initnext_we = 1; + end + + case (rx_ctrl_reg) + RX_INIT: + if (core_ready) + begin + rx_ctrl_new = RX_SYN; + rx_ctrl_we = 1; + end + RX_SYN: + if (rx_syn) + begin + rx_ack_new = 1; + rx_ack_we = 1; + block_new = rx_data; + block_we = 1; + rx_ctrl_new = RX_ACK; + rx_ctrl_we = 1; + end + RX_ACK: + if (!rx_syn) + begin + rx_ack_new = 0; + rx_ack_we = 1; + rx_ptr_new = rx_ptr_reg + 1; + rx_ptr_we = 1; + rx_ctrl_new = RX_SYN; + rx_ctrl_we = 1; + if (rx_ptr_new == BLOCK_BYTES) + begin + rx_ptr_new = 0; + rx_ctrl_new = RX_WAIT; + if (initnext_reg == 0) + begin + init_new = 1; + init_we = 1; + initnext_new = 1; + initnext_we = 1; + end + else + begin + next_new = 1; + next_we = 1; + end + end + end + RX_WAIT: + if (!core_ready) + begin + init_new = 0; + init_we = 1; + next_new = 0; + next_we = 1; + rx_ctrl_new = RX_INIT; + rx_ctrl_we = 1; + end + endcase // case (rx_ctrl_reg) + end // rx_engine + + //---------------------------------------------------------------- + // tx_engine + //---------------------------------------------------------------- + always @* + begin: tx_engine + tx_syn_new = 0; + tx_syn_we = 0; + tx_ptr_new = 0; + tx_ptr_we = 0; + tx_ctrl_new = 0; + tx_ctrl_we = 0; + tx_active_new = 0; + tx_active_we = 0; + + case (tx_ctrl_reg) + TX_INIT: + if (core_digest_valid) + begin + tx_ctrl_new = TX_SYN; + tx_ctrl_we = 1; + end + TX_SYN: + begin + tx_syn_new = 1; + tx_syn_we = 1; + tx_ctrl_new = TX_ACK; + tx_ctrl_we = 1; + end + TX_ACK: + if (!core_digest_valid) + begin + tx_syn_new = 0; + tx_syn_we = 1; + tx_ptr_new = 0; + tx_ptr_we = 1; + tx_ctrl_new = TX_INIT; + tx_ctrl_we = 1; + end + else if (tx_ack) + begin + tx_active_new = 1; + tx_active_we = 1; + tx_syn_new = 0; + tx_syn_we = 1; + tx_ptr_new = tx_ptr_reg + 1; + tx_ptr_we = 1; + tx_ctrl_new = TX_SYN; + tx_ctrl_we = 1; + if (((mode == MODE_SHA_512_224) && (tx_ptr_new == DIGEST_BYTES_512_224)) || + ((mode == MODE_SHA_512_256) && (tx_ptr_new == DIGEST_BYTES_512_256)) || + ((mode == MODE_SHA_384) && (tx_ptr_new == DIGEST_BYTES_384)) || + ((mode == MODE_SHA_512) && (tx_ptr_new == DIGEST_BYTES_512))) + begin + tx_active_new = 0; + tx_ptr_new = 0; + tx_ctrl_new = TX_INIT; + end + end + endcase // case (tx_ctrl_reg) + end // tx_engine + +endmodule // sha512 + +//====================================================================== +// EOF sha512.v +//====================================================================== |