| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-02-06 | Adding ports for the core selector to include Cryptech ports. Moving the Cryp... | Joachim Strömbergson |
| 2015-02-06 | Made sure that we name the ports the same as in the ucf. | Joachim Strömbergson |
| 2015-02-06 | Adding a bit of test logic to see that the noise board is properly connected. | Joachim Strömbergson |
| 2015-02-02 | Changing to Verilog 2001 style interface. Changed port names to not have inpo... | Joachim Strömbergson |
| 2015-02-01 | Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise b... | Joachim Strömbergson |
| 2015-02-01 | Added proper file headers to all verilog source files. | Joachim Strömbergson |
| 2015-02-01 | Removed trailing whitespace and ^M. | Joachim Strömbergson |
| 2015-01-31 | Adding all main hw source files and constraints. | Joachim Strömbergson |
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index : test/novena_base | |
| Cryptech Novena FPGA baseline | git repositories |
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