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path: root/rtl/src/verilog/novena_baseline_top.v
AgeCommit message (Expand)Author
2015-02-06Made sure that we name the ports the same as in the ucf.Joachim Strömbergson
2015-02-06Adding a bit of test logic to see that the noise board is properly connected.Joachim Strömbergson
2015-02-02Changing to Verilog 2001 style interface. Changed port names to not have inpo...Joachim Strömbergson
2015-02-01Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise b...Joachim Strömbergson
2015-02-01Added proper file headers to all verilog source files.Joachim Strömbergson
2015-02-01Removed trailing whitespace and ^M.Joachim Strömbergson
2015-01-31Adding all main hw source files and constraints.Joachim Strömbergson