| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-02-01 | Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files. | Joachim StroĢmbergson | |
| 2015-01-31 | Adding all main hw source files and constraints. | Joachim StroĢmbergson | |
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index : test/novena_base | |
| Cryptech Novena FPGA baseline | git repositories |
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