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Cryptech Novena FPGA baseline
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2015-02-06
Made sure that we name the ports the same as in the ucf.
Joachim Strömbergson
2015-02-06
Adding a bit of test logic to see that the noise board is properly connected.
Joachim Strömbergson
2015-02-05
Removed space between text and semicolon.
Joachim Strömbergson
2015-02-05
Adding ports for cryptech noise sources.
Joachim Strömbergson
2015-02-05
Adding pins for the LEDs on the Cryptech avalanche noise board.
Joachim Strömbergson
2015-02-03
use standard int types
Paul Selkirk
2015-02-03
reformat C code slightly
Paul Selkirk
2015-02-02
add a command-line build, for those who like that sort of thing
Paul Selkirk
2015-02-02
update project file paths to .v and .ucf files
Paul Selkirk
2015-02-02
Changing to Verilog 2001 style interface. Changed port names to not have ↵
Joachim Strömbergson
inports called ootput etc. Read and write is better.
2015-02-01
Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise ↵
Joachim Strömbergson
board. Fixed layout.
2015-02-01
Added header with license and info to the constraint file.
Joachim Strömbergson
2015-02-01
Updated README with more info about the base.
Joachim Strömbergson
2015-02-01
Changed file type.
Joachim Strömbergson
2015-02-01
Added proper file headers to all verilog source files.
Joachim Strömbergson
2015-02-01
Removed trailing whitespace and ^M.
Joachim Strömbergson
2015-02-01
Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.
Joachim Strömbergson
2015-02-01
Removed trailing whitespace and DOS ^M.
Joachim Strömbergson
2015-01-31
Adding license for the project.
Joachim Strömbergson
2015-01-31
Adding all main hw source files and constraints.
Joachim Strömbergson
2015-01-31
Removed exe bit on source files.
Joachim Strömbergson
2015-01-31
Adding initial version of the sw parts of the baseline.
Joachim Strömbergson
2015-01-31
Adding documentation.
Joachim Strömbergson
2015-01-31
Adding readme to explain the contents of the new repo.
Joachim Strömbergson